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0f65e8f6cc
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final submit
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2023-08-17 11:31:28 +08:00 |
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f17a44883f
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[Tag] pack submit
初赛提交包
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2023-08-04 16:20:04 +08:00 |
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f87199d467
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[Modified] pre submit file organization
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2023-08-04 16:10:30 +08:00 |
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df11c3a4ab
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[Modified] fix axi, pass func & pref test, but down to 85MHz
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2023-08-01 14:30:11 +08:00 |
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9f40b5f1bb
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[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test
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2023-07-31 16:05:29 +08:00 |
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b38d04cc35
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[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
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2023-07-29 21:16:28 +08:00 |
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3a070d35fc
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[Add] switch to 7-stage and pass func test
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2023-07-28 15:29:06 +08:00 |
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bf2dd4655b
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[Backup] ready for switching to 7-stage pipline
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2023-07-25 21:06:44 +08:00 |
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0352651836
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[Modified] fix bug & pass pref test on board
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2023-07-24 02:46:27 +08:00 |
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27ef99503d
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[Add] add ext_int
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2023-07-23 01:59:53 +08:00 |
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3e9b7e2b29
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Merge branch 'main' of github.com:bLueriVerLHR/neulacpu
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2023-07-23 01:12:18 +08:00 |
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d3af55af89
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[Modified] Fix (铸币←me) bug & up to 60MHz
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2023-07-23 01:10:46 +08:00 |
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bLueriVerLHR
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e31ce6bea5
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[Add] add la vmlinux
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2023-07-22 15:08:33 +08:00 |
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93a2528623
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Merge branch 'main' of github.com:bLueriVerLHR/neulacpu
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2023-07-22 14:58:11 +08:00 |
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4c9c2ddd78
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[Modified] Debug & board test with cache & pass n58 with 40 MHz
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2023-07-22 14:56:53 +08:00 |
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bLueriVerLHR
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1811d54f49
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[Modified] update makefile
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2023-07-22 02:02:10 +08:00 |
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bLueriVerLHR
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82f8712de1
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[Modified] rm la32r toolchain fxk it
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2023-07-22 01:28:32 +08:00 |
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bLueriVerLHR
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ff61889138
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[Modified] change toolchain to la32r
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2023-07-21 14:29:21 +08:00 |
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a755aae99e
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[Modified] Switch soc_top&board to axi&xc7a200t
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2023-07-20 21:40:21 +08:00 |
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bLueriVerLHR
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104518d875
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[Update] chg rv to la
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2023-07-20 18:43:45 +08:00 |
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bLueriVerLHR
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29abfe4101
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[Update] xv6-la init
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2023-07-20 18:06:22 +08:00 |
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bLueriVerLHR
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f683f3bed1
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[Add] add xv6-rv
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2023-07-20 17:48:37 +08:00 |
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bLueriVerLHR
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32e948a593
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[Add] import xv6-riscv and submodules
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2023-07-20 17:47:07 +08:00 |
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bLueriVerLHR
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72c2b73ded
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[Modified] rm redundant files
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2023-07-20 17:22:27 +08:00 |
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1b4c6eee10
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[Add] add icache dcache axi & pass test n46(before syscall)
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2023-07-20 17:19:04 +08:00 |
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yunlanglang
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60d8c35fef
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add the tlb.v
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2023-07-18 20:21:52 +08:00 |
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1bf8be3a27
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[Modifided] update lacpu readme.md & 58 Functional Test Point PASS
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2023-07-02 15:51:35 +08:00 |
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441df2d19b
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[Modifided] fix bugs & 56 Functional Test Point PASS
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2023-07-02 15:49:42 +08:00 |
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ca6e76f22c
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[Modified] Update lacpu readme.md
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2023-06-29 16:43:35 +08:00 |
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e11ddb23e6
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[Modified] Fix bugs & 47 Functional Test Point PASS
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2023-06-29 16:36:11 +08:00 |
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7a879edcb6
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[Modified] Fix bugs & 46 Functional Test Point PASS
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2023-06-26 20:30:39 +08:00 |
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38f1ea7eda
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[Modified] Fix bugs & 36 Functional Test Point PASS
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2023-06-26 17:14:26 +08:00 |
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7c1a1db436
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Merge branch 'main' of github.com:bLueriVerLHR/neulacpu
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2023-06-26 15:13:31 +08:00 |
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78fe1f6cf5
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[Modified] Fix bugs & 29 Functional Test Point PASS
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2023-06-26 15:11:31 +08:00 |
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bLueriVerLHR
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c931384e30
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[update] os
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2023-06-26 09:56:22 +08:00 |
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75644e4920
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[Modified] Rewrite pipeline structure & finish exp11 test
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2023-06-22 19:36:05 +08:00 |
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8d1aa17074
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[Modified] Change branch site, without stall (need 1 stall)
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2023-06-12 15:36:00 +08:00 |
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f592606196
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[Modified] Fix louduse
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2023-06-08 16:27:48 +08:00 |
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e8926ed8a4
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[Modified] fix some bug and small change for test
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2023-06-08 14:08:06 +08:00 |
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d3df7c858f
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[Modified] remove div diu ip use div.v instead
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2023-06-06 15:18:34 +08:00 |
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2921d3733c
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[Modified] change filename mycpu.h to mycpu.vh
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2023-06-06 13:46:34 +08:00 |
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df981a178c
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[Modified] change div divu ip position form soc_top to exe_stage
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2023-06-06 11:30:52 +08:00 |
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f660bd337b
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[Modified] finish loaduse & fix little bug
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2023-05-29 11:53:25 +08:00 |
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144623175a
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[Add] add loaduse.v & fix little bug
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2023-05-28 16:53:31 +08:00 |
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3b43e06054
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[Add] add div.w[u], mod.w[u]
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2023-05-27 23:52:30 +08:00 |
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9a72e27ca4
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[Add] add div ip only (not use)
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2023-05-23 12:59:04 +08:00 |
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c2c4f09c30
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[add] add div ip only (not use)
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2023-05-23 12:57:10 +08:00 |
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115d0492da
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[Add] add op_mu.wl, op_mulh.w[u]
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2023-05-23 12:09:45 +08:00 |
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bf41b61af0
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[Add] add forwarding
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2023-05-22 13:34:31 +08:00 |
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bLueriVerLHR
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029a8823f4
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[Add] laos base boot
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2023-05-21 00:48:04 +08:00 |
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