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[Modified] pre submit file organization

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包焕垲
2023-08-04 16:10:30 +08:00
parent df11c3a4ab
commit f87199d467
35 changed files with 98 additions and 5939 deletions
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.gitignore vendored
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@@ -11,10 +11,10 @@ ext/
/lacpu/rtl/xilinx_ip/axi_crossbar_1x2/*
/lacpu/rtl/xilinx_ip/axi_ram/*
/lacpu/rtl/xilinx_ip/clk_pll/*
/lacpu/rtl/xilinx_ip/data_bram_bank/*
/lacpu/rtl/xilinx_ip/data_sram_bank/*
!/lacpu/rtl/xilinx_ip/axi_crossbar_1x2/axi_crossbar_1x2.xci
!/lacpu/rtl/xilinx_ip/axi_ram/axi_ram.xci
!/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci
!/lacpu/rtl/xilinx_ip/data_bram_bank/data_bram_bank.xci
!/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xci

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lacpu/doc/design-初赛.docx Normal file
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lacpu/doc/mycpu性能计算.xlsx
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lacpu/doc/流水线设计.vsdx Normal file
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lacpu/rtl/mycpu/cache_data.v
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@@ -65,7 +65,7 @@ module cache_data_v5
data_bram_bank bank0_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[31:0]:sram_wdata ), // 32
.douta (rdata_way0[0] ) // 32
@@ -73,7 +73,7 @@ module cache_data_v5
data_bram_bank bank1_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[1]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[63:32]:sram_wdata ), // 32
.douta (rdata_way0[1] ) // 32
@@ -81,7 +81,7 @@ module cache_data_v5
data_bram_bank bank2_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[95:64]:sram_wdata ), // 32
.douta (rdata_way0[2] ) // 32
@@ -89,7 +89,7 @@ module cache_data_v5
data_bram_bank bank3_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[3]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[127:96]:sram_wdata ), // 32
.douta (rdata_way0[3] ) // 32
@@ -97,7 +97,7 @@ module cache_data_v5
data_bram_bank bank4_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[159:128]:sram_wdata ), // 32
.douta (rdata_way0[4] ) // 32
@@ -105,7 +105,7 @@ module cache_data_v5
data_bram_bank bank5_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[5]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[191:160]:sram_wdata ), // 32
.douta (rdata_way0[5] ) // 32
@@ -113,7 +113,7 @@ module cache_data_v5
data_bram_bank bank6_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[223:192]:sram_wdata ), // 32
.douta (rdata_way0[6] ) // 32
@@ -121,7 +121,7 @@ module cache_data_v5
data_bram_bank bank7_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[7]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[255:224]:sram_wdata ), // 32
.douta (rdata_way0[7] ) // 32
@@ -399,394 +399,4 @@ module cache_data_v5
};
assign cacheline_old = lru_r ? cacheline_old_way1 : cacheline_old_way0;
endmodule
module cache_data_v6
#(
parameter CACHELINE_WD = 512,
parameter TAG_WD = 21,
parameter HIT_WD = 2
)
(
input clk,
input reset,
input write_back,
input [ 1:0] hit,
input lru,
input cached,
// sram_port
input sram_en,
input [ 3:0] sram_we,
input [31:0] sram_addr,
input [31:0] sram_wdata,
output [63:0] sram_rdata,
// axi
input refresh,
input [CACHELINE_WD -1:0] cacheline_new,
output [CACHELINE_WD -1:0] cacheline_old
);
wire [31 :0] rdata_way0 [15:0];
wire [31 :0] rdata_way1 [15:0];
wire [TAG_WD -2:0] tag;
wire [5 :0] index;
wire [5 :0] offset;
reg [HIT_WD- 1:0] hit_r;
reg lru_r;
reg cached_r;
assign {tag,
index,
offset
} = sram_addr;
wire [15:0] bank_sel;
reg [15:0] bank_sel_r;
decoder_4_16 u_decoder_4_16(
.in (offset[5:2] ),
.out (bank_sel )
);
always @ (posedge clk) begin
if (reset) begin
hit_r <= 2'b0;
lru_r <= 1'b0;
cached_r <= 1'b1;
bank_sel_r <= 16'b0;
end
else begin
hit_r <= hit;
lru_r <= lru;
cached_r <= cached;
bank_sel_r <= bank_sel;
end
end
// data_bram_way0 begin
data_bram_bank bank0_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[31:0]:sram_wdata ), // 32
.douta (rdata_way0[0] ) // 32
);
data_bram_bank bank1_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[63:32]:sram_wdata ), // 32
.douta (rdata_way0[1] ) // 32
);
data_bram_bank bank2_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[95:64]:sram_wdata ), // 32
.douta (rdata_way0[2] ) // 32
);
data_bram_bank bank3_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[127:96]:sram_wdata ), // 32
.douta (rdata_way0[3] ) // 32
);
data_bram_bank bank4_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[159:128]:sram_wdata ), // 32
.douta (rdata_way0[4] ) // 32
);
data_bram_bank bank5_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[191:160]:sram_wdata ), // 32
.douta (rdata_way0[5] ) // 32
);
data_bram_bank bank6_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[223:192]:sram_wdata ), // 32
.douta (rdata_way0[6] ) // 32
);
data_bram_bank bank7_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[255:224]:sram_wdata ), // 32
.douta (rdata_way0[7] ) // 32
);
data_bram_bank bank8_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[8]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[287:256]:sram_wdata ), // 32
.douta (rdata_way0[8] ) // 32
);
data_bram_bank bank9_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[8]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[319:288]:sram_wdata ), // 32
.douta (rdata_way0[9] ) // 32
);
data_bram_bank bank10_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[10]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[351:320]:sram_wdata ), // 32
.douta (rdata_way0[10] ) // 32
);
data_bram_bank bank11_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[10]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[383:352]:sram_wdata ), // 32
.douta (rdata_way0[11] ) // 32
);
data_bram_bank bank12_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[12]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[415:384]:sram_wdata ), // 32
.douta (rdata_way0[12] ) // 32
);
data_bram_bank bank13_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[12]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[447:416]:sram_wdata ), // 32
.douta (rdata_way0[13] ) // 32
);
data_bram_bank bank14_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[14]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[479:448]:sram_wdata ), // 32
.douta (rdata_way0[14] ) // 32
);
data_bram_bank bank15_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[14]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[511:480]:sram_wdata ), // 32
.douta (rdata_way0[15] ) // 32
);
// data_bram_way0 end
// data_bram_way1 begin
data_bram_bank bank0_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[31:0]:sram_wdata ), // 32
.douta (rdata_way1[0] ) // 32
);
data_bram_bank bank1_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[63:32]:sram_wdata ), // 32
.douta (rdata_way1[1] ) // 32
);
data_bram_bank bank2_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[95:64]:sram_wdata ), // 32
.douta (rdata_way1[2] ) // 32
);
data_bram_bank bank3_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[127:96]:sram_wdata ), // 32
.douta (rdata_way1[3] ) // 32
);
data_bram_bank bank4_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[159:128]:sram_wdata ), // 32
.douta (rdata_way1[4] ) // 32
);
data_bram_bank bank5_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[191:160]:sram_wdata ), // 32
.douta (rdata_way1[5] ) // 32
);
data_bram_bank bank6_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[223:192]:sram_wdata ), // 32
.douta (rdata_way1[6] ) // 32
);
data_bram_bank bank7_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[255:224]:sram_wdata ), // 32
.douta (rdata_way1[7] ) // 32
);
data_bram_bank bank8_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[8]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[287:256]:sram_wdata ), // 32
.douta (rdata_way1[8] ) // 32
);
data_bram_bank bank9_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[8]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[319:288]:sram_wdata ), // 32
.douta (rdata_way1[9] ) // 32
);
data_bram_bank bank10_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[10]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[351:320]:sram_wdata ), // 32
.douta (rdata_way1[10] ) // 32
);
data_bram_bank bank11_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[10]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[383:352]:sram_wdata ), // 32
.douta (rdata_way1[11] ) // 32
);
data_bram_bank bank12_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[12]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[415:384]:sram_wdata ), // 32
.douta (rdata_way1[12] ) // 32
);
data_bram_bank bank13_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[12]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[447:416]:sram_wdata ), // 32
.douta (rdata_way1[13] ) // 32
);
data_bram_bank bank14_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[14]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[479:448]:sram_wdata ), // 32
.douta (rdata_way1[14] ) // 32
);
data_bram_bank bank15_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[14]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[511:480]:sram_wdata ), // 32
.douta (rdata_way1[15] ) // 32
);
// data_bram_way1 end
wire [63:0] sram_rdata_way0,sram_rdata_way1;
assign sram_rdata_way0 = ~cached_r ? 64'b0 :
bank_sel_r[ 0] ? {rdata_way0[ 1],rdata_way0[ 0]} :
bank_sel_r[ 2] ? {rdata_way0[ 3],rdata_way0[ 2]} :
bank_sel_r[ 4] ? {rdata_way0[ 5],rdata_way0[ 4]} :
bank_sel_r[ 6] ? {rdata_way0[ 7],rdata_way0[ 6]} :
bank_sel_r[ 8] ? {rdata_way0[ 9],rdata_way0[ 8]} :
bank_sel_r[10] ? {rdata_way0[11],rdata_way0[10]} :
bank_sel_r[12] ? {rdata_way0[13],rdata_way0[12]} :
bank_sel_r[14] ? {rdata_way0[15],rdata_way0[14]} : 64'b0;
assign sram_rdata_way1 = ~cached_r ? 64'b0 :
bank_sel_r[ 0] ? {rdata_way1[ 1],rdata_way1[ 0]} :
bank_sel_r[ 2] ? {rdata_way1[ 3],rdata_way1[ 2]} :
bank_sel_r[ 4] ? {rdata_way1[ 5],rdata_way1[ 4]} :
bank_sel_r[ 6] ? {rdata_way1[ 7],rdata_way1[ 6]} :
bank_sel_r[ 8] ? {rdata_way1[ 9],rdata_way1[ 8]} :
bank_sel_r[10] ? {rdata_way1[11],rdata_way1[10]} :
bank_sel_r[12] ? {rdata_way1[13],rdata_way1[12]} :
bank_sel_r[14] ? {rdata_way1[15],rdata_way1[14]} : 64'b0;
assign sram_rdata = hit_r[0] ? sram_rdata_way0 :
hit_r[1] ? sram_rdata_way1 : 64'b0;
wire [CACHELINE_WD -1:0] cacheline_old_way0, cacheline_old_way1;
assign cacheline_old_way0 = {
rdata_way0[15],
rdata_way0[14],
rdata_way0[13],
rdata_way0[12],
rdata_way0[11],
rdata_way0[10],
rdata_way0[ 9],
rdata_way0[ 8],
rdata_way0[ 7],
rdata_way0[ 6],
rdata_way0[ 5],
rdata_way0[ 4],
rdata_way0[ 3],
rdata_way0[ 2],
rdata_way0[ 1],
rdata_way0[ 0]
};
assign cacheline_old_way1 = {
rdata_way1[15],
rdata_way1[14],
rdata_way1[13],
rdata_way1[12],
rdata_way1[11],
rdata_way1[10],
rdata_way1[ 9],
rdata_way1[ 8],
rdata_way1[ 7],
rdata_way1[ 6],
rdata_way1[ 5],
rdata_way1[ 4],
rdata_way1[ 3],
rdata_way1[ 2],
rdata_way1[ 1],
rdata_way1[ 0]
};
assign cacheline_old = lru_r ? cacheline_old_way1 : cacheline_old_way0;
endmodule

18
lacpu/rtl/mycpu/csr.v
View File

@@ -63,9 +63,6 @@ module csr(
reg timer_en;
reg [63:0] timer_64;
// reg has_int_r;
// reg [ 1:0] plv_r;
wire inst_sc_w;
wire inst_csrrd;
wire inst_csrwr;
@@ -92,21 +89,6 @@ module csr(
wire va_error;
wire [31:0] bad_va;
// always @(posedge clk) begin
// if(reset) begin
// has_int_r <= 0;
// plv_r <= 0;
// end
// else begin
// has_int_r <= ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
// plv_r <= except_en & !inst_ertn ? 2'b0 :
// inst_ertn ? prmd[`PPLV] :
// csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] :
// crmd[`PLV];
// end
// end
// out TODO!
assign has_int_out = ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
assign plv_out = except_en & !inst_ertn ? 2'b0 :
inst_ertn ? prmd[`PPLV] :

12
lacpu/rtl/mycpu/dcache.v
View File

@@ -33,10 +33,10 @@ module dcache
.reset (reset ),
.flush (1'b0 ),
.stallreq (stallreq_dcache ),
.cached (~dcache_uncached ), // ? TODO from tlb
.sram_en (data_sram_en/* & ~d_refill & ~d_invalid & ~d_modify*/), // TODO!
.cached (~dcache_uncached ),
.sram_en (data_sram_en ),
.sram_we (data_sram_we ),
.sram_addr (data_sram_addr ), // _mmu ?
.sram_addr (data_sram_addr ),
.refresh (dcache_refresh ),
.miss (dcache_miss ),
.axi_raddr (dcache_raddr ),
@@ -52,10 +52,10 @@ module dcache
.write_back (dcache_write_back ),
.hit (dcache_hit ),
.lru (dcache_lru ),
.cached (~dcache_uncached ), // ? from tlb
.sram_en (data_sram_en/* & ~d_refill & ~d_invalid & ~d_modify*/), // TODO!
.cached (~dcache_uncached ),
.sram_en (data_sram_en ),
.sram_we (data_sram_we ),
.sram_addr (data_sram_addr ), // _mmu ?
.sram_addr (data_sram_addr ),
.sram_wdata (data_sram_wdata ),
.sram_rdata (data_sram_rdata ),
.refresh (dcache_refresh ),

2
lacpu/rtl/mycpu/dt.v → lacpu/rtl/mycpu/dt_stage.v
View File

@@ -1,4 +1,4 @@
module dt
module dt_stage
#(
parameter ES_TO_DT_BUS_WD = 340,
parameter DT_TO_MS_BUS_WD = 271,

46
lacpu/rtl/mycpu/exe_stage.v
View File

@@ -13,7 +13,6 @@ module exe_stage
input [ 5:0] stall,
output stallreq_es,
//output stallreq_es_for_cache,
input [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus,
output [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus,
@@ -22,18 +21,9 @@ module exe_stage
input src2_is_forward,
input [31:0] src1_forward_result,
input [31:0] src2_forward_result,
//input [MS_TO_ES_BUS_WD -1:0] dts_to_es_bus,
//input [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus,
//input [MS_TO_ES_BUS_WD -1:0] ms2_to_es_bus,
//input [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus,
output [BR_BUS_WD -1:0] br_bus,
input br_taken_buffer
// output data_sram_en,
// output [ 3:0] data_sram_we,
// output [31:0] data_sram_addr,
// output [31:0] data_sram_wdata
);
reg [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r;
@@ -130,26 +120,6 @@ module exe_stage
inst //31 :0
} = ds_to_es_bus_r;
// assign {dts_reg_we,
// dts_dest,
// dts_result
// } = dts_to_es_bus;
// assign {ms1_reg_we,
// ms1_dest,
// ms1_result
// } = ms1_to_es_bus;
// assign {ms2_reg_we,
// ms2_dest,
// ms2_result
// } = ms2_to_es_bus;
// assign {ws_reg_we,
// ws_dest,
// ws_result
// } = ws_to_es_bus;
assign es_to_dts_bus = {data_sram_en ,//339:339
data_sram_we ,//338:335
data_sram_addr ,//334:303
@@ -191,18 +161,10 @@ module exe_stage
end
end
assign src1 = //dts_reg_we & (dts_dest == rj ) & (rj != 1'b0) ? dts_result : // TODO!
//ms1_reg_we & (ms1_dest == rj ) & (rj != 1'b0) ? ms1_result : // TODO!
//ms2_reg_we & (ms2_dest == rj ) & (rj != 1'b0) ? ms2_result :
//ws_reg_we & (ws_dest == rj ) & (rj != 1'b0) ? ws_result :
src1_is_forward ? src1_forward_result :
rj_value;
assign src2 = //dts_reg_we & (dts_dest == rkd) & (rkd != 1'b0) ? dts_result : // TODO!
//ms1_reg_we & (ms1_dest == rkd) & (rkd != 1'b0) ? ms1_result : // TODO!
//ms2_reg_we & (ms2_dest == rkd) & (rkd != 1'b0) ? ms2_result :
//ws_reg_we & (ws_dest == rkd) & (rkd != 1'b0) ? ws_result :
src2_is_forward ? src2_forward_result :
rkd_value;
assign src1 = src1_is_forward ? src1_forward_result :
rj_value;
assign src2 = src2_is_forward ? src2_forward_result :
rkd_value;
assign alu_src1 = src1_is_pc ? es_pc :
src1;

6
lacpu/rtl/mycpu/icache.v
View File

@@ -31,9 +31,9 @@ module icache
.flush (1'b0 ),
.stallreq (stallreq_icache ),
.cached (1'b1 ),
.sram_en (inst_sram_en/* & ~i_refill & ~i_invalid*/ ), // TODO!
.sram_en (inst_sram_en ),
.sram_we (inst_sram_we ),
.sram_addr (inst_sram_addr ), // _mmu ?
.sram_addr (inst_sram_addr ),
.refresh (icache_refresh ),
.miss (icache_miss ),
.axi_raddr (icache_raddr ),
@@ -50,7 +50,7 @@ module icache
.hit (icache_hit ),
.lru (icache_lru ),
.cached (1'b1 ),
.sram_en (inst_sram_en/* & ~i_refill & ~i_invalid*/ ), // TODO!
.sram_en (inst_sram_en ),
.sram_we (inst_sram_we ),
.sram_addr (inst_sram_addr ),
.sram_wdata (inst_sram_wdata ),

43
lacpu/rtl/mycpu/id_stage.v
View File

@@ -30,9 +30,6 @@ module id_stage
reg [31:0] inst_sram_rdata_r;
reg stall_flag;
reg [ 6:0] es_load_buffer;
reg es_csr_buffer;
wire br_flush;
wire [31:0] ds_pc;
@@ -75,13 +72,6 @@ module id_stage
wire [31:0] rj_value;
wire [31:0] rkd_value;
wire [ 4:0] es_dest;
wire es_is_load;
wire es_is_csr;
wire es_reg_we;
wire stallreq_load;
wire stallreq_csr;
wire excp_adef;
wire [31:0] csr_vec_l;
wire [63:0] csr_vec;
@@ -219,37 +209,4 @@ module id_stage
assign rj_value = rf_rdata1;
assign rkd_value = rf_rdata2;
always @ (posedge clk) begin
if (reset) begin
es_load_buffer <= 7'b0;
es_csr_buffer <= 1'b0;
end
else if (flush) begin
es_load_buffer <= 7'b0;
es_csr_buffer <= 1'b0;
end
else if (stall[2]&(!stall[3])) begin
es_load_buffer <= 7'b0;
es_csr_buffer <= 1'b0;
end
else if (!stall[2]) begin
es_load_buffer <= {|load_op, reg_we, dest};
es_csr_buffer <= |csr_op;
end
end
assign {es_is_load,
es_reg_we,
es_dest
} = es_load_buffer;
assign es_is_csr = es_csr_buffer;
//ex段为load指令，且发生数据相关时，id段需要被暂停
assign stallreq_load = es_is_load & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); //TODO?
assign stallreq_csr = es_is_csr & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0));
wire stallreq_forward;
assign stallreq_forward = es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); // TODO!
assign stallreq_ds = stallreq_load | stallreq_csr/* | stallreq_forward*/;
endmodule

8
lacpu/rtl/mycpu/inst_decoder.v
View File

@@ -34,8 +34,6 @@ module inst_decoder(
output csr_wdata_sel,
output [31:0] csr_vec_l,
//output [ 3:0] sel_rf_res,
output reg_we
);
wire dest_is_r1;
@@ -536,10 +534,4 @@ module inst_decoder(
//inst_idle ;
assign excp_ipe = kernel_inst && (csr_plv == 2'b11);
// rf_res from
// assign sel_rf_res[0] = inst_jirl | inst_bl;
// assign sel_rf_res[1] = |load_op;
// assign sel_rf_res[2] = |csr_op;
// assign sel_rf_res[3] = |mul_div_op;
endmodule

2
lacpu/rtl/mycpu/mem_stage.v
View File

@@ -214,7 +214,7 @@ module mem2_stage
(inst_ld_hu & byte_sel[0]) ? { 16'b0, data_temp[15: 0]} :
(inst_ld_hu & byte_sel[2]) ? { 16'b0, data_temp[31:16]} :
(inst_ld_w & byte_sel[0]) ? data_temp :
32'b0; // inst_ll ?
32'b0;
assign {csr_we,
csr_wdata_sel,

10
lacpu/rtl/mycpu/mul.v
View File

@@ -16,6 +16,7 @@ module mul(
wire carry;
wire [63:0] mul_result;
reg [63:0] mul_result_r;
always @ (posedge clk) begin
if (reset) begin
@@ -25,7 +26,7 @@ module mul(
cnt <= cnt - 1;
end
else if (in_valid) begin
cnt <= 1;//32;
cnt <= 2;//32;
end
end
@@ -35,15 +36,18 @@ module mul(
if (reset) begin
result_h <= 0;
result_l <= 0;
mul_result_r <= 0;
end
else if (cnt != 0) begin
//{result_h, result_l} <= {carry, add_result, result_l[31:1]};
result_h <= mul_result[63:32];
result_l <= mul_result[31: 0];
result_h <= mul_result_r[63:32];
result_l <= mul_result_r[31: 0];
mul_result_r <= mul_result;
end
else if (in_valid) begin
result_h <= 0;
result_l <= 0;//b;
mul_result_r <= 0;
end
end

10
lacpu/rtl/mycpu/mul_div_top.v
View File

@@ -32,16 +32,6 @@ module mul_div_top(
wire sign_flag_locked;
wire rem_flag_locked;
//-------------------------
wire [63:0] unsigned_prod;
wire [63:0] signed_prod;
assign unsigned_prod = a * b;
//assign signed_prod = $signed(a) * $signed(b);
//-------------------------
assign mul_en = mul_div_op[0] | mul_div_op[1];
assign div_en = mul_div_op[2] | mul_div_op[3];

2
lacpu/rtl/mycpu/mycpu_core.v
View File

@@ -173,7 +173,7 @@ module mycpu_core
.br_taken_buffer (br_taken_buffer )
);
dt dt(
dt_stage dt_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),

25
lacpu/rtl/mycpu/mycpu_top.v
View File

@@ -52,18 +52,6 @@ module mycpu_top
input bvalid,
output bready,
// // inst sram interface
// output inst_sram_en,
// output [ 3:0] inst_sram_we,
// output [31:0] inst_sram_addr,
// output [31:0] inst_sram_wdata,
// input [31:0] inst_sram_rdata,
// // data sram interface
// output data_sram_en,
// output [ 3:0] data_sram_we,
// output [31:0] data_sram_addr,
// output [31:0] data_sram_wdata,
// input [31:0] data_sram_rdata,
// trace debug interface
output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_we,
@@ -223,25 +211,12 @@ module mycpu_top
end
assign data_sram_rdata = dcache_cached_r ? dcache_temp_rdata : uncache_temp_rdata;
// mmu u_inst_mmu(
// .addr_i (inst_sram_addr ),
// .addr_o (inst_sram_addr_mmu ),
// .cache_v (icache_cached )
// );
mmu data_mmu(
.addr_i (data_sram_addr ),
.addr_o (data_sram_addr_mmu ),
.cache_v (dcache_cached )
);
// cache signal from tlb
// begin
//assign dcache_uncached = 1'b0;
// end
axi_ctrl_v5 axi_ctrl(
.clk (clk ),
.reset (~resetn ),

15
lacpu/rtl/mycpu/pip_ctrl.v
View File

@@ -34,24 +34,11 @@ module pip_ctrl(
flush = 0;
stall = `StallBus'b111111;
end
//id段å<C2B5>‘生暂å<E2809A>œï¼Œæ­¤æ—¶idå<64>Šä¹‹å‰<C3A5>æš‚å<E2809A>?
else if (stallreq_ds) begin
flush = 0;
stall = `StallBus'b000111;
end
// else if(stallreq_fs_for_cache) begin
// flush = 0;
// stall = `StallBus'b000011;
// end
// else if(stallreq_es_for_cache) begin
// flush = 0;
// stall = `StallBus'b011111;
// end
// else if(stallreq_cache) begin
// flush = 0;
// stall = `StallBus'b111111;
// end
else begin
flush = 0;
stall = `StallBus'b000000;

7
lacpu/rtl/mycpu/uncache.v
View File

@@ -50,13 +50,6 @@ module uncache
end
end
// assign rd_req = conf_en & ~valid & ~(|conf_we);
// assign rd_addr = conf_addr;
// assign wr_req = conf_en & ~valid & (|conf_we);
// assign wr_wstrb = conf_we;
// assign wr_addr = conf_addr;
// assign wr_data = conf_wdata;
always @ (posedge clk) begin
if (!resetn) begin
conf_rdata <= 32'b0;

8
lacpu/rtl/xilinx_ip/axi_crossbar_1x2/axi_crossbar_1x2.xci
View File

@@ -1023,10 +1023,10 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_ADDR_WIDTH">0x0000001c0000001d0000001e0000001e000000180000000000000000000000000000001000000010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_BASE_ADDR">0x0000000000000000000000008000000000000000c00000000000000040000000000000001c000000ffffffffffffffffffffffffffffffffffffffffffffffff00000000bfaf0000000000001faf0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_READ_CONNECTIVITY">0x0000000100000001</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_READ_CONNECTIVITY">0xFFFFFFFFFFFFFFFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_READ_ISSUING">0x0000000400000004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_SECURE">0x0000000000000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_WRITE_CONNECTIVITY">0x0000000100000001</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_SECURE">0x00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_WRITE_CONNECTIVITY">0xFFFFFFFFFFFFFFFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_WRITE_ISSUING">0x0000000400000004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_ADDR_RANGES">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MASTER_SLOTS">2</spirit:configurableElementValue>
@@ -2246,7 +2246,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>

10
lacpu/rtl/xilinx_ip/axi_ram/axi_ram.xci
View File

@@ -131,9 +131,9 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">axi_ram.mem</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">axi_ram.mif</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
@@ -172,7 +172,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">../../../../../cdp_ede_local/mycpu_env/func/obj/inst_ram.coe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_ram</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
@@ -189,7 +189,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">READ_FIRST</spirit:configurableElementValue>
@@ -244,7 +244,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>

34
lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci
View File

@@ -98,17 +98,17 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">75.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">90.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">100.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">75.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">90.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">75.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">90.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
@@ -203,16 +203,16 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">42.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">49.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
@@ -251,7 +251,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">12.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
@@ -292,7 +292,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__75.00000______0.000______50.0______146.170____105.461</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__90.00000______0.000______50.0______140.709____105.461</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">timer_clk__100.00000______0.000______50.0______137.681____105.461</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
@@ -393,7 +393,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1866.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">800.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_pll</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
@@ -414,11 +414,11 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">146.170</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">140.709</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">105.461</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">75.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">90.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
@@ -530,7 +530,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
@@ -659,7 +659,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>

BIN
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.dcp
View File

Binary file not shown.

2
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xci
View File

@@ -244,7 +244,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>

192
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xml
View File

@@ -1457,11 +1457,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
<spirit:value>Fri Aug 04 07:02:12 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
<spirit:value>9:2ebdaf5f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1477,11 +1477,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
<spirit:value>Fri Aug 04 07:02:49 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
<spirit:value>9:2ebdaf5f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1492,7 +1492,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
<spirit:value>9:2ebdaf5f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1508,86 +1508,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
<spirit:value>Fri Aug 04 07:02:49 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:949760af</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>data_bram_bank</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:949760af</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_project_archive</spirit:name>
<spirit:displayName>Miscellaneous</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_versioninformation</spirit:name>
<spirit:displayName>Version Information</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
<spirit:value>9:2ebdaf5f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1526,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:57 UTC 2023</spirit:value>
<spirit:value>Fri Aug 04 07:04:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
<spirit:value>9:2ebdaf5f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1619,7 +1544,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1642,7 +1566,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1665,7 +1588,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1688,7 +1610,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1715,7 +1636,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1742,7 +1662,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1769,7 +1688,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1796,7 +1714,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1816,7 +1733,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1839,7 +1755,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1862,7 +1777,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1885,7 +1799,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1912,7 +1825,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1939,7 +1851,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1966,7 +1877,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1993,7 +1903,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2013,7 +1922,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2036,7 +1944,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2059,7 +1966,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2082,7 +1988,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2102,7 +2007,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2126,7 +2030,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2146,7 +2049,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2169,7 +2071,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2192,7 +2093,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2215,7 +2115,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2235,7 +2134,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2255,7 +2153,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2278,7 +2175,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2305,7 +2201,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2332,7 +2227,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2359,7 +2253,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2386,7 +2279,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2413,7 +2305,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2436,7 +2327,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2459,7 +2349,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2483,7 +2372,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2510,7 +2398,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2533,7 +2420,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2556,7 +2442,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2579,7 +2464,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2603,7 +2487,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2627,7 +2510,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2647,7 +2529,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2667,7 +2548,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2694,7 +2574,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2721,7 +2600,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2748,7 +2626,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2775,7 +2652,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2802,7 +2678,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2825,7 +2700,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2848,7 +2722,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2872,7 +2745,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2896,7 +2768,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2920,7 +2791,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2940,7 +2810,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2960,7 +2829,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2980,7 +2848,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3003,7 +2870,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3026,7 +2892,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3049,7 +2914,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3069,7 +2933,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3093,7 +2956,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3569,42 +3431,6 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>simulation/blk_mem_gen_v8_4.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
<spirit:exportedName>blk_mem_gen_v8_4_4</spirit:exportedName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/data_bram_bank.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_project_archive_view_fileset</spirit:name>
<spirit:file>
<spirit:name>summary.log</spirit:name>
<spirit:userFileType>log</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>misc/blk_mem_gen_v8_4.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>doc/blk_mem_gen_v8_4_changelog.txt</spirit:name>
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>

4
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
View File

@@ -1,14 +1,14 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Mon Jul 31 07:02:57 2023
// Date : Fri Aug 4 15:04:01 2023
// Host : BHKLaptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
// Design : data_bram_bank
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a200tfbg676-1
// Device : xc7a200tfbg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

4
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.vhdl
View File

@@ -1,14 +1,14 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Mon Jul 31 07:02:57 2023
-- Date : Fri Aug 4 15:04:01 2023
-- Host : BHKLaptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.vhdl
-- Design : data_bram_bank
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tfbg676-1
-- Device : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

4
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
View File

@@ -1,13 +1,13 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Mon Jul 31 07:02:57 2023
// Date : Fri Aug 4 15:04:01 2023
// Host : BHKLaptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
// Design : data_bram_bank
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tfbg676-1
// Device : xc7a200tfbg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

4
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
View File

@@ -1,13 +1,13 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Mon Jul 31 07:02:57 2023
-- Date : Fri Aug 4 15:04:01 2023
-- Host : BHKLaptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
-- Design : data_bram_bank
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tfbg676-1
-- Device : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

207
lacpu/rtl/xilinx_ip/data_sram_bank/doc/blk_mem_gen_v8_4_changelog.txt
View File

@@ -1,207 +0,0 @@
2019.2:
* Version 8.4 (Rev. 4)
* Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations
2019.1.3:
* Version 8.4 (Rev. 3)
* No changes
2019.1.2:
* Version 8.4 (Rev. 3)
* No changes
2019.1.1:
* Version 8.4 (Rev. 3)
* No changes
2019.1:
* Version 8.4 (Rev. 3)
* General: Internal device family change, no functional changes
2018.3.1:
* Version 8.4 (Rev. 2)
* No changes
2018.3:
* Version 8.4 (Rev. 2)
* Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
* Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
* Other: Internal device family change, no functional changes
2018.2:
* Version 8.4 (Rev. 1)
* No changes
2018.1:
* Version 8.4 (Rev. 1)
* No changes
2017.4:
* Version 8.4 (Rev. 1)
* General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
2017.3:
* Version 8.4
* General: Safety Circuit option is enabled by default if reset option in any one port is enabled
2017.2:
* Version 8.3 (Rev. 6)
* No changes
2017.1:
* Version 8.3 (Rev. 6)
* General: Internal device family change, no functional changes
* General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
2016.4:
* Version 8.3 (Rev. 5)
* General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
2016.3:
* Version 8.3 (Rev. 4)
* Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
* Other: Enable support for future devices
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
2016.2:
* Version 8.3 (Rev. 3)
* updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
* Updated the IP to support the device package changes
2016.1:
* Version 8.3 (Rev. 2)
* Updated the IP to deliver only verilog behavioral model
* Updated the IP to support UltraRAM in IP Integrator
* Updated the IP to support the device package changes
2015.4.2:
* Version 8.3 (Rev. 1)
* No changes
2015.4.1:
* Version 8.3 (Rev. 1)
* No changes
2015.4:
* Version 8.3 (Rev. 1)
* Updated the IP to support the device package changes
2015.3:
* Version 8.3
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
* Simulation models are delivered in VHDL only
2015.2.1:
* Version 8.2 (Rev. 5)
* No changes
2015.2:
* Version 8.2 (Rev. 5)
* No changes
2015.1:
* Version 8.2 (Rev. 5)
* Delivering non encrypted behavioral models
* Supported memory depth is increased up to 1M words
* Added the power saving feature (RDADDRCHG) for ultrascale devices
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 8.2 (Rev. 4)
* Updated the IP to support the device package changes
2014.4:
* Version 8.2 (Rev. 3)
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
* Internal device family change, no functional changes
2014.3:
* Version 8.2 (Rev. 2)
* Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
* Fixed the GUI crash in Simple Dual Port RAM
* Added support of all write modes in Simple Dual Port RAM when ECC is not used
* Increased the supported depth to a maximum value of 256k
2014.2:
* Version 8.2 (Rev. 1)
* Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
2014.1:
* Version 8.2
* Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
* Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
* Added support of the dynamic power saving for ultra-scale devices
* Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
* Internal device family name change, no functional changes
2013.4:
* Version 8.1
* The Primitive output registers are made "ON" by default in the stand alone mode
* Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
* Added support for ultrascale devices
2013.3:
* Version 8.0 (Rev. 2)
* Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator.
* Improved GUI speed and responsivness, no functional changes
* Reduced synthesis and simulation warnings
* Added support for Cadence IES and Synopsys VCS simulators
* Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
* Changed BRAM Interface DIN and DOUT to match bus interface directions.
2013.2:
* Version 8.0 (Rev. 1)
* No Changes
2013.1:
* Version 8.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2019 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

150
lacpu/rtl/xilinx_ip/data_sram_bank/misc/blk_mem_gen_v8_4.vhd
View File

@@ -1,150 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_4_4 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_4_4;
architecture xilinx of blk_mem_gen_v8_4_4 is
begin
end
architecture xilinx;

220
lacpu/rtl/xilinx_ip/data_sram_bank/sim/data_bram_bank.v
View File

@@ -1,220 +0,0 @@
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module data_bram_bank (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [3 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [5 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [31 : 0] dina;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
blk_mem_gen_v8_4_4 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(8),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("data_bram_bank.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(4),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(64),
.C_READ_DEPTH_A(64),
.C_ADDRA_WIDTH(6),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(4),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(64),
.C_READ_DEPTH_B(64),
.C_ADDRB_WIDTH(6),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_READ_LATENCY_A(1),
.C_READ_LATENCY_B(1),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.53845 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(4'B0),
.addrb(6'B0),
.dinb(32'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(4'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule

4522
lacpu/rtl/xilinx_ip/data_sram_bank/simulation/blk_mem_gen_v8_4.v
View File

File diff suppressed because it is too large Load Diff

20
lacpu/rtl/xilinx_ip/data_sram_bank/summary.log
View File

@@ -1,20 +0,0 @@
User Configuration
--------------------------------------------------------------------------------
Algorithm : Minimum_Area
Memory Type : Single_Port_RAM
Port A Read Width : [32]
Port A Write Width : [32]
Memory Depth : [64]
----------------------------------------------------------------------------------
Block RAM resource(s) (18K BRAMs) : [1]
Block RAM resource(s) (36K BRAMs) : [0]
----------------------------------------------------------------------------------
Clock A Frequency : [100]
Port A Enable Rate : [100]
Port A Write Rate : [50]
----------------------------------------------------------------------------------
Estimated Power for IP : 3.53845 mW
----------------------------------------------------------------------------------

40
lacpu/run_vivado/la32r/la32r.xpr
View File

@@ -7,7 +7,7 @@
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="5374406f040d4ef0beb6257db957f456"/>
<Option Name="Part" Val="xc7a200tfbg676-1"/>
<Option Name="Part" Val="xc7a200tfbg676-2"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
@@ -36,13 +36,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="48"/>
<Option Name="WTModelSimExportSim" Val="48"/>
<Option Name="WTQuestaExportSim" Val="48"/>
<Option Name="WTIesExportSim" Val="48"/>
<Option Name="WTVcsExportSim" Val="48"/>
<Option Name="WTRivieraExportSim" Val="48"/>
<Option Name="WTActivehdlExportSim" Val="48"/>
<Option Name="WTXSimExportSim" Val="50"/>
<Option Name="WTModelSimExportSim" Val="50"/>
<Option Name="WTQuestaExportSim" Val="50"/>
<Option Name="WTIesExportSim" Val="50"/>
<Option Name="WTVcsExportSim" Val="50"/>
<Option Name="WTRivieraExportSim" Val="50"/>
<Option Name="WTActivehdlExportSim" Val="50"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -135,7 +135,7 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/dt.v">
<File Path="$PPRDIR/../../rtl/mycpu/dt_stage.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@@ -284,7 +284,7 @@
</File>
<File Path="$PPRDIR/../../rtl/mycpu/tlb.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -403,7 +403,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design">
@@ -417,7 +417,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_pll_synth_1" Type="Ft3:Synth" SrcSet="clk_pll" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_pll_synth_1" IncludeInArchive="true">
<Run Id="clk_pll_synth_1" Type="Ft3:Synth" SrcSet="clk_pll" Part="xc7a200tfbg676-2" ConstrsSet="clk_pll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_pll_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
@@ -427,7 +427,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axi_ram_synth_1" Type="Ft3:Synth" SrcSet="axi_ram" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_ram_synth_1" IncludeInArchive="true">
<Run Id="axi_ram_synth_1" Type="Ft3:Synth" SrcSet="axi_ram" Part="xc7a200tfbg676-2" ConstrsSet="axi_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_ram_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
@@ -437,7 +437,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axi_crossbar_1x2_synth_1" Type="Ft3:Synth" SrcSet="axi_crossbar_1x2" Part="xc7a200tfbg676-1" ConstrsSet="axi_crossbar_1x2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crossbar_1x2_synth_1" IncludeInArchive="true">
<Run Id="axi_crossbar_1x2_synth_1" Type="Ft3:Synth" SrcSet="axi_crossbar_1x2" Part="xc7a200tfbg676-2" ConstrsSet="axi_crossbar_1x2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crossbar_1x2_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
@@ -447,7 +447,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="data_bram_bank_synth_1" Type="Ft3:Synth" SrcSet="data_bram_bank" Part="xc7a200tfbg676-1" ConstrsSet="data_bram_bank" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/data_bram_bank_synth_1" IncludeInArchive="true">
<Run Id="data_bram_bank_synth_1" Type="Ft3:Synth" SrcSet="data_bram_bank" Part="xc7a200tfbg676-2" ConstrsSet="data_bram_bank" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/data_bram_bank_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
@@ -457,7 +457,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
@@ -481,7 +481,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_pll_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Run Id="clk_pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="clk_pll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_pll_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
@@ -498,7 +498,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axi_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Run Id="axi_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="axi_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
@@ -515,7 +515,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axi_crossbar_1x2_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_crossbar_1x2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crossbar_1x2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Run Id="axi_crossbar_1x2_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="axi_crossbar_1x2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crossbar_1x2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
@@ -532,7 +532,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="data_bram_bank_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="data_bram_bank" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="data_bram_bank_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Run Id="data_bram_bank_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="data_bram_bank" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="data_bram_bank_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>