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[Modified] fix some bug and small change for test

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This commit is contained in:
包焕垲
2023-06-08 14:08:06 +08:00
parent d3df7c858f
commit e8926ed8a4
9 changed files with 298 additions and 294 deletions
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12
lacpu/rtl/cpu/exe_stage.v
View File

@@ -62,7 +62,6 @@ module exe_stage(
wire es_src2_is_ms_dest;
wire es_data_is_rf_wdata;
wire lu_to_es_bus_r;
reg loaduse_r;
assign {es_alu_op , //173:155
@@ -106,9 +105,6 @@ module exe_stage(
wire es_inst_modw ;
wire es_inst_divwu;
wire es_inst_modwu;
wire es_inst_mulw;
wire es_inst_mulhw;
wire es_inst_mulhwu;
wire [ 1:0] div_op;
wire div_stall;
@@ -135,7 +131,7 @@ module exe_stage(
assign es_to_lu_bus = {es_dest, es_load_op};
assign es_ready_go = div_stall || loaduse_r;
assign es_ready_go = !(div_stall || loaduse_r);
assign es_allowin = !es_valid || es_ready_go && ms_allowin;
assign es_to_ms_valid = es_valid && es_ready_go;
always @(posedge clk) begin
@@ -146,6 +142,9 @@ module exe_stage(
es_valid <= ds_to_es_valid;
end
if (reset) begin
ds_to_es_bus_r <= 0;
end
if (ds_to_es_valid && es_allowin) begin
ds_to_es_bus_r <= ds_to_es_bus;
end
@@ -216,8 +215,7 @@ module exe_stage(
es_store_op[2] ? es_rf_rdata2 :
32'b0;
assign br_target = (^es_branch_op[5:0]) ? (es_pc + es_imm) :
( es_branch_op[7:6]) ? (es_pc + es_imm) :
assign br_target = (|es_branch_op[7:0]) ? (es_alu_result ) :
( es_branch_op[8] ) ? (es_rf_rdata1 + es_imm) :
0;

109
lacpu/rtl/cpu/id_stage.v
View File

@@ -121,10 +121,6 @@ module id_stage(
wire [ 4:0] rf_raddr2;
wire [31:0] rf_rdata2;
wire rj_eq_rd;
wire rj_lt_rd;
wire rj_ltu_rd;
assign ds_to_es_bus = {alu_op , //173:155
src1_is_pc , //154:154
src2_is_imm , //153:153
@@ -158,7 +154,10 @@ module id_stage(
ds_valid <= fs_to_ds_valid;
end
if (fs_to_ds_valid && ds_allowin) begin
if (reset) begin
fs_to_ds_bus_r <= 0;
end
else if (fs_to_ds_valid && ds_allowin) begin
fs_to_ds_bus_r <= fs_to_ds_bus;
end
end
@@ -174,54 +173,54 @@ module id_stage(
decoder_3_8 u_dec2(.in(op[14:12]), .out(op10_d));
decoder_5_32 u_dec3(.in(ra ), .out(op17_d));
assign inst_addw = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b00000];
assign inst_subw = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b00001];
assign inst_slt = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b00100];
assign inst_sltu = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b00101];
assign inst_nor = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b01000];
assign inst_and = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b01001];
assign inst_or = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b01010];
assign inst_xor = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b01011];
assign inst_sllw = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b01110];
assign inst_srlw = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b01111];
assign inst_sraw = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b10000];
assign inst_slliw = (op[21: 5] == 12'b0000_0000_0100) & op17_d[5'b00001];
assign inst_srliw = (op[21: 5] == 12'b0000_0000_0100) & op17_d[5'b01001];
assign inst_sraiw = (op[21: 5] == 12'b0000_0000_0100) & op17_d[5'b10001];
assign inst_mulw = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b11000];
assign inst_mulhw = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b11001];
assign inst_mulhwu = (op[21: 5] == 12'b0000_0000_0001) & op17_d[5'b11010];
assign inst_divw = (op[21: 5] == 12'b0000_0000_0010) & op17_d[5'b00000];
assign inst_modw = (op[21: 5] == 12'b0000_0000_0010) & op17_d[5'b00001];
assign inst_divwu = (op[21: 5] == 12'b0000_0000_0010) & op17_d[5'b00010];
assign inst_modwu = (op[21: 5] == 12'b0000_0000_0010) & op17_d[5'b00011];
assign inst_slti = (op[21:11] == 7'b0000_001 ) & op10_d[3'b000];
assign inst_sltui = (op[21:11] == 7'b0000_001 ) & op10_d[3'b001];
assign inst_addiw = (op[21:11] == 7'b0000_001 ) & op10_d[3'b010];
assign inst_andi = (op[21:11] == 7'b0000_001 ) & op10_d[3'b101];
assign inst_ori = (op[21:11] == 7'b0000_001 ) & op10_d[3'b110];
assign inst_xori = (op[21:11] == 7'b0000_001 ) & op10_d[3'b111];
assign inst_ldb = (op[21:11] == 7'b0010_100 ) & op10_d[3'b000];
assign inst_ldh = (op[21:11] == 7'b0010_100 ) & op10_d[3'b001];
assign inst_ldw = (op[21:11] == 7'b0010_100 ) & op10_d[3'b010];
assign inst_stb = (op[21:11] == 7'b0010_100 ) & op10_d[3'b100];
assign inst_sth = (op[21:11] == 7'b0010_100 ) & op10_d[3'b101];
assign inst_stw = (op[21:11] == 7'b0010_100 ) & op10_d[3'b110];
assign inst_ldbu = (op[21:11] == 7'b0010_101 ) & op10_d[3'b000];
assign inst_ldhu = (op[21:11] == 7'b0010_101 ) & op10_d[3'b001];
assign inst_lu12iw = (op[21:17] == 4'b0001 ) & op7_d[3'b010];
assign inst_pcaddu12i = (op[21:17] == 4'b0001 ) & op7_d[3'b110];
assign inst_jirl = (op[21:15] == 3'b010 ) & op6_d[3'b011];
assign inst_b = (op[21:15] == 3'b010 ) & op6_d[3'b100];
assign inst_bl = (op[21:15] == 3'b010 ) & op6_d[3'b101];
assign inst_beq = (op[21:15] == 3'b010 ) & op6_d[3'b110];
assign inst_bne = (op[21:15] == 3'b010 ) & op6_d[3'b111];
assign inst_blt = (op[21:15] == 3'b011 ) & op6_d[3'b000];
assign inst_bge = (op[21:15] == 3'b011 ) & op6_d[3'b001];
assign inst_bltu = (op[21:15] == 3'b011 ) & op6_d[3'b010];
assign inst_bgeu = (op[21:15] == 3'b011 ) & op6_d[3'b011];
assign inst_addw = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b00000];
assign inst_subw = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b00001];
assign inst_slt = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b00100];
assign inst_sltu = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b00101];
assign inst_nor = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b01000];
assign inst_and = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b01001];
assign inst_or = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b01010];
assign inst_xor = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b01011];
assign inst_sllw = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b01110];
assign inst_srlw = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b01111];
assign inst_sraw = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b10000];
assign inst_slliw = (op[21:10] == 12'b0000_0000_0100) & op17_d[5'b00001];
assign inst_srliw = (op[21:10] == 12'b0000_0000_0100) & op17_d[5'b01001];
assign inst_sraiw = (op[21:10] == 12'b0000_0000_0100) & op17_d[5'b10001];
assign inst_mulw = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b11000];
assign inst_mulhw = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b11001];
assign inst_mulhwu = (op[21:10] == 12'b0000_0000_0001) & op17_d[5'b11010];
assign inst_divw = (op[21:10] == 12'b0000_0000_0010) & op17_d[5'b00000];
assign inst_modw = (op[21:10] == 12'b0000_0000_0010) & op17_d[5'b00001];
assign inst_divwu = (op[21:10] == 12'b0000_0000_0010) & op17_d[5'b00010];
assign inst_modwu = (op[21:10] == 12'b0000_0000_0010) & op17_d[5'b00011];
assign inst_slti = (op[21:15] == 7'b0000_001 ) & op10_d[3'b000];
assign inst_sltui = (op[21:15] == 7'b0000_001 ) & op10_d[3'b001];
assign inst_addiw = (op[21:15] == 7'b0000_001 ) & op10_d[3'b010];
assign inst_andi = (op[21:15] == 7'b0000_001 ) & op10_d[3'b101];
assign inst_ori = (op[21:15] == 7'b0000_001 ) & op10_d[3'b110];
assign inst_xori = (op[21:15] == 7'b0000_001 ) & op10_d[3'b111];
assign inst_ldb = (op[21:15] == 7'b0010_100 ) & op10_d[3'b000];
assign inst_ldh = (op[21:15] == 7'b0010_100 ) & op10_d[3'b001];
assign inst_ldw = (op[21:15] == 7'b0010_100 ) & op10_d[3'b010];
assign inst_stb = (op[21:15] == 7'b0010_100 ) & op10_d[3'b100];
assign inst_sth = (op[21:15] == 7'b0010_100 ) & op10_d[3'b101];
assign inst_stw = (op[21:15] == 7'b0010_100 ) & op10_d[3'b110];
assign inst_ldbu = (op[21:15] == 7'b0010_101 ) & op10_d[3'b000];
assign inst_ldhu = (op[21:15] == 7'b0010_101 ) & op10_d[3'b001];
assign inst_lu12iw = (op[21:18] == 4'b0001 ) & op7_d[3'b010];
assign inst_pcaddu12i = (op[21:18] == 4'b0001 ) & op7_d[3'b110];
assign inst_jirl = (op[21:19] == 3'b010 ) & op6_d[3'b011];
assign inst_b = (op[21:19] == 3'b010 ) & op6_d[3'b100];
assign inst_bl = (op[21:19] == 3'b010 ) & op6_d[3'b101];
assign inst_beq = (op[21:19] == 3'b010 ) & op6_d[3'b110];
assign inst_bne = (op[21:19] == 3'b010 ) & op6_d[3'b111];
assign inst_blt = (op[21:19] == 3'b011 ) & op6_d[3'b000];
assign inst_bge = (op[21:19] == 3'b011 ) & op6_d[3'b001];
assign inst_bltu = (op[21:19] == 3'b011 ) & op6_d[3'b010];
assign inst_bgeu = (op[21:19] == 3'b011 ) & op6_d[3'b011];
assign alu_op[ 0] = inst_addw | inst_addiw | inst_pcaddu12i | inst_ldb | inst_ldh | inst_ldbu | inst_ldhu | inst_ldw | inst_stb | inst_sth | inst_stw | inst_bl | inst_jirl;
assign alu_op[ 0] = inst_addw | inst_addiw | inst_pcaddu12i | inst_ldb | inst_ldh | inst_ldbu | inst_ldhu | inst_ldw | inst_stb | inst_sth | inst_stw | inst_bl | inst_jirl | inst_b;
assign alu_op[ 1] = inst_subw;
assign alu_op[ 2] = inst_slt | inst_slti;
assign alu_op[ 3] = inst_sltu | inst_sltui;
@@ -248,12 +247,12 @@ module id_stage(
| {32{inst_slliw | inst_srliw | inst_sraiw}} & { 27'b0 , rk}
| {32{inst_b | inst_bl}} & {{4{ds_inst[9]}}, ds_inst[9:0], ds_inst[25:10], 2'b0};
assign src1_is_pc = inst_bl | inst_jirl | inst_pcaddu12i;
assign src1_is_pc = inst_bl | inst_jirl | inst_pcaddu12i | inst_b;
assign src2_is_4 = inst_bl | inst_jirl;
assign src2_is_imm = inst_addiw | inst_lu12iw | inst_pcaddu12i | inst_andi | inst_ori | inst_xori | inst_slliw | inst_srliw | inst_sraiw | inst_ldb | inst_ldh | inst_ldw | inst_ldbu | inst_ldhu | inst_stb | inst_sth | inst_stw | inst_mulhwu | inst_divwu | inst_modwu;
assign src2_is_imm = inst_addiw | inst_lu12iw | inst_pcaddu12i | inst_andi | inst_ori | inst_xori | inst_slliw | inst_srliw | inst_sraiw | inst_ldb | inst_ldh | inst_ldw | inst_ldbu | inst_ldhu | inst_stb | inst_sth | inst_stw | inst_mulhwu | inst_divwu | inst_modwu | inst_b | inst_beq | inst_bne | inst_bge | inst_bgeu | inst_blt | inst_bltu;
assign dst_is_r1 = inst_bl;
assign reg_we = ~(inst_beq | inst_bne | inst_bge | inst_bgeu | inst_blt | inst_bltu | inst_b | inst_stw | inst_sth | inst_stb);
assign reg_we = ~(inst_b | inst_beq | inst_bne | inst_bge | inst_bgeu | inst_blt | inst_bltu | inst_stw | inst_sth | inst_stb);
assign mem_we = inst_stw | inst_sth | inst_stb;
assign mem_to_reg = inst_ldw | inst_ldh | inst_ldb | inst_ldhu | inst_ldbu;
assign load_op = {inst_ldhu, inst_ldbu, inst_ldw, inst_ldh, inst_ldb};

2
lacpu/rtl/cpu/if_stage.v
View File

@@ -54,7 +54,7 @@ module if_stage(
end
if (reset) begin
fs_pc <= 32'h1bffffc; //to make nextpc be 0x1C000000 during reset
fs_pc <= 32'h1bff_fffc; //to make nextpc be 0x1c000000 during reset
end
else if (to_fs_valid && fs_allowin) begin
fs_pc <= nextpc;

21
lacpu/rtl/cpu/mem_stage.v
View File

@@ -87,6 +87,9 @@ module mem_stage(
ms_valid <= es_to_ms_valid;
end
if (reset) begin
es_to_ms_bus_r <= 0;
end
if (es_to_ms_valid && ms_allowin) begin
es_to_ms_bus_r <= es_to_ms_bus;
end
@@ -106,15 +109,15 @@ module mem_stage(
ms_div_op[1] ? mod_result :
ms_alu_result;
assign br_taken = ( ms_branch_op[0] && ms_Zero
|| ms_branch_op[1] && !ms_Zero
|| ms_branch_op[2] && (ms_Sign != ms_Overflow)
|| ms_branch_op[3] && (ms_Zero | (ms_Sign == ms_Overflow))
|| ms_branch_op[4] && ms_Carry
|| ms_branch_op[5] && (ms_Zero | ~ms_Carry )
|| ms_branch_op[6]
|| ms_branch_op[7]
|| ms_branch_op[8]);
assign br_taken = ( ms_branch_op[0] & ms_Zero
| ms_branch_op[1] & !ms_Zero
| ms_branch_op[2] & (ms_Sign != ms_Overflow)
| ms_branch_op[3] & (ms_Zero | (ms_Sign == ms_Overflow))
| ms_branch_op[4] & ms_Carry
| ms_branch_op[5] & (ms_Zero | ~ms_Carry )
| ms_branch_op[6]
| ms_branch_op[7]
| ms_branch_op[8]);
endmodule

422
lacpu/rtl/cpu/cpu_top.v → lacpu/rtl/cpu/mycpu_top.v Executable file → Normal file
View File

@@ -1,211 +1,211 @@
`include "mycpu.vh"
module mycpu_top(
input clk,
input resetn,
// inst sram interface
output inst_sram_en,
output [ 3:0] inst_sram_wen,
output [31:0] inst_sram_addr,
output [31:0] inst_sram_wdata,
input [31:0] inst_sram_rdata,
// data sram interface
output data_sram_en,
output [ 3:0] data_sram_wen,
output [31:0] data_sram_addr,
output [31:0] data_sram_wdata,
input [31:0] data_sram_rdata,
// trace debug interface
output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_wen,
output [ 4:0] debug_wb_rf_wnum,
output [31:0] debug_wb_rf_wdata
);
reg reset;
always @(posedge clk) reset <= ~resetn;
wire ds_allowin;
wire es_allowin;
wire ms_allowin;
wire ws_allowin;
wire fs_to_ds_valid;
wire ds_to_es_valid;
wire es_to_ms_valid;
wire ms_to_ws_valid;
wire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
wire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
wire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
wire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
wire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
wire [`BR_BUS_WD -1:0] br_bus;
wire [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus;
wire [`ES_TO_FW_BUS_WD -1:0] es_to_fw_bus;
wire [`MS_TO_FW_BUS_WD -1:0] ms_to_fw_bus;
wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus;
wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
wire [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus;
wire [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus;
wire lu_to_es_bus;
wire es_div_enable;
wire es_div_sign;
wire [31:0] es_rf_rdata1;
wire [31:0] es_rf_rdata2;
wire div_complete;
wire [31:0] div_result;
wire [31:0] mod_result;
// IF stage
if_stage if_stage(
.clk (clk ),
.reset (reset ),
//allowin
.ds_allowin (ds_allowin ),
//brbus
.br_bus (br_bus ),
//outputs
.fs_to_ds_valid (fs_to_ds_valid ),
.fs_to_ds_bus (fs_to_ds_bus ),
// inst sram interface
.inst_sram_en (inst_sram_en ),
.inst_sram_wen (inst_sram_wen ),
.inst_sram_addr (inst_sram_addr ),
.inst_sram_wdata(inst_sram_wdata),
.inst_sram_rdata(inst_sram_rdata)
);
// ID stage
id_stage id_stage(
.clk (clk ),
.reset (reset ),
//allowin
.es_allowin (es_allowin ),
.ds_allowin (ds_allowin ),
//from fs
.fs_to_ds_valid (fs_to_ds_valid ),
.fs_to_ds_bus (fs_to_ds_bus ),
//to es
.ds_to_es_valid (ds_to_es_valid ),
.ds_to_es_bus (ds_to_es_bus ),
//to rf: for write back
.ws_to_rf_bus (ws_to_rf_bus ),
//to fw
.ds_to_fw_bus (ds_to_fw_bus ),
//to lu
.ds_to_lu_bus (ds_to_lu_bus )
);
// EXE stage
exe_stage exe_stage(
.clk (clk ),
.reset (reset ),
//allowin
.ms_allowin (ms_allowin ),
.es_allowin (es_allowin ),
//from ds
.ds_to_es_valid (ds_to_es_valid ),
.ds_to_es_bus (ds_to_es_bus ),
//to ms
.es_to_ms_valid (es_to_ms_valid ),
.es_to_ms_bus (es_to_ms_bus ),
//from fw
.fw_to_es_bus (fw_to_es_bus ),
//to fw
.es_to_fw_bus (es_to_fw_bus ),
//from ms
.ms_to_ds_bus (ms_to_es_bus ),
//from ws
.ws_to_ds_bus (ws_to_es_bus ),
//to lu
.es_to_lu_bus (es_to_lu_bus ),
//from lu
.lu_to_es_bus (lu_to_es_bus ),
// data sram interface
.data_sram_en (data_sram_en ),
.data_sram_wen (data_sram_wen ),
.data_sram_addr (data_sram_addr ),
.data_sram_wdata(data_sram_wdata),
// div
.es_div_enable (es_div_enable) ,
.es_div_sign (es_div_sign) ,
.es_rf_rdata1 (es_rf_rdata1) ,
.es_rf_rdata2 (es_rf_rdata2) ,
.div_complete (div_complete)
);
// div
div u_div(
.div_clk (clk ),
.reset (reset ),
.div (es_div_enable ),
.div_signed (es_div_sign ),
.x (es_rf_rdata1 ),
.y (es_rf_rdata2 ),
.s (div_result ),
.r (mod_result ),
.complete (div_complete )
);
// MEM stage
mem_stage mem_stage(
.clk (clk ),
.reset (reset ),
//allowin
.ws_allowin (ws_allowin ),
.ms_allowin (ms_allowin ),
//from es
.es_to_ms_valid (es_to_ms_valid ),
.es_to_ms_bus (es_to_ms_bus ),
//to ws
.ms_to_ws_valid (ms_to_ws_valid ),
.ms_to_ws_bus (ms_to_ws_bus ),
//to fs
.br_bus (br_bus ),
//from data-sram
.data_sram_rdata(data_sram_rdata),
//to fw
.ms_to_fw_bus (ms_to_fw_bus ),
//to es
.ms_to_es_bus (ms_to_es_bus ),
//div
.div_result (div_result ),
.mod_result (mod_result )
);
// WB stage
wb_stage wb_stage(
.clk (clk ),
.reset (reset ),
//allowin
.ws_allowin (ws_allowin ),
//from ms
.ms_to_ws_valid (ms_to_ws_valid ),
.ms_to_ws_bus (ms_to_ws_bus ),
//to rf: for write back
.ws_to_rf_bus (ws_to_rf_bus ),
//to es
.ws_to_es_bus (ws_to_es_bus ),
//trace debug interface
.debug_wb_pc (debug_wb_pc ),
.debug_wb_rf_wen (debug_wb_rf_wen ),
.debug_wb_rf_wnum (debug_wb_rf_wnum ),
.debug_wb_rf_wdata(debug_wb_rf_wdata)
);
// Forwarding
forward forward(
.clk (clk ),
.reset (reset ),
.ds_to_fw_bus (ds_to_fw_bus),
.es_to_fw_bus (es_to_fw_bus),
.ms_to_fw_bus (ms_to_fw_bus),
.fw_to_es_bus (fw_to_es_bus)
);
//Loaduse
loaduse loaduse(
.ds_to_lu_bus (ds_to_lu_bus),
.es_to_lu_bus (es_to_lu_bus),
.lu_to_es_bus (lu_to_es_bus)
);
endmodule
`include "mycpu.vh"
module mycpu_top(
input clk,
input resetn,
// inst sram interface
output inst_sram_en,
output [ 3:0] inst_sram_we,
output [31:0] inst_sram_addr,
output [31:0] inst_sram_wdata,
input [31:0] inst_sram_rdata,
// data sram interface
output data_sram_en,
output [ 3:0] data_sram_we,
output [31:0] data_sram_addr,
output [31:0] data_sram_wdata,
input [31:0] data_sram_rdata,
// trace debug interface
output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_we,
output [ 4:0] debug_wb_rf_wnum,
output [31:0] debug_wb_rf_wdata
);
reg reset;
always @(posedge clk) reset <= ~resetn;
wire ds_allowin;
wire es_allowin;
wire ms_allowin;
wire ws_allowin;
wire fs_to_ds_valid;
wire ds_to_es_valid;
wire es_to_ms_valid;
wire ms_to_ws_valid;
wire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
wire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
wire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
wire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
wire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
wire [`BR_BUS_WD -1:0] br_bus;
wire [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus;
wire [`ES_TO_FW_BUS_WD -1:0] es_to_fw_bus;
wire [`MS_TO_FW_BUS_WD -1:0] ms_to_fw_bus;
wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus;
wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
wire [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus;
wire [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus;
wire lu_to_es_bus;
wire es_div_enable;
wire es_div_sign;
wire [31:0] es_rf_rdata1;
wire [31:0] es_rf_rdata2;
wire div_complete;
wire [31:0] div_result;
wire [31:0] mod_result;
// IF stage
if_stage if_stage(
.clk (clk ),
.reset (reset ),
//allowin
.ds_allowin (ds_allowin ),
//brbus
.br_bus (br_bus ),
//outputs
.fs_to_ds_valid (fs_to_ds_valid ),
.fs_to_ds_bus (fs_to_ds_bus ),
// inst sram interface
.inst_sram_en (inst_sram_en ),
.inst_sram_wen (inst_sram_we ),
.inst_sram_addr (inst_sram_addr ),
.inst_sram_wdata(inst_sram_wdata),
.inst_sram_rdata(inst_sram_rdata)
);
// ID stage
id_stage id_stage(
.clk (clk ),
.reset (reset ),
//allowin
.es_allowin (es_allowin ),
.ds_allowin (ds_allowin ),
//from fs
.fs_to_ds_valid (fs_to_ds_valid ),
.fs_to_ds_bus (fs_to_ds_bus ),
//to es
.ds_to_es_valid (ds_to_es_valid ),
.ds_to_es_bus (ds_to_es_bus ),
//to rf: for write back
.ws_to_rf_bus (ws_to_rf_bus ),
//to fw
.ds_to_fw_bus (ds_to_fw_bus ),
//to lu
.ds_to_lu_bus (ds_to_lu_bus )
);
// EXE stage
exe_stage exe_stage(
.clk (clk ),
.reset (reset ),
//allowin
.ms_allowin (ms_allowin ),
.es_allowin (es_allowin ),
//from ds
.ds_to_es_valid (ds_to_es_valid ),
.ds_to_es_bus (ds_to_es_bus ),
//to ms
.es_to_ms_valid (es_to_ms_valid ),
.es_to_ms_bus (es_to_ms_bus ),
//from fw
.fw_to_es_bus (fw_to_es_bus ),
//to fw
.es_to_fw_bus (es_to_fw_bus ),
//from ms
.ms_to_ds_bus (ms_to_es_bus ),
//from ws
.ws_to_ds_bus (ws_to_es_bus ),
//to lu
.es_to_lu_bus (es_to_lu_bus ),
//from lu
.lu_to_es_bus (lu_to_es_bus ),
// data sram interface
.data_sram_en (data_sram_en ),
.data_sram_wen (data_sram_we ),
.data_sram_addr (data_sram_addr ),
.data_sram_wdata(data_sram_wdata),
// div
.es_div_enable (es_div_enable) ,
.es_div_sign (es_div_sign) ,
.es_rf_rdata1 (es_rf_rdata1) ,
.es_rf_rdata2 (es_rf_rdata2) ,
.div_complete (div_complete)
);
// div
div u_div(
.div_clk (clk ),
.reset (reset ),
.div (es_div_enable ),
.div_signed (es_div_sign ),
.x (es_rf_rdata1 ),
.y (es_rf_rdata2 ),
.s (div_result ),
.r (mod_result ),
.complete (div_complete )
);
// MEM stage
mem_stage mem_stage(
.clk (clk ),
.reset (reset ),
//allowin
.ws_allowin (ws_allowin ),
.ms_allowin (ms_allowin ),
//from es
.es_to_ms_valid (es_to_ms_valid ),
.es_to_ms_bus (es_to_ms_bus ),
//to ws
.ms_to_ws_valid (ms_to_ws_valid ),
.ms_to_ws_bus (ms_to_ws_bus ),
//to fs
.br_bus (br_bus ),
//from data-sram
.data_sram_rdata(data_sram_rdata),
//to fw
.ms_to_fw_bus (ms_to_fw_bus ),
//to es
.ms_to_es_bus (ms_to_es_bus ),
//div
.div_result (div_result ),
.mod_result (mod_result )
);
// WB stage
wb_stage wb_stage(
.clk (clk ),
.reset (reset ),
//allowin
.ws_allowin (ws_allowin ),
//from ms
.ms_to_ws_valid (ms_to_ws_valid ),
.ms_to_ws_bus (ms_to_ws_bus ),
//to rf: for write back
.ws_to_rf_bus (ws_to_rf_bus ),
//to es
.ws_to_es_bus (ws_to_es_bus ),
//trace debug interface
.debug_wb_pc (debug_wb_pc ),
.debug_wb_rf_wen (debug_wb_rf_we ),
.debug_wb_rf_wnum (debug_wb_rf_wnum ),
.debug_wb_rf_wdata(debug_wb_rf_wdata)
);
// Forwarding
forward forward(
.clk (clk ),
.reset (reset ),
.ds_to_fw_bus (ds_to_fw_bus),
.es_to_fw_bus (es_to_fw_bus),
.ms_to_fw_bus (ms_to_fw_bus),
.fw_to_es_bus (fw_to_es_bus)
);
//Loaduse
loaduse loaduse(
.ds_to_lu_bus (ds_to_lu_bus),
.es_to_lu_bus (es_to_lu_bus),
.lu_to_es_bus (lu_to_es_bus)
);
endmodule

1
lacpu/rtl/cpu/tools.v
View File

@@ -1,3 +1,4 @@
`default_nettype wire
module decoder_5_32(
input [ 4:0] in,
output [31:0] out

5
lacpu/rtl/cpu/wb_stage.v
View File

@@ -52,7 +52,10 @@ module wb_stage(
else if (ws_allowin) begin
ws_valid <= ms_to_ws_valid;
end
if (reset) begin
ms_to_ws_bus_r <= 0;
end
if (ms_to_ws_valid && ws_allowin) begin
ms_to_ws_bus_r <= ms_to_ws_bus;
end

6
lacpu/rtl/soc_lite_top.v
View File

@@ -40,20 +40,20 @@ module soc_lite_top
.resetn (cpu_resetn), //low active
.inst_sram_en (cpu_inst_en ),
.inst_sram_wen (cpu_inst_wen ),
.inst_sram_we (cpu_inst_wen ),
.inst_sram_addr (cpu_inst_addr ),
.inst_sram_wdata (cpu_inst_wdata),
.inst_sram_rdata (cpu_inst_rdata),
.data_sram_en (cpu_data_en ),
.data_sram_wen (cpu_data_wen ),
.data_sram_we (cpu_data_wen ),
.data_sram_addr (cpu_data_addr ),
.data_sram_wdata (cpu_data_wdata),
.data_sram_rdata (cpu_data_rdata),
//debug
.debug_wb_pc (debug_wb_pc ),
.debug_wb_rf_wen (debug_wb_rf_wen ),
.debug_wb_rf_we (debug_wb_rf_wen ),
.debug_wb_rf_wnum (debug_wb_rf_wnum ),
.debug_wb_rf_wdata(debug_wb_rf_wdata)
);

14
lacpu/run_vivado/la32r/la32r.xpr
View File

@@ -61,13 +61,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/cpu/cpu_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/cpu/div.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -117,6 +110,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/cpu/mycpu_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/cpu/regfile.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>