Commit Graph

Select branches

Hide Pull Requests

main

初赛提交包

Mono Color

• 0f65e8f6cc final submit main UnbalancedCat 2023-08-17 11:31:28 +08:00
• f17a44883f [Tag] pack submit 初赛提交包 UnbalancedCat 2023-08-04 16:20:04 +08:00
• f87199d467 [Modified] pre submit file organization UnbalancedCat 2023-08-04 16:10:30 +08:00
• df11c3a4ab [Modified] fix axi, pass func & pref test, but down to 85MHz UnbalancedCat 2023-08-01 14:30:11 +08:00
• 9f40b5f1bb [Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test UnbalancedCat 2023-07-31 16:05:29 +08:00
• b38d04cc35 [Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test) UnbalancedCat 2023-07-29 21:16:28 +08:00
• 3a070d35fc [Add] switch to 7-stage and pass func test UnbalancedCat 2023-07-28 15:29:06 +08:00
• bf2dd4655b [Backup] ready for switching to 7-stage pipline UnbalancedCat 2023-07-25 21:06:44 +08:00
• 0352651836 [Modified] fix bug & pass pref test on board UnbalancedCat 2023-07-24 02:46:27 +08:00
• 27ef99503d [Add] add ext_int UnbalancedCat 2023-07-23 01:59:53 +08:00
• 3e9b7e2b29 Merge branch 'main' of github.com:bLueriVerLHR/neulacpu UnbalancedCat 2023-07-23 01:12:18 +08:00
• d3af55af89 [Modified] Fix (铸币←me) bug & up to 60MHz UnbalancedCat 2023-07-23 01:10:46 +08:00
• e31ce6bea5 [Add] add la vmlinux bLueriVerLHR 2023-07-22 15:08:20 +08:00
• 93a2528623 Merge branch 'main' of github.com:bLueriVerLHR/neulacpu UnbalancedCat 2023-07-22 14:58:11 +08:00
• 4c9c2ddd78 [Modified] Debug & board test with cache & pass n58 with 40 MHz UnbalancedCat 2023-07-22 14:56:53 +08:00
• 1811d54f49 [Modified] update makefile bLueriVerLHR 2023-07-22 02:02:10 +08:00
• 82f8712de1 [Modified] rm la32r toolchain fxk it bLueriVerLHR 2023-07-22 01:28:32 +08:00
• ff61889138 [Modified] change toolchain to la32r bLueriVerLHR 2023-07-21 14:26:41 +08:00
• a755aae99e [Modified] Switch soc_top&board to axi&xc7a200t UnbalancedCat 2023-07-20 21:40:21 +08:00
• 104518d875 [Update] chg rv to la bLueriVerLHR 2023-07-20 18:43:45 +08:00
• 29abfe4101 [Update] xv6-la init bLueriVerLHR 2023-07-20 18:06:22 +08:00
• f683f3bed1 [Add] add xv6-rv bLueriVerLHR 2023-07-20 17:48:37 +08:00
• 32e948a593 [Add] import xv6-riscv and submodules bLueriVerLHR 2023-07-20 17:47:07 +08:00
• 72c2b73ded [Modified] rm redundant files bLueriVerLHR 2023-07-20 17:22:16 +08:00
• 1b4c6eee10 [Add] add icache dcache axi & pass test n46(before syscall) UnbalancedCat 2023-07-20 17:19:04 +08:00
• 60d8c35fef add the tlb.v yunlanglang 2023-07-18 20:21:52 +08:00
• 1bf8be3a27 [Modifided] update lacpu readme.md & 58 Functional Test Point PASS UnbalancedCat 2023-07-02 15:51:35 +08:00
• 441df2d19b [Modifided] fix bugs & 56 Functional Test Point PASS UnbalancedCat 2023-07-02 15:49:42 +08:00
• ca6e76f22c [Modified] Update lacpu readme.md UnbalancedCat 2023-06-29 16:43:35 +08:00
• e11ddb23e6 [Modified] Fix bugs & 47 Functional Test Point PASS UnbalancedCat 2023-06-29 16:36:11 +08:00
• 7a879edcb6 [Modified] Fix bugs & 46 Functional Test Point PASS UnbalancedCat 2023-06-26 20:30:39 +08:00
• 38f1ea7eda [Modified] Fix bugs & 36 Functional Test Point PASS UnbalancedCat 2023-06-26 17:14:26 +08:00
• 7c1a1db436 Merge branch 'main' of github.com:bLueriVerLHR/neulacpu UnbalancedCat 2023-06-26 15:13:31 +08:00
• 78fe1f6cf5 [Modified] Fix bugs & 29 Functional Test Point PASS UnbalancedCat 2023-06-26 15:11:31 +08:00
• c931384e30 [update] os bLueriVerLHR 2023-06-26 09:56:22 +08:00
• 75644e4920 [Modified] Rewrite pipeline structure & finish exp11 test UnbalancedCat 2023-06-22 19:36:05 +08:00
• 8d1aa17074 [Modified] Change branch site, without stall (need 1 stall) UnbalancedCat 2023-06-12 15:36:00 +08:00
• f592606196 [Modified] Fix louduse UnbalancedCat 2023-06-08 16:27:48 +08:00
• e8926ed8a4 [Modified] fix some bug and small change for test UnbalancedCat 2023-06-08 14:08:06 +08:00
• d3df7c858f [Modified] remove div diu ip use div.v instead UnbalancedCat 2023-06-06 15:18:34 +08:00
• 2921d3733c [Modified] change filename mycpu.h to mycpu.vh UnbalancedCat 2023-06-06 13:46:34 +08:00
• df981a178c [Modified] change div divu ip position form soc_top to exe_stage UnbalancedCat 2023-06-06 11:30:52 +08:00
• f660bd337b [Modified] finish loaduse & fix little bug UnbalancedCat 2023-05-29 11:53:25 +08:00
• 144623175a [Add] add loaduse.v & fix little bug UnbalancedCat 2023-05-28 16:53:31 +08:00
• 3b43e06054 [Add] add div.w[u], mod.w[u] UnbalancedCat 2023-05-27 23:52:30 +08:00
• 9a72e27ca4 [Add] add div ip only (not use) UnbalancedCat 2023-05-23 12:59:04 +08:00
• c2c4f09c30 [add] add div ip only (not use) UnbalancedCat 2023-05-23 12:57:10 +08:00
• 115d0492da [Add] add op_mu.wl, op_mulh.w[u] UnbalancedCat 2023-05-23 12:09:45 +08:00
• bf41b61af0 [Add] add forwarding UnbalancedCat 2023-05-22 13:34:31 +08:00
• 029a8823f4 [Add] laos base boot bLueriVerLHR 2023-05-21 00:48:04 +08:00
• 5d31bf294c [add] laos using xv6-riscv thought bLueriVerLHR 2023-05-18 00:05:52 +08:00
• 399c978c09 [Add] full funtion except execeptions and cache/TLB added bLueriVerLHR 2023-05-14 17:46:12 +08:00
• f3d2382a60 [Modified] little changes about file format and for dpi UnbalancedCat 2023-05-12 23:22:01 +08:00
• bc692afda0 [Modified] little changes for dpi UnbalancedCat 2023-05-12 22:58:45 +08:00
• 70305945e0 [Add] doc add UnbalancedCat 2023-05-12 22:22:42 +08:00
• cf7d106af0 [Modified] meet time limit UnbalancedCat 2023-05-12 22:14:46 +08:00
• 3228082f83 [Modified] little bug fix UnbalancedCat 2023-05-12 21:42:26 +08:00
• d4366a9c7b [Add] la32r cpu framework add UnbalancedCat 2023-05-12 21:00:39 +08:00
• d915fb5f49 [Modified] update .gitignore UnbalancedCat 2023-05-12 20:59:00 +08:00
• cca1da6765 [Modified] change the way we decode and exec bLueriVerLHR 2023-05-12 18:47:34 +08:00
• 5f2016f254 [Downgrade] downgrade example file to 4.0 ver. bLueriVerLHR 2023-05-11 22:34:21 +08:00
• 0bf1c68d94 [Add] software simulator add bLueriVerLHR 2023-05-11 17:55:41 +08:00
• 4e39007d17 [Modified] init laos compile env bLueriVerLHR 2023-05-11 16:10:59 +08:00
• 5fb23889fa [Modified] reorganize the project bLueriVerLHR 2023-05-11 14:17:51 +08:00
• f86bda7b50 [Init] initialize repo bLueriVerLHR 2023-05-11 12:33:10 +08:00
• 7647279185 Initial commit LHR 2023-05-11 11:51:24 +08:00