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[Modified] Fix bugs & 47 Functional Test Point PASS

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This commit is contained in:
包焕垲
2023-06-29 16:36:11 +08:00
parent 7a879edcb6
commit e11ddb23e6
8 changed files with 335 additions and 82 deletions
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104
lacpu/rtl/cpu/csr.hv Normal file
View File

@@ -0,0 +1,104 @@
`define CRMD_ADDR 14'h0
`define PRMD_ADDR 14'h1
`define EUEN_ADDR 14'h2
`define ECFG_ADDR 14'h4
`define ESTAT_ADDR 14'h5
`define ERA_ADDR 14'h6
`define BADV_ADDR 14'h7
`define EENTRY_ADDR 14'hc
`define TLBIDX_ADDR 14'h10
`define TLBEHI_ADDR 14'h11
`define TLBELO0_ADDR 14'h12
`define TLBELO1_ADDR 14'h13
`define ASID_ADDR 14'h18
`define PGDL_ADDR 14'h19
`define PGDH_ADDR 14'h1a
`define PGD_ADDR 14'h1b
`define CPUID_ADDR 14'h20
`define SAVE0_ADDR 14'h30
`define SAVE1_ADDR 14'h31
`define SAVE2_ADDR 14'h32
`define SAVE3_ADDR 14'h33
`define TID_ADDR 14'h40
`define TCFG_ADDR 14'h41
`define TVAL_ADDR 14'h42
`define TICLR_ADDR 14'h44
`define LLBCTL_ADDR 14'h60
`define TLBRENTRY_ADDR 14'h88
`define CTAG_ADDR 14'h98
`define DMW0_ADDR 14'h180
`define DMW1_ADDR 14'h181
//CRMD
`define PLV 1:0
`define IE 2
`define DA 3
`define PG 4
`define DATF 6:5
`define DATM 8:7
//PRMD
`define PPLV 1:0
`define PIE 2
//ECTL
`define LIE 12:0
`define LIE_1 9:0
`define LIE_2 12:11
//ESTAT
`define IS 12:0
`define ECODE 21:16
`define ESUBCODE 30:22
//TLBIDX
`define INDEX 4:0
`define PS 29:24
`define NE 31
//TLBEHI
`define VPPN 31:13
//TLBELO
`define TLB_V 0
`define TLB_D 1
`define TLB_PLV 3:2
`define TLB_MAT 5:4
`define TLB_G 6
`define TLB_PPN 31:8
`define TLB_PPN_EN 27:8 //todo
//ASID
`define TLB_ASID 9:0
//CPUID
`define COREID 8:0
//LLBCTL
`define ROLLB 0
`define WCLLB 1
`define KLO 2
//TCFG
`define EN 0
`define PERIODIC 1
`define INITVAL 31:2
//TICLR
`define CLR 0
//TLBRENTRY
`define TLBRENTRY_PA 31:6
//DMW
`define PLV0 0
`define PLV3 3
`define DMW_MAT 5:4
`define PSEG 27:25
`define VSEG 31:29
//PGDL PGDH PGD
`define BASE 31:12
`define ECODE_INT 6'h0
`define ECODE_PIL 6'h1
`define ECODE_PIS 6'h2
`define ECODE_PIF 6'h3
`define ECODE_PME 6'h4
`define ECODE_PPI 6'h7
`define ECODE_ADEF 6'h8
`define ECODE_ALE 6'h9
`define ECODE_SYS 6'hb
`define ECODE_BRK 6'hc
`define ECODE_INE 6'hd
`define ECODE_IPE 6'he
`define ECODE_FPD 6'hf
`define ECODE_TLBR 6'h3f
`define ESUBCODE_ADEF 9'h0

117
lacpu/rtl/cpu/csr.v
View File

@@ -1,59 +1,33 @@
`define CRMD_ADDR 14'h0
`define PRMD_ADDR 14'h1
`define EUEN_ADDR 14'h2
`define ECFG_ADDR 14'h4
`define ESTAT_ADDR 14'h5
`define ERA_ADDR 14'h6
`define BADV_ADDR 14'h7
`define EENTRY_ADDR 14'hc
`define TLBIDX_ADDR 14'h10
`define TLBEHI_ADDR 14'h11
`define TLBELO0_ADDR 14'h12
`define TLBELO1_ADDR 14'h13
`define ASID_ADDR 14'h18
`define PGDL_ADDR 14'h19
`define PGDH_ADDR 14'h1a
`define PGD_ADDR 14'h1b
`define CPUID_ADDR 14'h20
`define SAVE0_ADDR 14'h30
`define SAVE1_ADDR 14'h31
`define SAVE2_ADDR 14'h32
`define SAVE3_ADDR 14'h33
`define TID_ADDR 14'h40
`define TCFG_ADDR 14'h41
`define TVAL_ADDR 14'h42
`define TICLR_ADDR 14'h44
`define LLBCTL_ADDR 14'h60
`define TLBRENTRY_ADDR 14'h88
`define CTAG_ADDR 14'h98
`define DMW0_ADDR 14'h180
`define DMW1_ADDR 14'h181
`include "csr.hv"
module csr(
input clk,
input reset,
input stall,
input [31:0] pc,
input [31:0] src1,
input csr_we,
input [ 3:0] csr_op,
input [63:0] csr_vec,
input [ 6:0] csr_op,
input [13:0] csr_addr,
input csr_wdata_sel,
input [31:0] csr_wdata,
output [31:0] csr_rdata,
output except_en,
output [31:0] new_pc
output [31:0] new_pc,
output [ 1:0] plv
);
reg [31:0] crmd; // 当前模式信息
reg [31:0] prmd; // 例外前模式信息
reg [31:0] euen; // 扩展部件是能
reg [31:0] crmd; //** 当前模式信息
reg [31:0] prmd; //** 例外前模式信息
reg [31:0] euen; // 扩展部件使能
reg [31:0] ecfg; // 例外配置
reg [31:0] estat; // 例外状态
reg [31:0] era; // 例外返回地址
reg [31:0] estat; //** 例外状态
reg [31:0] era; //** 例外返回地址
reg [31:0] badv; // 出错虚地址
reg [31:0] eentry; // 例外入口地址
reg [31:0] eentry; //** 例外入口地址
reg [31:0] tlbidx; // TLB 索引
reg [31:0] tlbehi; // TLB 表项最高位
reg [31:0] tlbelo0; // TLB 表项低位 0
@@ -63,10 +37,10 @@ module csr(
reg [31:0] pgdh; // 高半地址空间全局目录基址
reg [31:0] pgd; // 全局目录基址
reg [31:0] cpuid; // 处理器编号
reg [31:0] save0; // 数据保存0
reg [31:0] save1; // 数据保存1
reg [31:0] save2; // 数据保存2
reg [31:0] save3; // 数据保存3
reg [31:0] save0; //** 数据保存0
reg [31:0] save1; //** 数据保存1
reg [31:0] save2; //** 数据保存2
reg [31:0] save3; //** 数据保存3
reg [31:0] tid; // 定时器编号
reg [31:0] tcfg; // 定时器配置
reg [31:0] tval; // 定时器值
@@ -87,13 +61,39 @@ module csr(
wire inst_rdcntvl_w;
wire inst_rdcntvh_w;
wire excp_ipe;
wire excp_ine;
wire inst_break;
wire inst_syscall;
wire inst_ertn;
wire [31:0] csr_wdata_temp;
wire [ 5:0] ecode;
wire [ 8:0] esubcode;
assign plv = except_en ? 2'b0 :
inst_ertn ? prmd[`PPLV] :
csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] :
crmd[`PLV];
assign {excp_ipe,
excp_ine,
inst_break,
inst_syscall,
inst_ertn
} = csr_vec[4:0];
assign {ecode,esubcode} = inst_syscall ? {`ECODE_SYS, 9'b0} :
inst_break ? {`ECODE_BRK, 9'b0} :
excp_ine ? {`ECODE_INE, 9'b0} :
excp_ipe ? {`ECODE_IPE, 9'b0} :
15'b0;
assign csr_rdata = csr_rdata_r;
always @(*) begin
if(|csr_addr) begin
if(|csr_op) begin
case(csr_addr)
`CRMD_ADDR : csr_rdata_r <= crmd;
`PRMD_ADDR : csr_rdata_r <= prmd;
@@ -129,7 +129,7 @@ module csr(
endcase
end
else begin
csr_rdata_r <= 32'b0;
//csr_rdata_r <= 32'b0;
end
end
@@ -142,11 +142,11 @@ module csr(
inst_sc_w
} = csr_op;
assign csr_wdata_temp = csr_wdata_sel ? csr_rdata_r : csr_wdata;
assign csr_wdata_temp = csr_wdata_sel ? (src1 & csr_wdata) | (~src1 & csr_rdata_r) : csr_wdata;
always @(posedge clk) begin
if(reset) begin
crmd <= 0;
crmd <= 32'd8;
prmd <= 0;
euen <= 0;
ecfg <= 0;
@@ -178,7 +178,22 @@ module csr(
dmw1 <= 0;
end
else if (except_en) begin
// ?
if(inst_syscall) begin
crmd[ `PLV] <= 2'b0;
crmd[ `IE] <= 1'b0;
prmd[`PPLV] <= crmd[`PLV];
prmd[ `PIE] <= crmd[`IE ];
estat[ `ECODE] <= ecode;
estat[`ESUBCODE] <= esubcode;
era <= pc;
end
else if(inst_ertn) begin
crmd[ `PLV] <= prmd[`PPLV];
crmd[ `IE] <= prmd[`PIE ];
end
end
else if (csr_we) begin
case (csr_addr)
@@ -216,6 +231,8 @@ module csr(
end
end
assign except_en = 1'b0; // TODO!
assign new_pc = era; // TODO!
assign except_en = excp_ipe | excp_ine | inst_break | inst_syscall | inst_ertn;
assign new_pc = inst_syscall ? eentry :
inst_ertn ? era :
32'b0; // TODO!
endmodule

45
lacpu/rtl/cpu/exe_stage.v
View File

@@ -1,8 +1,8 @@
module exe_stage
#(
parameter BR_BUS_WD = 33,
parameter DS_TO_ES_BUS_WD = 237,
parameter ES_TO_MS_BUS_WD = 175,
parameter DS_TO_ES_BUS_WD = 301,
parameter ES_TO_MS_BUS_WD = 271,
parameter MS_TO_ES_BUS_WD = 38,
parameter WS_TO_ES_BUS_WD = 38
)
@@ -29,6 +29,7 @@ module exe_stage
reg [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r;
wire [63:0] csr_vec;
wire [ 6:0] csr_op;
wire csr_wdata_sel;
wire [13:0] csr_addr;
@@ -70,6 +71,7 @@ module exe_stage
wire br_flush;
wire data_sram_en_temp;
wire [ 3:0] data_sram_we_temp;
wire stallreq_for_mul_div;
wire [31:0] mul_div_result;
@@ -79,7 +81,8 @@ module exe_stage
wire [63:0] csr_bus;
assign {csr_op ,//236:230
assign {csr_vec ,//300:237
csr_op ,//236:230
csr_wdata_sel ,//229:229
csr_addr ,//228:215
csr_we ,//214:214
@@ -113,12 +116,14 @@ module exe_stage
ws_result
} = ws_to_es_bus;
assign es_to_ms_bus = {csr_bus ,//174:111
load_op ,//110:105
store_op ,//102:102
reg_we ,//101:101
dest ,//100:96
es_result,//95 :64
assign es_to_ms_bus = {csr_vec ,//270:207
csr_bus ,//206:143
load_op ,//142:137
store_op ,//136:134
reg_we ,//133:133
dest ,//132:128
es_result,//127:96
src1 ,//95 :64
es_pc ,//63 :32
inst //31 :0
};
@@ -177,10 +182,21 @@ module exe_stage
);
wire csr_cancel;
wire csr_cancel_reg;
reg csr_cancel_reg;
assign csr_cancel = 1'b0;
assign csr_cancel_reg = 1'b0; //TODO!
assign csr_cancel = |csr_vec[31:0];
always @ (posedge clk) begin
if (reset) begin
csr_cancel_reg <= 0;
end
else if (flush) begin
csr_cancel_reg <= 0;
end
else if (csr_cancel) begin
csr_cancel_reg <= 1;
end
end
assign br_bus = {br_taken & ~(csr_cancel|csr_cancel_reg),
br_target
@@ -194,11 +210,12 @@ module exe_stage
.imm (imm ),
.data_sram_en (data_sram_en_temp),
.data_sram_we (data_sram_we ),
.data_sram_we (data_sram_we_temp),
.data_sram_addr (data_sram_addr ),
.data_sram_wdata(data_sram_wdata )
);
assign data_sram_en = (csr_cancel|csr_cancel_reg) ? 1'b0 : data_sram_en_temp;
assign data_sram_we = {4{data_sram_en}} & data_sram_we_temp;
// mul_div
mul_div_top u_mul_div_top(
@@ -217,7 +234,7 @@ module exe_stage
(|load_op | |store_op) ? data_sram_addr :
alu_result;
assign csr_wdata = csr_wdata_sel ? imm : src1;
assign csr_wdata = src2;
assign csr_bus = {csr_we,
csr_wdata_sel,
csr_op,

13
lacpu/rtl/cpu/id_stage.v
View File

@@ -1,7 +1,7 @@
module id_stage
#(
parameter FS_TO_DS_BUS_WD = 32,
parameter DS_TO_ES_BUS_WD = 237,
parameter DS_TO_ES_BUS_WD = 301,
parameter WS_TO_RF_BUS_WD = 38
)
(
@@ -17,6 +17,7 @@ module id_stage
input pc_valid,
input [31:0] inst_sram_rdata,
input [31:0] csr_vec_h,
input [ 1:0] csr_plv,
input [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus,
input [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus,
@@ -87,11 +88,12 @@ module id_stage
rf_wdata //31:0
} = ws_to_rf_bus;
wire csr_vec_l;
assign csr_vec_l = 0; //TODO!
wire [31:0] csr_vec_l;
wire [63:0] csr_vec;
assign csr_vec = {csr_vec_h_r, csr_vec_l};
assign ds_to_es_bus = {csr_op ,//236:230
assign ds_to_es_bus = {csr_vec ,//300:237
csr_op ,//236:230
csr_wdata_sel ,//229:229
csr_addr ,//228:215
csr_we ,//214:214
@@ -175,7 +177,6 @@ module id_stage
inst_decoder u_inst_decoder(
.inst (inst ),
.src1_is_pc (src1_is_pc ),
.src2_is_imm (src2_is_imm ),
.src2_is_4 (src2_is_4 ),
@@ -191,10 +192,12 @@ module id_stage
.branch_op (branch_op ),
.load_op (load_op ),
.store_op (store_op ),
.csr_plv (csr_plv ),
.csr_we (csr_we ),
.csr_op (csr_op ),
.csr_addr (csr_addr ),
.csr_wdata_sel (csr_wdata_sel ),
.csr_vec_l (csr_vec_l ),
.reg_we (reg_we )
);

2
lacpu/rtl/cpu/if_stage.v
View File

@@ -55,7 +55,7 @@ module if_stage
assign seq_pc = fs_pc + 3'h4;
assign next_pc = br_taken ? br_target : seq_pc;
assign csr_vec_h = timer_int;
assign csr_vec_h = 0; // timer_int; TODO!
assign inst_sram_en = flush | (br_taken ? 1'b0 : pc_valid);
assign inst_sram_we = 4'h0;

102
lacpu/rtl/cpu/inst_decoder.v
View File

@@ -24,11 +24,13 @@ module inst_decoder(
output [ 2:0] store_op,
// csr
input [ 1:0] csr_plv,
output csr_we,
output [ 6:0] csr_op,
output [13:0] csr_addr,
output csr_wdata_sel,
//output [31:0] csr_vec_l,
output [31:0] csr_vec_l,
//output [ 3:0] sel_rf_res,
@@ -142,6 +144,12 @@ module inst_decoder(
wire need_si20_pc;
wire need_si26_pc;
wire inst_valid;
wire excp_ine;
wire kernel_inst;
wire excp_ipe;
assign op_31_26 = inst[31:26];
assign op_25_22 = inst[25:22];
@@ -434,8 +442,98 @@ module inst_decoder(
};
assign csr_addr = inst[23:10];
assign csr_wdata_sel = inst_csrxchg;
//assign csr_vec_l = ?;
assign csr_vec_l = {28'b0 ,excp_ipe, excp_ine, inst_break, inst_syscall, inst_ertn};
assign inst_valid = inst_add_w |
inst_sub_w |
inst_slt |
inst_sltu |
inst_nor |
inst_and |
inst_or |
inst_xor |
inst_sll_w |
inst_srl_w |
inst_sra_w |
inst_mul_w |
inst_mulh_w |
inst_mulh_wu |
inst_div_w |
inst_mod_w |
inst_div_wu |
inst_mod_wu |
inst_break |
inst_syscall |
inst_slli_w |
inst_srli_w |
inst_srai_w |
//inst_idle |
inst_slti |
inst_sltui |
inst_addi_w |
inst_andi |
inst_ori |
inst_xori |
inst_ld_b |
inst_ld_h |
inst_ld_w |
inst_st_b |
inst_st_h |
inst_st_w |
inst_ld_bu |
inst_ld_hu |
inst_ll_w |
inst_sc_w |
inst_jirl |
inst_b |
inst_bl |
inst_beq |
inst_bne |
inst_blt |
inst_bge |
inst_bltu |
inst_bgeu |
inst_lu12i_w |
inst_pcaddu12i |
inst_csrrd |
inst_csrwr |
inst_csrxchg |
inst_rdcntid_w |
inst_rdcntvh_w |
inst_rdcntvl_w |
inst_ertn |
//inst_cacop |
//inst_preld |
inst_dbar |
inst_ibar ;
//inst_tlbsrch |
//inst_tlbrd |
//inst_tlbwr |
//inst_tlbfill |
//(inst_invtlb && (rd == 5'd0 ||
// rd == 5'd1 ||
// rd == 5'd2 ||
// rd == 5'd3 ||
// rd == 5'd4 ||
// rd == 5'd5 ||
// rd == 5'd6 )); //invtlb valid op
assign excp_ine = 1'b0;//~inst_valid; // TODO!
assign kernel_inst = inst_csrrd |
inst_csrwr |
inst_csrxchg |
//inst_cacop |
//inst_tlbsrch |
//inst_tlbrd |
//inst_tlbwr |
//inst_tlbfill |
//inst_invtlb |
inst_ertn ;
//inst_idle ;
assign excp_ipe = kernel_inst && (csr_plv == 2'b11); // TODO!
// rf_res from
// assign sel_rf_res[0] = inst_jirl | inst_bl;

26
lacpu/rtl/cpu/mem_stage.v
View File

@@ -1,6 +1,6 @@
module mem_stage
#(
parameter ES_TO_MS_BUS_WD = 175,
parameter ES_TO_MS_BUS_WD = 271,
parameter MS_TO_ES_BUS_WD = 38,
parameter MS_TO_WS_BUS_WD = 102
)
@@ -13,6 +13,8 @@ module mem_stage
output except_en,
output [31:0] new_pc,
output [ 1:0] csr_plv,
input [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus,
output [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
output [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus,
@@ -25,6 +27,7 @@ module mem_stage
reg [31:0] csr_rdata_r;
reg stall_flag;
wire [63:0] csr_vec;
wire [63:0] csr_bus;
wire [ 5:0] load_op;
wire [ 2:0] store_op;
@@ -54,21 +57,25 @@ module mem_stage
wire [13:0] csr_addr;
wire [31:0] csr_wdata;
wire [31:0] src1;
wire [31:0] ms_final_result;
assign {csr_bus ,//174:111
load_op ,//110:105
store_op ,//102:102
reg_we ,//101:101
dest ,//100:96
es_result,//95 :64
assign {csr_vec ,//270:207
csr_bus ,//206:143
load_op ,//142:137
store_op ,//136:134
reg_we ,//133:133
dest ,//132:128
es_result,//127:96
src1 ,//95 :64
ms_pc ,//63 :32
inst //31 :0
} = es_to_ms_bus_r;
assign ms_to_es_bus = {reg_we,
dest,
(|load_op) ? ms_result : es_result
ms_final_result
};
assign ms_to_ws_bus = {reg_we ,//101:101
@@ -162,7 +169,10 @@ module mem_stage
.reset (reset ),
.stall (stall[3]&stall[4]),
.pc (ms_pc ),
.src1 (src1 ),
.plv (csr_plv ),
.csr_we (csr_we ),
.csr_vec (csr_vec ),
.csr_op (csr_op ),
.csr_addr (csr_addr ),
.csr_wdata_sel (csr_wdata_sel ),

8
lacpu/rtl/cpu/mycpu_top.v
View File

@@ -1,8 +1,8 @@
module mycpu_top
#(
parameter FS_TO_DS_BUS_WD = 32,
parameter DS_TO_ES_BUS_WD = 237,
parameter ES_TO_MS_BUS_WD = 175,
parameter DS_TO_ES_BUS_WD = 301,
parameter ES_TO_MS_BUS_WD = 271,
parameter MS_TO_WS_BUS_WD = 102,
parameter WS_TO_RF_BUS_WD = 38,
@@ -57,6 +57,8 @@ module mycpu_top
wire [31:0] new_pc;
wire [31:0] csr_vec_h;
wire [ 1:0] csr_plv;
if_stage if_stage(
.clk (clk ),
.reset (reset ),
@@ -84,6 +86,7 @@ module mycpu_top
.pc_valid (inst_sram_en ),
.inst_sram_rdata (inst_sram_rdata ),
.csr_vec_h (csr_vec_h ),
.csr_plv (csr_plv ),
.ws_to_rf_bus (ws_to_rf_bus ),
.ds_to_es_bus (ds_to_es_bus )
);
@@ -114,6 +117,7 @@ module mycpu_top
.stall (stall ),
.except_en (except_en ),
.new_pc (new_pc ),
.csr_plv (csr_plv ),
.es_to_ms_bus (es_to_ms_bus ),
.ms_to_es_bus (ms_to_es_bus ),