Commit Graph

17 Commits

Author SHA1 Message Date
f17a44883f [Tag] pack submit 2023-08-04 16:20:04 +08:00
f87199d467 [Modified] pre submit file organization 2023-08-04 16:10:30 +08:00
df11c3a4ab [Modified] fix axi, pass func & pref test, but down to 85MHz 2023-08-01 14:30:11 +08:00
9f40b5f1bb [Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test 2023-07-31 16:05:29 +08:00
b38d04cc35 [Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test) 2023-07-29 21:16:28 +08:00
3a070d35fc [Add] switch to 7-stage and pass func test 2023-07-28 15:29:06 +08:00
bf2dd4655b [Backup] ready for switching to 7-stage pipline 2023-07-25 21:06:44 +08:00
d3af55af89 [Modified] Fix (铸币←me) bug & up to 60MHz 2023-07-23 01:10:46 +08:00
4c9c2ddd78 [Modified] Debug & board test with cache & pass n58 with 40 MHz 2023-07-22 14:56:53 +08:00
a755aae99e [Modified] Switch soc_top&board to axi&xc7a200t 2023-07-20 21:40:21 +08:00
1b4c6eee10 [Add] add icache dcache axi & pass test n46(before syscall) 2023-07-20 17:19:04 +08:00
38f1ea7eda [Modified] Fix bugs & 36 Functional Test Point PASS 2023-06-26 17:14:26 +08:00
8d1aa17074 [Modified] Change branch site, without stall (need 1 stall) 2023-06-12 15:36:00 +08:00
f592606196 [Modified] Fix louduse 2023-06-08 16:27:48 +08:00
d3df7c858f [Modified] remove div diu ip use div.v instead 2023-06-06 15:18:34 +08:00
9a72e27ca4 [Add] add div ip only (not use) 2023-05-23 12:59:04 +08:00
d4366a9c7b [Add] la32r cpu framework add 2023-05-12 21:00:39 +08:00