UnbalancedCat 9f40b5f1bb [Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

2023-07-31 16:05:29 +08:00

..

axi_crossbar_1x2

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

axi_ram

[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

2023-07-31 16:05:29 +08:00

clk_pll

[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

2023-07-31 16:05:29 +08:00

data_sram_bank

[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

2023-07-31 16:05:29 +08:00