UnbalancedCat 9f40b5f1bb [Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

2023-07-31 16:05:29 +08:00

..

axi_wrap

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

CONFREG

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

mycpu

[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

2023-07-31 16:05:29 +08:00

ram_wrap

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

xilinx_ip

[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

2023-07-31 16:05:29 +08:00

soc_lite_top.v

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00

soc_lite_top.v.axi_bak

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00

soc_lite_top.v.bram_bak

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00