UnbalancedCat bf2dd4655b [Backup] ready for switching to 7-stage pipline

2023-07-25 21:06:44 +08:00

..

axi_crossbar_1x2

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

axi_ram

[Modified] Debug & board test with cache & pass n58 with 40 MHz

2023-07-22 14:56:53 +08:00

clk_pll

[Backup] ready for switching to 7-stage pipline

2023-07-25 21:06:44 +08:00

data_sram_bank

[Modified] Debug & board test with cache & pass n58 with 40 MHz

2023-07-22 14:56:53 +08:00