93 lines
3.1 KiB
Verilog
93 lines
3.1 KiB
Verilog
module mul_div_top(
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input clk,
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input reset,
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input [ 5:0] stall,
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output stallreq,
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input [ 3:0] mul_div_op,
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input mul_div_sign,
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input [31:0] a,
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input [31:0] b,
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output [31:0] mul_div_result
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);
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wire stallreq_for_mul;
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wire stallreq_for_div;
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wire sign_flag;
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wire [31:0] src_a;
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wire [31:0] src_b;
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wire [31:0] result_h;
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wire [31:0] result_l;
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wire [31:0] quotient;
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wire [31:0] remainder;
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wire mul_en;
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wire div_en;
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wire [31:0] a_locked;
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wire [31:0] b_locked;
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wire mul_en_locked;
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wire div_en_locked;
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wire sign_flag_locked;
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wire rem_flag_locked;
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assign mul_en = mul_div_op[0] | mul_div_op[1];
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assign div_en = mul_div_op[2] | mul_div_op[3];
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assign sign_flag = a[31] ^ b[31];
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assign src_a = (mul_div_sign & a[31]) ? (~a[31:0] + 1'b1) : a;
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assign src_b = (mul_div_sign & b[31]) ? (~b[31:0] + 1'b1) : b;
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mul_div_lock u_mul_div_lock(
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.clk (clk ),
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.reset (reset ),
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.stall (stall ),
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.a (src_a ),
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.b (src_b ),
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.sign_flag (sign_flag ),
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.rem_flag (a[31] ),
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.mul_en (mul_en ),
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.div_en (div_en ),
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.stallreq_for_mul (stallreq_for_mul ),
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.stallreq_for_div (stallreq_for_div ),
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.a_locked (a_locked ),
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.b_locked (b_locked ),
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.sign_flag_locked (sign_flag_locked ),
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.rem_flag_locked (rem_flag_locked ),
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.mul_en_locked (mul_en_locked ),
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.div_en_locked (div_en_locked )
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);
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mul u_mul(
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.clk (clk ),
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.reset (reset ),
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.stallreq (stallreq_for_mul),
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.in_valid (mul_en_locked ),
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.out_valid (),
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.a (a_locked ),
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.b (b_locked ),
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.result_h (result_h ),
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.result_l (result_l )
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);
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div u_div(
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.clk (clk ),
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.reset (reset ),
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.stallreq (stallreq_for_div),
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.in_valid (div_en_locked ),
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.out_valid (),
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.a (a_locked ),
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.b (b_locked ),
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.quotient (quotient ),
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.remainder (remainder )
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);
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assign stallreq = stallreq_for_mul | stallreq_for_div;
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assign mul_div_result = mul_div_op[0] ? (mul_div_sign & sign_flag_locked & |result_l ) ? { ~result_l[31:0] + 1'b1} : result_l :
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mul_div_op[1] ? (mul_div_sign & sign_flag_locked & |result_h ) ? {sign_flag_locked, ~result_h[30:0] } : result_h :
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mul_div_op[2] ? (mul_div_sign & sign_flag_locked & |quotient ) ? {sign_flag_locked, ~quotient[30:0] + 1'b1} : quotient :
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mul_div_op[3] ? (mul_div_sign & rem_flag_locked & |remainder) ? {rem_flag_locked , ~remainder[30:0] + 1'b1} : remainder :
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32'b0;
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endmodule |