UnbalancedCat/neulacpu
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b38d04cc35438ba7a247f749f2ae960f3f9f325f
neulacpu/lacpu/rtl/mycpu
History
UnbalancedCat b38d04cc35 [Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00
..
alu.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
axi_ctrl.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
bru.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
cache_data.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
cache_tag.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
csr.hv
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
csr.v
[Add] add ext_int
2023-07-23 01:59:53 +08:00
dcache.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
div.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
dt.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00
exe_stage.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00
forward.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00
icache.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
id_stage.v
[Add] switch to 7-stage and pass func test
2023-07-28 15:29:06 +08:00
if_stage.v
[Add] switch to 7-stage and pass func test
2023-07-28 15:29:06 +08:00
inst_decoder.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
lsu.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mem_stage.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00
mmu.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mul_div_lock.v
[Add] switch to 7-stage and pass func test
2023-07-28 15:29:06 +08:00
mul_div_top.v
[Add] switch to 7-stage and pass func test
2023-07-28 15:29:06 +08:00
mul.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mycpu_core.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00
mycpu_top.v
[Add] switch to 7-stage and pass func test
2023-07-28 15:29:06 +08:00
pip_ctrl.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00
regfile.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
tlb.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
tools.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
uncache.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
wb_stage.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00