UnbalancedCat b38d04cc35 [Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)

2023-07-29 21:16:28 +08:00

..

axi_wrap

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

CONFREG

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

mycpu

[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)

2023-07-29 21:16:28 +08:00

ram_wrap

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

xilinx_ip

[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)

2023-07-29 21:16:28 +08:00

soc_lite_top.v

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00

soc_lite_top.v.axi_bak

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00

soc_lite_top.v.bram_bak

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00