82 lines
2.4 KiB
Verilog
82 lines
2.4 KiB
Verilog
module mul_div_lock (
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input clk,
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input reset,
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input [ 5:0] stall,
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input [31:0] a,
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input [31:0] b,
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input mul_en,
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input div_en,
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input stallreq_for_mul,
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input stallreq_for_div,
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input sign_flag,
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input rem_flag,
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output [31:0] a_locked,
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output [31:0] b_locked,
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output mul_en_locked,
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output div_en_locked,
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output sign_flag_locked,
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output rem_flag_locked
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);
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reg first_enable;
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reg mul_en_musk;
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reg div_en_musk;
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reg [31:0] a_buffer;
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reg [31:0] b_buffer;
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reg sign_flag_buffer;
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reg rem_flag_buffer;
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wire stallreq = stallreq_for_mul | stallreq_for_div;
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assign mul_en_locked = mul_en & mul_en_musk;
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assign div_en_locked = div_en & div_en_musk;
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assign a_locked = first_enable ? a : a_buffer;
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assign b_locked = first_enable ? b : b_buffer;
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assign sign_flag_locked = first_enable ? sign_flag : sign_flag_buffer;
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assign rem_flag_locked = first_enable ? rem_flag : rem_flag_buffer;
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always @ (posedge clk) begin
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if (reset) begin
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a_buffer <= 0;
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b_buffer <= 0;
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sign_flag_buffer <= 0;
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rem_flag_buffer <= 0;
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mul_en_musk <= 1;
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div_en_musk <= 1;
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first_enable <= 1;
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end
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else if (mul_en & first_enable) begin
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a_buffer <= a;
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b_buffer <= b;
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sign_flag_buffer <= sign_flag;
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rem_flag_buffer <= rem_flag;
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mul_en_musk <= 0;
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div_en_musk <= 1;
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first_enable <= 0;
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end
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else if (div_en & first_enable) begin
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a_buffer <= a;
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b_buffer <= b;
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sign_flag_buffer <= sign_flag;
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rem_flag_buffer <= rem_flag;
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mul_en_musk <= 1;
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div_en_musk <= 0;
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first_enable <= 0;
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end
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else if (!stallreq & (mul_en|div_en) & !first_enable & !stall[2]) begin
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a_buffer <= 0;
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b_buffer <= 0;
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sign_flag_buffer <= 0;
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rem_flag_buffer <= 0;
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mul_en_musk <= 1;
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div_en_musk <= 1;
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first_enable <= 1;
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end
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end
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endmodule |