[Modified] Fix louduse

.gitignore

@@ -11,4 +11,7 @@ vivado.jou
 vivado.log
 !/lacpu/run_vivado/la32r/la32r.xpr
 !/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci
+!/lacpu/run_vivado/la32r/sim
+!/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe
 !/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci
+!/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe

lacpu/rtl/cpu/exe_stage.v

@@ -24,9 +24,6 @@ module exe_stage(
     input  [`MS_TO_ES_BUS_WD -1:0] ms_to_ds_bus  ,
     //from ws
     input  [`WS_TO_ES_BUS_WD -1:0] ws_to_ds_bus  ,
-    //lu
-    output [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus  ,
-    input                          lu_to_es_bus  ,
     //div_mul
     output        es_div_enable   ,
     output        es_div_sign     ,
@@ -62,8 +59,6 @@ module exe_stage(
     wire        es_src2_is_ms_dest;
     wire        es_data_is_rf_wdata;
 
-    reg         loaduse_r;
-
     assign {es_alu_op       ,   //173:155
             es_src1_is_pc   ,   //154:154
             es_src2_is_imm  ,   //153:153
@@ -129,9 +124,7 @@ module exe_stage(
                            es_mem_we     
                            };
 
-    assign es_to_lu_bus  = {es_dest, es_load_op};
+    assign es_ready_go    = !(div_stall);
-
-    assign es_ready_go    = !(div_stall || loaduse_r);
     assign es_allowin     = !es_valid || es_ready_go && ms_allowin;
     assign es_to_ms_valid =  es_valid && es_ready_go;
     always @(posedge clk) begin
@@ -150,18 +143,6 @@ module exe_stage(
         end
     end
 
-    always @(posedge clk) begin
-        if(reset) begin
-            loaduse_r <= 1'b0;
-        end
-        else if(loaduse_r == 1'b1) begin
-            loaduse_r <= 1'b0;
-        end
-        else begin
-            loaduse_r <= lu_to_es_bus;
-        end
-    end
-
     assign es_alu_src1 = es_src1_is_pc      ? es_pc         :
                          es_src1_is_es_dest ? ms_alu_result :
                          es_src1_is_ms_dest ? ws_rf_wdata   :

lacpu/rtl/cpu/id_stage.v

@@ -16,10 +16,7 @@ module id_stage(
     //to fs
     input  [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus  ,
     //to fw
-    output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus  ,
+    output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus  
-    //to lu
-    output [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus
-
 );
 
     reg         ds_valid   ;
@@ -140,8 +137,6 @@ module id_stage(
 
     assign ds_to_fw_bus = {rf_raddr1 , rf_raddr2};
 
-    assign ds_to_lu_bus = {rf_raddr1 , rf_raddr2};
-
     assign ds_ready_go    = 1'b1;
     assign ds_allowin     = !ds_valid || ds_ready_go && es_allowin;
     assign ds_to_es_valid = ds_valid && ds_ready_go;

lacpu/rtl/cpu/loaduse.v

@@ -1,19 +0,0 @@
-`include "mycpu.vh"
-
-module loaduse(  
-    input  [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
-    input  [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus,
-
-    output                         lu_to_es_bus
-);
-    wire [4:0] ds_rf_raddr1;
-    wire [4:0] ds_rf_raddr2;
-    wire [4:0] es_load_op;
-    wire [4:0] es_dest;
-
-    assign {ds_rf_raddr1, ds_rf_raddr2} = ds_to_lu_bus;
-    assign {es_dest     , es_load_op  } = es_to_lu_bus;
-    
-    assign lu_to_es_bus = ^es_load_op && 
-                        (((ds_rf_raddr1 == es_dest) && (ds_rf_raddr1 != 5'b0)) || ((ds_rf_raddr2 == es_dest) && (ds_rf_raddr2 != 5'b0)));
-endmodule

lacpu/rtl/cpu/mycpu_top.v

@@ -44,9 +44,6 @@ module mycpu_top(
     wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus;
     wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
     wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
-    wire [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus;
-    wire [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus;
-    wire                         lu_to_es_bus;
 
     wire        es_div_enable;
     wire        es_div_sign;
@@ -91,9 +88,7 @@ module mycpu_top(
         //to rf: for write back
         .ws_to_rf_bus   (ws_to_rf_bus   ),
         //to fw
-        .ds_to_fw_bus   (ds_to_fw_bus   ),
+        .ds_to_fw_bus   (ds_to_fw_bus   )
-        //to lu
-        .ds_to_lu_bus   (ds_to_lu_bus   )
     );
     // EXE stage
     exe_stage exe_stage(
@@ -116,10 +111,6 @@ module mycpu_top(
         .ms_to_ds_bus   (ms_to_es_bus   ),
         //from ws
         .ws_to_ds_bus   (ws_to_es_bus   ),
-        //to lu
-        .es_to_lu_bus   (es_to_lu_bus   ),
-        //from lu
-        .lu_to_es_bus   (lu_to_es_bus   ),
         // data sram interface
         .data_sram_en   (data_sram_en   ),
         .data_sram_wen  (data_sram_we   ),
@@ -201,11 +192,5 @@ module mycpu_top(
         .ms_to_fw_bus   (ms_to_fw_bus),
         .fw_to_es_bus   (fw_to_es_bus)
     );
-    //Loaduse
-    loaduse loaduse(
-        .ds_to_lu_bus   (ds_to_lu_bus),
-        .es_to_lu_bus   (es_to_lu_bus),
-        .lu_to_es_bus   (lu_to_es_bus)
-    );
 
 endmodule

lacpu/rtl/xilinx_ip/data_ram/data_ram.coe

@@ -0,0 +1,3 @@
+memory_initialization_radix = 16;
+memory_initialization_vector =
+00000001

lacpu/rtl/xilinx_ip/data_ram/data_ram.xci

@@ -131,9 +131,9 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">data_ram.mem</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">data_ram.mif</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
@@ -172,7 +172,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">./data_ram.coe</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">data_ram</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
@@ -189,7 +189,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
@@ -296,6 +296,8 @@
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>

lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe

@@ -0,0 +1,2 @@
+memory_initialization_radix=16;
+memory_initialization_vector=28800401 02800822;

lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci

@@ -131,9 +131,9 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">inst_ram.mem</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">inst_ram.mif</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
@@ -172,7 +172,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">inst_ram.coe</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">inst_ram</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
@@ -189,7 +189,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
@@ -296,6 +296,8 @@
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>

lacpu/run_vivado/la32r/la32r.xpr

@@ -29,20 +29,20 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="WTXSimLaunchSim" Val="1"/>
+    <Option Name="WTXSimLaunchSim" Val="22"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="8"/>
+    <Option Name="WTXSimExportSim" Val="12"/>
-    <Option Name="WTModelSimExportSim" Val="8"/>
+    <Option Name="WTModelSimExportSim" Val="12"/>
-    <Option Name="WTQuestaExportSim" Val="8"/>
+    <Option Name="WTQuestaExportSim" Val="12"/>
-    <Option Name="WTIesExportSim" Val="8"/>
+    <Option Name="WTIesExportSim" Val="12"/>
-    <Option Name="WTVcsExportSim" Val="8"/>
+    <Option Name="WTVcsExportSim" Val="12"/>
-    <Option Name="WTRivieraExportSim" Val="8"/>
+    <Option Name="WTRivieraExportSim" Val="12"/>
-    <Option Name="WTActivehdlExportSim" Val="8"/>
+    <Option Name="WTActivehdlExportSim" Val="12"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -96,13 +96,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../../rtl/cpu/loaduse.v">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PPRDIR/../../rtl/cpu/mem_stage.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -145,6 +138,26 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../../rtl/cpu/loaduse.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../rtl/xilinx_ip/inst_ram/inst_ram.coe">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../rtl/xilinx_ip/data_ram/data_ram.coe">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="soc_lite_top"/>
@@ -165,15 +178,30 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/sim/soc_tb.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sim/cpu_tb_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="soc_lite_top"/>
+        <Option Name="TopModule" Val="cpu_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/sim/cpu_tb_behav.wcfg"/>
+        <Option Name="xsim.simulate.log_all_signals" Val="true"/>
+        <Option Name="xsim.simulate.saif_all_signals" Val="true"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
@@ -230,7 +258,9 @@
   <Runs Version="1" Minor="11">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -260,7 +290,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

lacpu/run_vivado/la32r/sim/soc_tb.v

@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps
+
+module cpu_tb(
+
+    );
+    reg         resetn;
+    reg         clk;
+    wire [31:0] debug_wb_pc;
+    wire [ 3:0] debug_wb_rf_wen;
+    wire [ 4:0] debug_wb_rf_wnum;
+    wire [31:0] debug_wb_rf_wdata;
+    
+    initial
+    begin
+        clk = 1'b0;
+        resetn = 1'b0;
+        #20;
+        resetn = 1'b1;
+        #2000;
+        $finish;
+    end
+    always #5 clk=~clk;
+    
+    soc_lite_top u_soc_top(
+        .resetn             (resetn           ),
+        .clk                (clk              ),
+        
+        .pc                 ()
+    );
+    
+     //debug signals
+    assign debug_wb_pc = u_soc_top.debug_wb_pc;
+    assign debug_wb_rf_wen = u_soc_top.debug_wb_rf_wen;
+    assign debug_wb_rf_wnum = u_soc_top.debug_wb_rf_wnum;
+    assign debug_wb_rf_wdata = u_soc_top.debug_wb_rf_wdata;
+    
+    always @(posedge clk) begin
+        $display("PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
+                      debug_wb_pc, debug_wb_rf_wnum, debug_wb_rf_wdata);
+    end
+    
+    
+endmodule