diff --git a/.gitignore b/.gitignore
index 44e1c46..f05f7eb 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,4 +11,7 @@ vivado.jou
vivado.log
!/lacpu/run_vivado/la32r/la32r.xpr
!/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci
+!/lacpu/run_vivado/la32r/sim
+!/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe
!/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci
+!/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe
diff --git a/lacpu/rtl/cpu/exe_stage.v b/lacpu/rtl/cpu/exe_stage.v
index 22b37ba..cb18874 100755
--- a/lacpu/rtl/cpu/exe_stage.v
+++ b/lacpu/rtl/cpu/exe_stage.v
@@ -24,9 +24,6 @@ module exe_stage(
input [`MS_TO_ES_BUS_WD -1:0] ms_to_ds_bus ,
//from ws
input [`WS_TO_ES_BUS_WD -1:0] ws_to_ds_bus ,
- //lu
- output [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus ,
- input lu_to_es_bus ,
//div_mul
output es_div_enable ,
output es_div_sign ,
@@ -62,8 +59,6 @@ module exe_stage(
wire es_src2_is_ms_dest;
wire es_data_is_rf_wdata;
- reg loaduse_r;
-
assign {es_alu_op , //173:155
es_src1_is_pc , //154:154
es_src2_is_imm , //153:153
@@ -129,9 +124,7 @@ module exe_stage(
es_mem_we
};
- assign es_to_lu_bus = {es_dest, es_load_op};
-
- assign es_ready_go = !(div_stall || loaduse_r);
+ assign es_ready_go = !(div_stall);
assign es_allowin = !es_valid || es_ready_go && ms_allowin;
assign es_to_ms_valid = es_valid && es_ready_go;
always @(posedge clk) begin
@@ -150,18 +143,6 @@ module exe_stage(
end
end
- always @(posedge clk) begin
- if(reset) begin
- loaduse_r <= 1'b0;
- end
- else if(loaduse_r == 1'b1) begin
- loaduse_r <= 1'b0;
- end
- else begin
- loaduse_r <= lu_to_es_bus;
- end
- end
-
assign es_alu_src1 = es_src1_is_pc ? es_pc :
es_src1_is_es_dest ? ms_alu_result :
es_src1_is_ms_dest ? ws_rf_wdata :
diff --git a/lacpu/rtl/cpu/id_stage.v b/lacpu/rtl/cpu/id_stage.v
index 87335e2..cbeed89 100755
--- a/lacpu/rtl/cpu/id_stage.v
+++ b/lacpu/rtl/cpu/id_stage.v
@@ -16,10 +16,7 @@ module id_stage(
//to fs
input [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus ,
//to fw
- output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus ,
- //to lu
- output [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus
-
+ output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus
);
reg ds_valid ;
@@ -140,8 +137,6 @@ module id_stage(
assign ds_to_fw_bus = {rf_raddr1 , rf_raddr2};
- assign ds_to_lu_bus = {rf_raddr1 , rf_raddr2};
-
assign ds_ready_go = 1'b1;
assign ds_allowin = !ds_valid || ds_ready_go && es_allowin;
assign ds_to_es_valid = ds_valid && ds_ready_go;
diff --git a/lacpu/rtl/cpu/loaduse.v b/lacpu/rtl/cpu/loaduse.v
deleted file mode 100644
index 197da7f..0000000
--- a/lacpu/rtl/cpu/loaduse.v
+++ /dev/null
@@ -1,19 +0,0 @@
-`include "mycpu.vh"
-
-module loaduse(
- input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
- input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus,
-
- output lu_to_es_bus
-);
- wire [4:0] ds_rf_raddr1;
- wire [4:0] ds_rf_raddr2;
- wire [4:0] es_load_op;
- wire [4:0] es_dest;
-
- assign {ds_rf_raddr1, ds_rf_raddr2} = ds_to_lu_bus;
- assign {es_dest , es_load_op } = es_to_lu_bus;
-
- assign lu_to_es_bus = ^es_load_op &&
- (((ds_rf_raddr1 == es_dest) && (ds_rf_raddr1 != 5'b0)) || ((ds_rf_raddr2 == es_dest) && (ds_rf_raddr2 != 5'b0)));
-endmodule
\ No newline at end of file
diff --git a/lacpu/rtl/cpu/mycpu_top.v b/lacpu/rtl/cpu/mycpu_top.v
index a78c66e..ea4e5af 100644
--- a/lacpu/rtl/cpu/mycpu_top.v
+++ b/lacpu/rtl/cpu/mycpu_top.v
@@ -44,9 +44,6 @@ module mycpu_top(
wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus;
wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
- wire [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus;
- wire [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus;
- wire lu_to_es_bus;
wire es_div_enable;
wire es_div_sign;
@@ -91,9 +88,7 @@ module mycpu_top(
//to rf: for write back
.ws_to_rf_bus (ws_to_rf_bus ),
//to fw
- .ds_to_fw_bus (ds_to_fw_bus ),
- //to lu
- .ds_to_lu_bus (ds_to_lu_bus )
+ .ds_to_fw_bus (ds_to_fw_bus )
);
// EXE stage
exe_stage exe_stage(
@@ -116,10 +111,6 @@ module mycpu_top(
.ms_to_ds_bus (ms_to_es_bus ),
//from ws
.ws_to_ds_bus (ws_to_es_bus ),
- //to lu
- .es_to_lu_bus (es_to_lu_bus ),
- //from lu
- .lu_to_es_bus (lu_to_es_bus ),
// data sram interface
.data_sram_en (data_sram_en ),
.data_sram_wen (data_sram_we ),
@@ -201,11 +192,5 @@ module mycpu_top(
.ms_to_fw_bus (ms_to_fw_bus),
.fw_to_es_bus (fw_to_es_bus)
);
- //Loaduse
- loaduse loaduse(
- .ds_to_lu_bus (ds_to_lu_bus),
- .es_to_lu_bus (es_to_lu_bus),
- .lu_to_es_bus (lu_to_es_bus)
- );
endmodule
diff --git a/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe b/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe
new file mode 100644
index 0000000..9ef4a6f
--- /dev/null
+++ b/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe
@@ -0,0 +1,3 @@
+memory_initialization_radix = 16;
+memory_initialization_vector =
+00000001
diff --git a/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci b/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci
index 4c94830..92255e0 100644
--- a/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci
+++ b/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci
@@ -131,9 +131,9 @@
0
0
data_ram.mem
- no_coe_file_loaded
+ data_ram.mif
0
- 0
+ 1
0
0
1
@@ -172,7 +172,7 @@
false
8
NONE
- no_coe_file_loaded
+ ./data_ram.coe
ALL
data_ram
false
@@ -189,7 +189,7 @@
Single_Bit_Error_Injection
false
Native
- false
+ true
no_mem_loaded
Single_Port_RAM
WRITE_FIRST
@@ -296,6 +296,8 @@
+
+
diff --git a/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe b/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe
new file mode 100644
index 0000000..14985ca
--- /dev/null
+++ b/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe
@@ -0,0 +1,2 @@
+memory_initialization_radix=16;
+memory_initialization_vector=28800401 02800822;
diff --git a/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci b/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci
index a439f35..b51d51b 100644
--- a/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci
+++ b/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci
@@ -131,9 +131,9 @@
0
0
inst_ram.mem
- no_coe_file_loaded
+ inst_ram.mif
0
- 0
+ 1
0
0
1
@@ -172,7 +172,7 @@
false
8
NONE
- no_coe_file_loaded
+ inst_ram.coe
ALL
inst_ram
false
@@ -189,7 +189,7 @@
Single_Bit_Error_Injection
false
Native
- false
+ true
no_mem_loaded
Single_Port_RAM
WRITE_FIRST
@@ -296,6 +296,8 @@
+
+
diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr
index 5253f87..94f69c1 100644
--- a/lacpu/run_vivado/la32r/la32r.xpr
+++ b/lacpu/run_vivado/la32r/la32r.xpr
@@ -29,20 +29,20 @@
-
+
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -96,13 +96,6 @@
-
-
-
-
-
-
-
@@ -145,6 +138,26 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -165,15 +178,30 @@
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
@@ -230,7 +258,9 @@
-
+
+ Vivado Synthesis Defaults
+
@@ -260,7 +290,9 @@
-
+
+ Default settings for Implementation.
+
diff --git a/lacpu/run_vivado/la32r/sim/cpu_tb_behav.wcfg b/lacpu/run_vivado/la32r/sim/cpu_tb_behav.wcfg
new file mode 100644
index 0000000..12f2fe6
--- /dev/null
+++ b/lacpu/run_vivado/la32r/sim/cpu_tb_behav.wcfg
@@ -0,0 +1,1236 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ debug
+ label
+
+ resetn
+ resetn
+
+
+ clk
+ clk
+
+
+ debug_wb_pc[31:0]
+ debug_wb_pc[31:0]
+
+
+ debug_wb_rf_wen[3:0]
+ debug_wb_rf_wen[3:0]
+
+
+ debug_wb_rf_wnum[4:0]
+ debug_wb_rf_wnum[4:0]
+
+
+ debug_wb_rf_wdata[31:0]
+ debug_wb_rf_wdata[31:0]
+
+
+
+ cpu
+ label
+
+
+ if_stage
+ label
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ ds_allowin
+ ds_allowin
+
+
+ br_bus[32:0]
+ br_bus[32:0]
+
+
+ fs_to_ds_valid
+ fs_to_ds_valid
+
+
+ fs_to_ds_bus[63:0]
+ fs_to_ds_bus[63:0]
+
+
+ inst_sram_en
+ inst_sram_en
+
+
+ inst_sram_wen[3:0]
+ inst_sram_wen[3:0]
+
+
+ inst_sram_addr[31:0]
+ inst_sram_addr[31:0]
+
+
+ inst_sram_wdata[31:0]
+ inst_sram_wdata[31:0]
+
+
+ inst_sram_rdata[31:0]
+ inst_sram_rdata[31:0]
+
+
+ fs_valid
+ fs_valid
+
+
+ fs_ready_go
+ fs_ready_go
+
+
+ fs_allowin
+ fs_allowin
+
+
+ to_fs_valid
+ to_fs_valid
+
+
+ seq_pc[31:0]
+ seq_pc[31:0]
+
+
+ nextpc[31:0]
+ nextpc[31:0]
+
+
+ br_taken
+ br_taken
+
+
+ br_target[31:0]
+ br_target[31:0]
+
+
+ fs_inst[31:0]
+ fs_inst[31:0]
+
+
+ fs_pc[31:0]
+ fs_pc[31:0]
+
+
+
+ id_stage
+ label
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ es_allowin
+ es_allowin
+
+
+ ds_allowin
+ ds_allowin
+
+
+ fs_to_ds_valid
+ fs_to_ds_valid
+
+
+ fs_to_ds_bus[63:0]
+ fs_to_ds_bus[63:0]
+
+
+ ds_to_es_valid
+ ds_to_es_valid
+
+
+ ds_to_es_bus[173:0]
+ ds_to_es_bus[173:0]
+
+
+ ws_to_rf_bus[37:0]
+ ws_to_rf_bus[37:0]
+
+
+ ds_to_fw_bus[9:0]
+ ds_to_fw_bus[9:0]
+
+
+ ds_valid
+ ds_valid
+
+
+ ds_ready_go
+ ds_ready_go
+
+
+ fs_pc[31:0]
+ fs_pc[31:0]
+
+
+ fs_to_ds_bus_r[63:0]
+ fs_to_ds_bus_r[63:0]
+
+
+ ds_inst[31:0]
+ ds_inst[31:0]
+ BINARYRADIX
+ #FFA500
+ true
+
+
+ ds_pc[31:0]
+ ds_pc[31:0]
+ #FFA500
+ true
+
+
+ rf_we
+ rf_we
+
+
+ rf_waddr[4:0]
+ rf_waddr[4:0]
+
+
+ rf_wdata[31:0]
+ rf_wdata[31:0]
+
+
+ alu_op[18:0]
+ alu_op[18:0]
+
+
+ src1_is_pc
+ src1_is_pc
+
+
+ src2_is_imm
+ src2_is_imm
+
+
+ src2_is_4
+ src2_is_4
+
+
+ mem_to_reg
+ mem_to_reg
+
+
+ reg_we
+ reg_we
+
+
+ mem_we
+ mem_we
+
+
+ load_op[4:0]
+ load_op[4:0]
+
+
+ store_op[2:0]
+ store_op[2:0]
+
+
+ branch_op[8:0]
+ branch_op[8:0]
+
+
+ dest[4:0]
+ dest[4:0]
+
+
+ imm[31:0]
+ imm[31:0]
+
+
+ op[21:0]
+ op[21:0]
+
+
+ ra[4:0]
+ ra[4:0]
+
+
+ rk[4:0]
+ rk[4:0]
+
+
+ rj[4:0]
+ rj[4:0]
+
+
+ rd[4:0]
+ rd[4:0]
+
+
+ op6_d[7:0]
+ op6_d[7:0]
+
+
+ op7_d[7:0]
+ op7_d[7:0]
+
+
+ op10_d[7:0]
+ op10_d[7:0]
+ BINARYRADIX
+
+
+ op17_d[31:0]
+ op17_d[31:0]
+
+
+ inst_addw
+ inst_addw
+
+
+ inst_subw
+ inst_subw
+
+
+ inst_addiw
+ inst_addiw
+
+
+ inst_lu12iw
+ inst_lu12iw
+
+
+ inst_slt
+ inst_slt
+
+
+ inst_sltu
+ inst_sltu
+
+
+ inst_slti
+ inst_slti
+
+
+ inst_sltui
+ inst_sltui
+
+
+ inst_pcaddu12i
+ inst_pcaddu12i
+
+
+ inst_and
+ inst_and
+
+
+ inst_or
+ inst_or
+
+
+ inst_nor
+ inst_nor
+
+
+ inst_xor
+ inst_xor
+
+
+ inst_andi
+ inst_andi
+
+
+ inst_ori
+ inst_ori
+
+
+ inst_xori
+ inst_xori
+
+
+ inst_sllw
+ inst_sllw
+
+
+ inst_srlw
+ inst_srlw
+
+
+ inst_sraw
+ inst_sraw
+
+
+ inst_slliw
+ inst_slliw
+
+
+ inst_srliw
+ inst_srliw
+
+
+ inst_sraiw
+ inst_sraiw
+
+
+ inst_mulw
+ inst_mulw
+
+
+ inst_mulhw
+ inst_mulhw
+
+
+ inst_mulhwu
+ inst_mulhwu
+
+
+ inst_beq
+ inst_beq
+
+
+ inst_bne
+ inst_bne
+
+
+ inst_blt
+ inst_blt
+
+
+ inst_bge
+ inst_bge
+
+
+ inst_bltu
+ inst_bltu
+
+
+ inst_bgeu
+ inst_bgeu
+
+
+ inst_b
+ inst_b
+
+
+ inst_bl
+ inst_bl
+
+
+ inst_jirl
+ inst_jirl
+
+
+ inst_ldb
+ inst_ldb
+
+
+ inst_ldh
+ inst_ldh
+
+
+ inst_ldw
+ inst_ldw
+
+
+ inst_ldbu
+ inst_ldbu
+
+
+ inst_ldhu
+ inst_ldhu
+
+
+ inst_stb
+ inst_stb
+
+
+ inst_sth
+ inst_sth
+
+
+ inst_stw
+ inst_stw
+
+
+ inst_divw
+ inst_divw
+
+
+ inst_modw
+ inst_modw
+
+
+ inst_divwu
+ inst_divwu
+
+
+ inst_modwu
+ inst_modwu
+
+
+ dst_is_r1
+ dst_is_r1
+
+
+ rf_raddr1[4:0]
+ rf_raddr1[4:0]
+
+
+ rf_rdata1[31:0]
+ rf_rdata1[31:0]
+
+
+ rf_raddr2[4:0]
+ rf_raddr2[4:0]
+
+
+ rf_rdata2[31:0]
+ rf_rdata2[31:0]
+
+
+
+ exe_stage
+ label
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ ms_allowin
+ ms_allowin
+
+
+ es_allowin
+ es_allowin
+
+
+ ds_to_es_valid
+ ds_to_es_valid
+
+
+ ds_to_es_bus[173:0]
+ ds_to_es_bus[173:0]
+
+
+ es_to_ms_valid
+ es_to_ms_valid
+
+
+ es_to_ms_bus[122:0]
+ es_to_ms_bus[122:0]
+
+
+ data_sram_en
+ data_sram_en
+
+
+ data_sram_wen[3:0]
+ data_sram_wen[3:0]
+
+
+ data_sram_addr[31:0]
+ data_sram_addr[31:0]
+
+
+ data_sram_wdata[31:0]
+ data_sram_wdata[31:0]
+
+
+ es_to_fw_bus[11:0]
+ es_to_fw_bus[11:0]
+
+
+ fw_to_es_bus[4:0]
+ fw_to_es_bus[4:0]
+
+
+ ms_to_ds_bus[31:0]
+ ms_to_ds_bus[31:0]
+
+
+ ws_to_ds_bus[31:0]
+ ws_to_ds_bus[31:0]
+
+
+ es_div_enable
+ es_div_enable
+
+
+ es_div_sign
+ es_div_sign
+
+
+ es_rf_rdata1[31:0]
+ es_rf_rdata1[31:0]
+
+
+ es_rf_rdata2[31:0]
+ es_rf_rdata2[31:0]
+
+
+ div_complete
+ div_complete
+
+
+ es_valid
+ es_valid
+
+
+ es_ready_go
+ es_ready_go
+
+
+ ds_to_es_bus_r[173:0]
+ ds_to_es_bus_r[173:0]
+
+
+ es_alu_op[18:0]
+ es_alu_op[18:0]
+
+
+ es_src1_is_pc
+ es_src1_is_pc
+
+
+ es_src2_is_imm
+ es_src2_is_imm
+
+
+ es_src2_is_4
+ es_src2_is_4
+
+
+ es_mem_to_reg
+ es_mem_to_reg
+
+
+ es_reg_we
+ es_reg_we
+
+
+ es_mem_we
+ es_mem_we
+
+
+ es_load_op[4:0]
+ es_load_op[4:0]
+
+
+ es_store_op[2:0]
+ es_store_op[2:0]
+
+
+ es_branch_op[8:0]
+ es_branch_op[8:0]
+
+
+ es_dest[4:0]
+ es_dest[4:0]
+
+
+ es_imm[31:0]
+ es_imm[31:0]
+
+
+ es_pc[31:0]
+ es_pc[31:0]
+ #FFA500
+ true
+
+
+ ms_alu_result[31:0]
+ ms_alu_result[31:0]
+
+
+ ws_rf_wdata[31:0]
+ ws_rf_wdata[31:0]
+
+
+ es_src1_is_es_dest
+ es_src1_is_es_dest
+
+
+ es_src1_is_ms_dest
+ es_src1_is_ms_dest
+
+
+ es_src2_is_es_dest
+ es_src2_is_es_dest
+
+
+ es_src2_is_ms_dest
+ es_src2_is_ms_dest
+
+
+ es_data_is_rf_wdata
+ es_data_is_rf_wdata
+
+
+ br_target[31:0]
+ br_target[31:0]
+
+
+ es_alu_src1[31:0]
+ es_alu_src1[31:0]
+
+
+ es_alu_src2[31:0]
+ es_alu_src2[31:0]
+
+
+ es_alu_result[31:0]
+ es_alu_result[31:0]
+
+
+ es_Carry
+ es_Carry
+
+
+ es_Sign
+ es_Sign
+
+
+ es_Overflow
+ es_Overflow
+
+
+ es_Zero
+ es_Zero
+
+
+ es_inst_divw
+ es_inst_divw
+
+
+ es_inst_modw
+ es_inst_modw
+
+
+ es_inst_divwu
+ es_inst_divwu
+
+
+ es_inst_modwu
+ es_inst_modwu
+
+
+ div_op[1:0]
+ div_op[1:0]
+
+
+ div_stall
+ div_stall
+
+
+
+ mem_stage
+ label
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ ws_allowin
+ ws_allowin
+
+
+ ms_allowin
+ ms_allowin
+
+
+ es_to_ms_valid
+ es_to_ms_valid
+
+
+ es_to_ms_bus[122:0]
+ es_to_ms_bus[122:0]
+
+
+ ms_to_ws_valid
+ ms_to_ws_valid
+
+
+ ms_to_ws_bus[69:0]
+ ms_to_ws_bus[69:0]
+
+
+ br_bus[32:0]
+ br_bus[32:0]
+
+
+ data_sram_rdata[31:0]
+ data_sram_rdata[31:0]
+
+
+ ms_to_fw_bus[5:0]
+ ms_to_fw_bus[5:0]
+
+
+ ms_to_es_bus[31:0]
+ ms_to_es_bus[31:0]
+
+
+ div_result[31:0]
+ div_result[31:0]
+
+
+ mod_result[31:0]
+ mod_result[31:0]
+
+
+ ms_valid
+ ms_valid
+
+
+ ms_ready_go
+ ms_ready_go
+
+
+ es_to_ms_bus_r[122:0]
+ es_to_ms_bus_r[122:0]
+
+
+ br_target[31:0]
+ br_target[31:0]
+
+
+ ms_branch_op[8:0]
+ ms_branch_op[8:0]
+
+
+ ms_load_op[4:0]
+ ms_load_op[4:0]
+
+
+ ms_store_op[2:0]
+ ms_store_op[2:0]
+
+
+ ms_mem_to_reg
+ ms_mem_to_reg
+
+
+ ms_reg_we
+ ms_reg_we
+
+
+ ms_dest[4:0]
+ ms_dest[4:0]
+
+
+ ms_alu_result[31:0]
+ ms_alu_result[31:0]
+
+
+ ms_pc[31:0]
+ ms_pc[31:0]
+
+
+ ms_div_op[1:0]
+ ms_div_op[1:0]
+
+
+ ms_Carry
+ ms_Carry
+
+
+ ms_Sign
+ ms_Sign
+
+
+ ms_Overflow
+ ms_Overflow
+
+
+ ms_Zero
+ ms_Zero
+
+
+ br_taken
+ br_taken
+
+
+ mem_result[31:0]
+ mem_result[31:0]
+
+
+ ms_final_result[31:0]
+ ms_final_result[31:0]
+
+
+
+ wb_stage
+ label
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ ws_allowin
+ ws_allowin
+
+
+ ms_to_ws_valid
+ ms_to_ws_valid
+
+
+ ms_to_ws_bus[69:0]
+ ms_to_ws_bus[69:0]
+
+
+ ws_to_rf_bus[37:0]
+ ws_to_rf_bus[37:0]
+
+
+ ws_to_es_bus[31:0]
+ ws_to_es_bus[31:0]
+
+
+ debug_wb_pc[31:0]
+ debug_wb_pc[31:0]
+
+
+ debug_wb_rf_wen[3:0]
+ debug_wb_rf_wen[3:0]
+
+
+ debug_wb_rf_wnum[4:0]
+ debug_wb_rf_wnum[4:0]
+
+
+ debug_wb_rf_wdata[31:0]
+ debug_wb_rf_wdata[31:0]
+
+
+ ws_valid
+ ws_valid
+
+
+ ws_ready_go
+ ws_ready_go
+
+
+ ms_to_ws_bus_r[69:0]
+ ms_to_ws_bus_r[69:0]
+
+
+ ws_gr_we
+ ws_gr_we
+
+
+ ws_dest[4:0]
+ ws_dest[4:0]
+
+
+ ws_final_result[31:0]
+ ws_final_result[31:0]
+
+
+ ws_pc[31:0]
+ ws_pc[31:0]
+
+
+ rf_we
+ rf_we
+
+
+ rf_waddr[4:0]
+ rf_waddr[4:0]
+
+
+ rf_wdata[31:0]
+ rf_wdata[31:0]
+
+
+ ws_reg_we
+ ws_reg_we
+
+
+
+ forward
+ label
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ ds_to_fw_bus[9:0]
+ ds_to_fw_bus[9:0]
+
+
+ es_to_fw_bus[11:0]
+ es_to_fw_bus[11:0]
+
+
+ ms_to_fw_bus[5:0]
+ ms_to_fw_bus[5:0]
+
+
+ fw_to_es_bus[4:0]
+ fw_to_es_bus[4:0]
+
+
+ ds_to_fw_bus_r[9:0]
+ ds_to_fw_bus_r[9:0]
+
+
+ es_to_fw_bus_r[11:0]
+ es_to_fw_bus_r[11:0]
+
+
+ ms_to_fw_bus_r[5:0]
+ ms_to_fw_bus_r[5:0]
+
+
+ ds_rf_raddr1[4:0]
+ ds_rf_raddr1[4:0]
+
+
+ ds_rf_raddr2[4:0]
+ ds_rf_raddr2[4:0]
+
+
+ es_rf_raddr2[4:0]
+ es_rf_raddr2[4:0]
+
+
+ es_dest[4:0]
+ es_dest[4:0]
+
+
+ ms_dest[4:0]
+ ms_dest[4:0]
+
+
+ es_mem_we
+ es_mem_we
+
+
+ es_reg_we
+ es_reg_we
+
+
+ ms_reg_we
+ ms_reg_we
+
+
+ src1_is_es_dest
+ src1_is_es_dest
+
+
+ src1_is_ms_dest
+ src1_is_ms_dest
+
+
+ src2_is_es_dest
+ src2_is_es_dest
+
+
+ src2_is_ms_dest
+ src2_is_ms_dest
+
+
+ data_is_rf_wdata
+ data_is_rf_wdata
+
+
+
+ div
+ label
+
+ div_clk
+ div_clk
+
+
+ reset
+ reset
+
+
+ div
+ div
+
+
+ div_signed
+ div_signed
+
+
+ x[31:0]
+ x[31:0]
+
+
+ y[31:0]
+ y[31:0]
+
+
+ s[31:0]
+ s[31:0]
+
+
+ r[31:0]
+ r[31:0]
+
+
+ complete
+ complete
+
+
+ UnsignS[32:0]
+ UnsignS[32:0]
+
+
+ UnsignR[32:0]
+ UnsignR[32:0]
+
+
+ tmp_r[32:0]
+ tmp_r[32:0]
+
+
+ count[7:0]
+ count[7:0]
+
+
+ tmp_d[32:0]
+ tmp_d[32:0]
+
+
+ result_r[32:0]
+ result_r[32:0]
+
+
+ UnsignX[32:0]
+ UnsignX[32:0]
+
+
+ UnsignY[32:0]
+ UnsignY[32:0]
+
+
+ div_signed_buffer
+ div_signed_buffer
+
+
+ x_31_buffer
+ x_31_buffer
+
+
+ y_31_buffer
+ y_31_buffer
+
+
+ real_div_signed
+ real_div_signed
+
+
+ real_x_31
+ real_x_31
+
+
+ real_y_31
+ real_y_31
+
+
+ complete_delay
+ complete_delay
+
+
+ real_complete
+ real_complete
+
+
+ TmpS[32:0]
+ TmpS[32:0]
+
+
+ TmpR[32:0]
+ TmpR[32:0]
+
+
+
+
+ regfile
+ label
+
+ clk
+ clk
+
+
+ raddr1[4:0]
+ raddr1[4:0]
+
+
+ rdata1[31:0]
+ rdata1[31:0]
+
+
+ raddr2[4:0]
+ raddr2[4:0]
+
+
+ rdata2[31:0]
+ rdata2[31:0]
+
+
+ we
+ we
+
+
+ waddr[4:0]
+ waddr[4:0]
+
+
+ wdata[31:0]
+ wdata[31:0]
+
+
+ rf[31:0][31:0]
+ rf[31:0][31:0]
+
+
+
diff --git a/lacpu/run_vivado/la32r/sim/soc_tb.v b/lacpu/run_vivado/la32r/sim/soc_tb.v
new file mode 100644
index 0000000..95dda79
--- /dev/null
+++ b/lacpu/run_vivado/la32r/sim/soc_tb.v
@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps
+
+module cpu_tb(
+
+ );
+ reg resetn;
+ reg clk;
+ wire [31:0] debug_wb_pc;
+ wire [ 3:0] debug_wb_rf_wen;
+ wire [ 4:0] debug_wb_rf_wnum;
+ wire [31:0] debug_wb_rf_wdata;
+
+ initial
+ begin
+ clk = 1'b0;
+ resetn = 1'b0;
+ #20;
+ resetn = 1'b1;
+ #2000;
+ $finish;
+ end
+ always #5 clk=~clk;
+
+ soc_lite_top u_soc_top(
+ .resetn (resetn ),
+ .clk (clk ),
+
+ .pc ()
+ );
+
+ //debug signals
+ assign debug_wb_pc = u_soc_top.debug_wb_pc;
+ assign debug_wb_rf_wen = u_soc_top.debug_wb_rf_wen;
+ assign debug_wb_rf_wnum = u_soc_top.debug_wb_rf_wnum;
+ assign debug_wb_rf_wdata = u_soc_top.debug_wb_rf_wdata;
+
+ always @(posedge clk) begin
+ $display("PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
+ debug_wb_pc, debug_wb_rf_wnum, debug_wb_rf_wdata);
+ end
+
+
+endmodule