From f59260619645aeb9fe97491d207eca78628caf8f Mon Sep 17 00:00:00 2001 From: UnbalancedCat Date: Thu, 8 Jun 2023 16:27:48 +0800 Subject: [PATCH] [Modified] Fix louduse --- .gitignore | 3 + lacpu/rtl/cpu/exe_stage.v | 21 +- lacpu/rtl/cpu/id_stage.v | 7 +- lacpu/rtl/cpu/loaduse.v | 19 - lacpu/rtl/cpu/mycpu_top.v | 17 +- lacpu/rtl/xilinx_ip/data_ram/data_ram.coe | 3 + lacpu/rtl/xilinx_ip/data_ram/data_ram.xci | 10 +- lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe | 2 + lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci | 10 +- lacpu/run_vivado/la32r/la32r.xpr | 68 +- lacpu/run_vivado/la32r/sim/cpu_tb_behav.wcfg | 1236 ++++++++++++++++++ lacpu/run_vivado/la32r/sim/soc_tb.v | 43 + 12 files changed, 1352 insertions(+), 87 deletions(-) delete mode 100644 lacpu/rtl/cpu/loaduse.v create mode 100644 lacpu/rtl/xilinx_ip/data_ram/data_ram.coe create mode 100644 lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe create mode 100644 lacpu/run_vivado/la32r/sim/cpu_tb_behav.wcfg create mode 100644 lacpu/run_vivado/la32r/sim/soc_tb.v diff --git a/.gitignore b/.gitignore index 44e1c46..f05f7eb 100644 --- a/.gitignore +++ b/.gitignore @@ -11,4 +11,7 @@ vivado.jou vivado.log !/lacpu/run_vivado/la32r/la32r.xpr !/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci +!/lacpu/run_vivado/la32r/sim +!/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe !/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci +!/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe diff --git a/lacpu/rtl/cpu/exe_stage.v b/lacpu/rtl/cpu/exe_stage.v index 22b37ba..cb18874 100755 --- a/lacpu/rtl/cpu/exe_stage.v +++ b/lacpu/rtl/cpu/exe_stage.v @@ -24,9 +24,6 @@ module exe_stage( input [`MS_TO_ES_BUS_WD -1:0] ms_to_ds_bus , //from ws input [`WS_TO_ES_BUS_WD -1:0] ws_to_ds_bus , - //lu - output [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus , - input lu_to_es_bus , //div_mul output es_div_enable , output es_div_sign , @@ -62,8 +59,6 @@ module exe_stage( wire es_src2_is_ms_dest; wire es_data_is_rf_wdata; - reg loaduse_r; - assign {es_alu_op , //173:155 es_src1_is_pc , //154:154 es_src2_is_imm , //153:153 @@ -129,9 +124,7 @@ module exe_stage( es_mem_we }; - assign es_to_lu_bus = {es_dest, es_load_op}; - - assign es_ready_go = !(div_stall || loaduse_r); + assign es_ready_go = !(div_stall); assign es_allowin = !es_valid || es_ready_go && ms_allowin; assign es_to_ms_valid = es_valid && es_ready_go; always @(posedge clk) begin @@ -150,18 +143,6 @@ module exe_stage( end end - always @(posedge clk) begin - if(reset) begin - loaduse_r <= 1'b0; - end - else if(loaduse_r == 1'b1) begin - loaduse_r <= 1'b0; - end - else begin - loaduse_r <= lu_to_es_bus; - end - end - assign es_alu_src1 = es_src1_is_pc ? es_pc : es_src1_is_es_dest ? ms_alu_result : es_src1_is_ms_dest ? ws_rf_wdata : diff --git a/lacpu/rtl/cpu/id_stage.v b/lacpu/rtl/cpu/id_stage.v index 87335e2..cbeed89 100755 --- a/lacpu/rtl/cpu/id_stage.v +++ b/lacpu/rtl/cpu/id_stage.v @@ -16,10 +16,7 @@ module id_stage( //to fs input [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus , //to fw - output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus , - //to lu - output [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus - + output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus ); reg ds_valid ; @@ -140,8 +137,6 @@ module id_stage( assign ds_to_fw_bus = {rf_raddr1 , rf_raddr2}; - assign ds_to_lu_bus = {rf_raddr1 , rf_raddr2}; - assign ds_ready_go = 1'b1; assign ds_allowin = !ds_valid || ds_ready_go && es_allowin; assign ds_to_es_valid = ds_valid && ds_ready_go; diff --git a/lacpu/rtl/cpu/loaduse.v b/lacpu/rtl/cpu/loaduse.v deleted file mode 100644 index 197da7f..0000000 --- a/lacpu/rtl/cpu/loaduse.v +++ /dev/null @@ -1,19 +0,0 @@ -`include "mycpu.vh" - -module loaduse( - input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus, - input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus, - - output lu_to_es_bus -); - wire [4:0] ds_rf_raddr1; - wire [4:0] ds_rf_raddr2; - wire [4:0] es_load_op; - wire [4:0] es_dest; - - assign {ds_rf_raddr1, ds_rf_raddr2} = ds_to_lu_bus; - assign {es_dest , es_load_op } = es_to_lu_bus; - - assign lu_to_es_bus = ^es_load_op && - (((ds_rf_raddr1 == es_dest) && (ds_rf_raddr1 != 5'b0)) || ((ds_rf_raddr2 == es_dest) && (ds_rf_raddr2 != 5'b0))); -endmodule \ No newline at end of file diff --git a/lacpu/rtl/cpu/mycpu_top.v b/lacpu/rtl/cpu/mycpu_top.v index a78c66e..ea4e5af 100644 --- a/lacpu/rtl/cpu/mycpu_top.v +++ b/lacpu/rtl/cpu/mycpu_top.v @@ -44,9 +44,6 @@ module mycpu_top( wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus; wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus; wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus; - wire [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus; - wire [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus; - wire lu_to_es_bus; wire es_div_enable; wire es_div_sign; @@ -91,9 +88,7 @@ module mycpu_top( //to rf: for write back .ws_to_rf_bus (ws_to_rf_bus ), //to fw - .ds_to_fw_bus (ds_to_fw_bus ), - //to lu - .ds_to_lu_bus (ds_to_lu_bus ) + .ds_to_fw_bus (ds_to_fw_bus ) ); // EXE stage exe_stage exe_stage( @@ -116,10 +111,6 @@ module mycpu_top( .ms_to_ds_bus (ms_to_es_bus ), //from ws .ws_to_ds_bus (ws_to_es_bus ), - //to lu - .es_to_lu_bus (es_to_lu_bus ), - //from lu - .lu_to_es_bus (lu_to_es_bus ), // data sram interface .data_sram_en (data_sram_en ), .data_sram_wen (data_sram_we ), @@ -201,11 +192,5 @@ module mycpu_top( .ms_to_fw_bus (ms_to_fw_bus), .fw_to_es_bus (fw_to_es_bus) ); - //Loaduse - loaduse loaduse( - .ds_to_lu_bus (ds_to_lu_bus), - .es_to_lu_bus (es_to_lu_bus), - .lu_to_es_bus (lu_to_es_bus) - ); endmodule diff --git a/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe b/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe new file mode 100644 index 0000000..9ef4a6f --- /dev/null +++ b/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe @@ -0,0 +1,3 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +00000001 diff --git a/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci b/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci index 4c94830..92255e0 100644 --- a/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci +++ b/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci @@ -131,9 +131,9 @@ 0 0 data_ram.mem - no_coe_file_loaded + data_ram.mif 0 - 0 + 1 0 0 1 @@ -172,7 +172,7 @@ false 8 NONE - no_coe_file_loaded + ./data_ram.coe ALL data_ram false @@ -189,7 +189,7 @@ Single_Bit_Error_Injection false Native - false + true no_mem_loaded Single_Port_RAM WRITE_FIRST @@ -296,6 +296,8 @@ + + diff --git a/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe b/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe new file mode 100644 index 0000000..14985ca --- /dev/null +++ b/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe @@ -0,0 +1,2 @@ +memory_initialization_radix=16; +memory_initialization_vector=28800401 02800822; diff --git a/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci b/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci index a439f35..b51d51b 100644 --- a/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci +++ b/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci @@ -131,9 +131,9 @@ 0 0 inst_ram.mem - no_coe_file_loaded + inst_ram.mif 0 - 0 + 1 0 0 1 @@ -172,7 +172,7 @@ false 8 NONE - no_coe_file_loaded + inst_ram.coe ALL inst_ram false @@ -189,7 +189,7 @@ Single_Bit_Error_Injection false Native - false + true no_mem_loaded Single_Port_RAM WRITE_FIRST @@ -296,6 +296,8 @@ + + diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr index 5253f87..94f69c1 100644 --- a/lacpu/run_vivado/la32r/la32r.xpr +++ b/lacpu/run_vivado/la32r/la32r.xpr @@ -29,20 +29,20 @@