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[Modified] Fix louduse

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包焕垲
2023-06-08 16:27:48 +08:00
parent e8926ed8a4
commit f592606196
12 changed files with 1352 additions and 87 deletions
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21
lacpu/rtl/cpu/exe_stage.v
View File

@@ -24,9 +24,6 @@ module exe_stage(
input [`MS_TO_ES_BUS_WD -1:0] ms_to_ds_bus ,
//from ws
input [`WS_TO_ES_BUS_WD -1:0] ws_to_ds_bus ,
//lu
output [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus ,
input lu_to_es_bus ,
//div_mul
output es_div_enable ,
output es_div_sign ,
@@ -62,8 +59,6 @@ module exe_stage(
wire es_src2_is_ms_dest;
wire es_data_is_rf_wdata;
reg loaduse_r;
assign {es_alu_op , //173:155
es_src1_is_pc , //154:154
es_src2_is_imm , //153:153
@@ -129,9 +124,7 @@ module exe_stage(
es_mem_we
};
assign es_to_lu_bus = {es_dest, es_load_op};
assign es_ready_go = !(div_stall || loaduse_r);
assign es_ready_go = !(div_stall);
assign es_allowin = !es_valid || es_ready_go && ms_allowin;
assign es_to_ms_valid = es_valid && es_ready_go;
always @(posedge clk) begin
@@ -150,18 +143,6 @@ module exe_stage(
end
end
always @(posedge clk) begin
if(reset) begin
loaduse_r <= 1'b0;
end
else if(loaduse_r == 1'b1) begin
loaduse_r <= 1'b0;
end
else begin
loaduse_r <= lu_to_es_bus;
end
end
assign es_alu_src1 = es_src1_is_pc ? es_pc :
es_src1_is_es_dest ? ms_alu_result :
es_src1_is_ms_dest ? ws_rf_wdata :

7
lacpu/rtl/cpu/id_stage.v
View File

@@ -16,10 +16,7 @@ module id_stage(
//to fs
input [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus ,
//to fw
output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus ,
//to lu
output [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus
output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus
);
reg ds_valid ;
@@ -140,8 +137,6 @@ module id_stage(
assign ds_to_fw_bus = {rf_raddr1 , rf_raddr2};
assign ds_to_lu_bus = {rf_raddr1 , rf_raddr2};
assign ds_ready_go = 1'b1;
assign ds_allowin = !ds_valid || ds_ready_go && es_allowin;
assign ds_to_es_valid = ds_valid && ds_ready_go;

19
lacpu/rtl/cpu/loaduse.v
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@@ -1,19 +0,0 @@
`include "mycpu.vh"
module loaduse(
input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus,
output lu_to_es_bus
);
wire [4:0] ds_rf_raddr1;
wire [4:0] ds_rf_raddr2;
wire [4:0] es_load_op;
wire [4:0] es_dest;
assign {ds_rf_raddr1, ds_rf_raddr2} = ds_to_lu_bus;
assign {es_dest , es_load_op } = es_to_lu_bus;
assign lu_to_es_bus = ^es_load_op &&
(((ds_rf_raddr1 == es_dest) && (ds_rf_raddr1 != 5'b0)) || ((ds_rf_raddr2 == es_dest) && (ds_rf_raddr2 != 5'b0)));
endmodule

17
lacpu/rtl/cpu/mycpu_top.v
View File

@@ -44,9 +44,6 @@ module mycpu_top(
wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus;
wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
wire [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus;
wire [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus;
wire lu_to_es_bus;
wire es_div_enable;
wire es_div_sign;
@@ -91,9 +88,7 @@ module mycpu_top(
//to rf: for write back
.ws_to_rf_bus (ws_to_rf_bus ),
//to fw
.ds_to_fw_bus (ds_to_fw_bus ),
//to lu
.ds_to_lu_bus (ds_to_lu_bus )
.ds_to_fw_bus (ds_to_fw_bus )
);
// EXE stage
exe_stage exe_stage(
@@ -116,10 +111,6 @@ module mycpu_top(
.ms_to_ds_bus (ms_to_es_bus ),
//from ws
.ws_to_ds_bus (ws_to_es_bus ),
//to lu
.es_to_lu_bus (es_to_lu_bus ),
//from lu
.lu_to_es_bus (lu_to_es_bus ),
// data sram interface
.data_sram_en (data_sram_en ),
.data_sram_wen (data_sram_we ),
@@ -201,11 +192,5 @@ module mycpu_top(
.ms_to_fw_bus (ms_to_fw_bus),
.fw_to_es_bus (fw_to_es_bus)
);
//Loaduse
loaduse loaduse(
.ds_to_lu_bus (ds_to_lu_bus),
.es_to_lu_bus (es_to_lu_bus),
.lu_to_es_bus (lu_to_es_bus)
);
endmodule