redo axi construction
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@@ -3,7 +3,7 @@
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="44" Path="D:/project/Vivado/project/AX7325/ddr_general_design/ddr_general_design.xpr">
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<Project Version="7" Minor="44" Path="D:/Project/Vivado/AX7325/ddr3_general_design/ddr_general_design.xpr">
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@@ -36,13 +36,13 @@
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<Option Name="WTXSimExportSim" Val="1"/>
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<Option Name="WTVcsExportSim" Val="1"/>
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<Option Name="WTRivieraExportSim" Val="1"/>
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<Option Name="WTActivehdlExportSim" Val="1"/>
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<Option Name="WTXSimExportSim" Val="7"/>
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<Option Name="WTModelSimExportSim" Val="7"/>
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<Option Name="WTQuestaExportSim" Val="7"/>
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<Option Name="WTIesExportSim" Val="7"/>
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<Option Name="WTVcsExportSim" Val="7"/>
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<Option Name="WTRivieraExportSim" Val="7"/>
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<Option Name="WTActivehdlExportSim" Val="7"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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@@ -65,14 +65,66 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/pcie_ddr/hdl/pcie_ddr_wrapper.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="ScopedToCell" Val="ddr3_mig"/>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="ddr_ctrl_top"/>
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<Option Name="TopModule" Val="pcie_ddr_wrapper"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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@@ -86,6 +138,8 @@
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<Filter Type="Srcs"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="pcie_ddr_wrapper"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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@@ -99,6 +153,48 @@
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="ddr3_mig" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ddr3_mig">
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<File Path="$PSRCDIR/sources_1/ip/ddr3_mig/ddr3_mig.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="ddr3_mig"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="fifo_ddr_wdara" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_wdara">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_wdara/fifo_ddr_wdara.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
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<Config>
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<Option Name="TopModule" Val="fifo_ddr_wdara"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="fifo_ddr_rdata" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_rdata">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_rdata/fifo_ddr_rdata.xci">
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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<Config>
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<Option Name="TopModule" Val="fifo_ddr_rdata"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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@@ -128,6 +224,40 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="ddr3_mig_synth_1" Type="Ft3:Synth" SrcSet="ddr3_mig" Part="xc7k325tffg900-2" ConstrsSet="ddr3_mig" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ddr3_mig_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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<Step Id="synth_design"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_wdara_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_wdara" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_wdara" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_wdara_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
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<RQSFiles/>
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</Run>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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<Strategy Version="1" Minor="2">
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@@ -145,6 +275,61 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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<Run Id="fifo_ddr_rdata_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_rdata" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_rdata_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Desc>Default settings for Implementation.</Desc>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Runs>
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<Board/>
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<DashboardSummary Version="1" Minor="0">
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