FPGALab/ddr3_general_design
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UnbalancedCat 43b95e063d fix fifo ctrl bug
2025-05-16 16:27:46 +08:00
ddr3_general_design.srcs
fix fifo ctrl bug
2025-05-16 16:27:46 +08:00
.gitignore
v2.0_fifo_interface
2025-04-27 19:10:44 +08:00
ddr3_general_design.xpr
fix fifo ctrl bug
2025-05-16 16:27:46 +08:00
Description
基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板
59 MiB
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Verilog 100%