FPGALab/ddr3_general_design
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fix fifo ctrl bug

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包焕垲
2025-05-16 16:27:46 +08:00
parent b6dea8b6e0
commit 43b95e063d
2 changed files with 24 additions and 46 deletions
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20
ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v
View File

@@ -140,14 +140,14 @@ module ddr_axi_m_top #(
wire fifo_ddr_wstrb_full;
assign fifo_ddr_rd_almost_full_o = fifo_ddr_rd_addr_almost_full & fifo_ddr_rd_len_almost_full;
assign fifo_ddr_rd_full_o = fifo_ddr_rd_addr_full & fifo_ddr_rd_len_full;
assign fifo_ddr_rd_almost_full_o = fifo_ddr_rd_addr_almost_full | fifo_ddr_rd_len_almost_full;
assign fifo_ddr_rd_full_o = fifo_ddr_rd_addr_full | fifo_ddr_rd_len_full;
assign fifo_ddr_wr_almost_full_o = fifo_ddr_wr_addr_almost_full & fifo_ddr_wr_len_almost_full;
assign fifo_ddr_wr_full_o = fifo_ddr_wr_addr_full & fifo_ddr_wr_len_full;
assign fifo_ddr_wr_almost_full_o = fifo_ddr_wr_addr_almost_full | fifo_ddr_wr_len_almost_full;
assign fifo_ddr_wr_full_o = fifo_ddr_wr_addr_full | fifo_ddr_wr_len_full;
assign fifo_ddr_wdata_almost_full_o = fifo_ddr_wdata_almost_full & fifo_ddr_wstrb_almost_full;
assign fifo_ddr_wdata_full_o = fifo_ddr_wdata_full & fifo_ddr_wstrb_full;
assign fifo_ddr_wdata_almost_full_o = fifo_ddr_wdata_almost_full | fifo_ddr_wstrb_almost_full;
assign fifo_ddr_wdata_full_o = fifo_ddr_wdata_full | fifo_ddr_wstrb_full;
ddr_axi_m_rd #(
.ADDR_WIDTH (ADDR_WIDTH ),
@@ -173,9 +173,9 @@ module ddr_axi_m_top #(
.m_axi_rresp_i (m_axi_rresp_i ),
.m_axi_rlast_i (m_axi_rlast_i ),
.m_axi_rvalid_i (m_axi_rvalid_i ),
.fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty & fifo_ddr_rd_len_empty),
.fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty | fifo_ddr_rd_len_empty),
.fifo_ddr_rd_rd_en_o (fifo_ddr_rd_rd_en ),
.fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v ),
.fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v),
.fifo_ddr_rd_addr_i (fifo_ddr_rd_addr ),
.fifo_ddr_rd_len_i (fifo_ddr_rd_len ),
.fifo_ddr_rdata_almost_full_i (fifo_ddr_rdata_almost_full ),
@@ -211,12 +211,12 @@ module ddr_axi_m_top #(
.m_axi_bid_i (m_axi_bid_i ),
.m_axi_bresp_i (m_axi_bresp_i ),
.m_axi_bvalid_i (m_axi_bvalid_i ),
.fifo_ddr_wr_empty_i (fifo_ddr_wr_addr_empty & fifo_ddr_wr_len_empty),
.fifo_ddr_wr_empty_i (fifo_ddr_wr_addr_empty | fifo_ddr_wr_len_empty),
.fifo_ddr_wr_rd_en_o (fifo_ddr_wr_rd_en ),
.fifo_ddr_wr_v_i (fifo_ddr_wr_addr_v & fifo_ddr_wr_len_v),
.fifo_ddr_wr_addr_i (fifo_ddr_wr_addr ),
.fifo_ddr_wr_len_i (fifo_ddr_wr_len ),
.fifo_ddr_wdata_empty_i (fifo_ddr_wdata_empty & fifo_ddr_wstrb_empty),
.fifo_ddr_wdata_empty_i (fifo_ddr_wdata_empty | fifo_ddr_wstrb_empty),
.fifo_ddr_wdata_rd_en_o (fifo_ddr_wdata_rd_en ),
.fifo_ddr_wdata_v_i (fifo_ddr_wdata_v & fifo_ddr_wstrb_v),
.fifo_ddr_wdata_i (fifo_ddr_wdata ),

50
ddr3_general_design.xpr
View File

@@ -98,6 +98,7 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ddr_axi_m_top"/>
@@ -118,6 +119,7 @@
<FileSet Name="ddr3_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ddr3_ctrl">
<File Path="$PSRCDIR/sources_1/ip/ddr3_ctrl/ddr3_ctrl.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -202,9 +204,7 @@
<Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
@@ -213,9 +213,7 @@
</Run>
<Run Id="ddr3_ctrl_synth_1" Type="Ft3:Synth" SrcSet="ddr3_ctrl" Part="xc7k325tffg900-2" ConstrsSet="ddr3_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ddr3_ctrl_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -225,9 +223,7 @@
</Run>
<Run Id="fifo_ddr_addr_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_addr" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_addr" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_addr_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -237,9 +233,7 @@
</Run>
<Run Id="fifo_ddr_len_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_len" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_len" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_len_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -249,9 +243,7 @@
</Run>
<Run Id="fifo_ddr_data_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_data" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_data" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_data_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -261,9 +253,7 @@
</Run>
<Run Id="fifo_ddr_strb_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_strb" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_strb" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_strb_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -273,9 +263,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -292,9 +280,7 @@
</Run>
<Run Id="ddr3_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="ddr3_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ddr3_ctrl_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -311,9 +297,7 @@
</Run>
<Run Id="fifo_ddr_addr_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_addr" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_addr_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -330,9 +314,7 @@
</Run>
<Run Id="fifo_ddr_len_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_len" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_len_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -349,9 +331,7 @@
</Run>
<Run Id="fifo_ddr_data_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_data" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_data_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -368,9 +348,7 @@
</Run>
<Run Id="fifo_ddr_strb_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_strb" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_strb_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>