From 43b95e063d3707eb909583e0ec439042b015f05a Mon Sep 17 00:00:00 2001 From: UnbalancedCat Date: Fri, 16 May 2025 16:27:46 +0800 Subject: [PATCH] fix fifo ctrl bug --- .../sources_1/new/ddr_axi_m_top.v | 20 ++++---- ddr3_general_design.xpr | 50 ++++++------------- 2 files changed, 24 insertions(+), 46 deletions(-) diff --git a/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v b/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v index f700ee6..47c8610 100644 --- a/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v +++ b/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v @@ -140,14 +140,14 @@ module ddr_axi_m_top #( wire fifo_ddr_wstrb_full; - assign fifo_ddr_rd_almost_full_o = fifo_ddr_rd_addr_almost_full & fifo_ddr_rd_len_almost_full; - assign fifo_ddr_rd_full_o = fifo_ddr_rd_addr_full & fifo_ddr_rd_len_full; + assign fifo_ddr_rd_almost_full_o = fifo_ddr_rd_addr_almost_full | fifo_ddr_rd_len_almost_full; + assign fifo_ddr_rd_full_o = fifo_ddr_rd_addr_full | fifo_ddr_rd_len_full; - assign fifo_ddr_wr_almost_full_o = fifo_ddr_wr_addr_almost_full & fifo_ddr_wr_len_almost_full; - assign fifo_ddr_wr_full_o = fifo_ddr_wr_addr_full & fifo_ddr_wr_len_full; + assign fifo_ddr_wr_almost_full_o = fifo_ddr_wr_addr_almost_full | fifo_ddr_wr_len_almost_full; + assign fifo_ddr_wr_full_o = fifo_ddr_wr_addr_full | fifo_ddr_wr_len_full; - assign fifo_ddr_wdata_almost_full_o = fifo_ddr_wdata_almost_full & fifo_ddr_wstrb_almost_full; - assign fifo_ddr_wdata_full_o = fifo_ddr_wdata_full & fifo_ddr_wstrb_full; + assign fifo_ddr_wdata_almost_full_o = fifo_ddr_wdata_almost_full | fifo_ddr_wstrb_almost_full; + assign fifo_ddr_wdata_full_o = fifo_ddr_wdata_full | fifo_ddr_wstrb_full; ddr_axi_m_rd #( .ADDR_WIDTH (ADDR_WIDTH ), @@ -173,9 +173,9 @@ module ddr_axi_m_top #( .m_axi_rresp_i (m_axi_rresp_i ), .m_axi_rlast_i (m_axi_rlast_i ), .m_axi_rvalid_i (m_axi_rvalid_i ), - .fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty & fifo_ddr_rd_len_empty), + .fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty | fifo_ddr_rd_len_empty), .fifo_ddr_rd_rd_en_o (fifo_ddr_rd_rd_en ), - .fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v ), + .fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v), .fifo_ddr_rd_addr_i (fifo_ddr_rd_addr ), .fifo_ddr_rd_len_i (fifo_ddr_rd_len ), .fifo_ddr_rdata_almost_full_i (fifo_ddr_rdata_almost_full ), @@ -211,12 +211,12 @@ module ddr_axi_m_top #( .m_axi_bid_i (m_axi_bid_i ), .m_axi_bresp_i (m_axi_bresp_i ), .m_axi_bvalid_i (m_axi_bvalid_i ), - .fifo_ddr_wr_empty_i (fifo_ddr_wr_addr_empty & fifo_ddr_wr_len_empty), + .fifo_ddr_wr_empty_i (fifo_ddr_wr_addr_empty | fifo_ddr_wr_len_empty), .fifo_ddr_wr_rd_en_o (fifo_ddr_wr_rd_en ), .fifo_ddr_wr_v_i (fifo_ddr_wr_addr_v & fifo_ddr_wr_len_v), .fifo_ddr_wr_addr_i (fifo_ddr_wr_addr ), .fifo_ddr_wr_len_i (fifo_ddr_wr_len ), - .fifo_ddr_wdata_empty_i (fifo_ddr_wdata_empty & fifo_ddr_wstrb_empty), + .fifo_ddr_wdata_empty_i (fifo_ddr_wdata_empty | fifo_ddr_wstrb_empty), .fifo_ddr_wdata_rd_en_o (fifo_ddr_wdata_rd_en ), .fifo_ddr_wdata_v_i (fifo_ddr_wdata_v & fifo_ddr_wstrb_v), .fifo_ddr_wdata_i (fifo_ddr_wdata ), diff --git a/ddr3_general_design.xpr b/ddr3_general_design.xpr index 614d328..a123537 100644 --- a/ddr3_general_design.xpr +++ b/ddr3_general_design.xpr @@ -98,6 +98,7 @@ +