From cf3f100d539df6844289aa4a65b58eedc0868a8f Mon Sep 17 00:00:00 2001 From: UnbalancedCat Date: Tue, 18 Mar 2025 16:56:47 +0800 Subject: [PATCH] redo axi construction --- .../bd/pcie_ddr/hdl/pcie_ddr_wrapper.v | 276 + .../pcie_ddr_auto_cc_1/pcie_ddr_auto_cc_1.xci | 237 + .../pcie_ddr_auto_cc_1/pcie_ddr_auto_cc_1.xml | 4020 +++++++++ .../pcie_ddr_auto_cc_2/pcie_ddr_auto_cc_2.xci | 237 + .../pcie_ddr_auto_cc_2/pcie_ddr_auto_cc_2.xml | 4020 +++++++++ .../pcie_ddr_auto_cc_3/pcie_ddr_auto_cc_3.xci | 237 + .../pcie_ddr_auto_cc_3/pcie_ddr_auto_cc_3.xml | 4020 +++++++++ .../pcie_ddr_auto_us_0/pcie_ddr_auto_us_0.xci | 224 + .../pcie_ddr_auto_us_0/pcie_ddr_auto_us_0.xml | 3522 ++++++++ .../pcie_ddr_auto_us_1/pcie_ddr_auto_us_1.xci | 224 + .../pcie_ddr_auto_us_1/pcie_ddr_auto_us_1.xml | 3522 ++++++++ .../pcie_ddr_axi_interconnect_0_1.xci} | 4 +- .../pcie_ddr_axi_interconnect_0_1.xml} | 4 +- .../pcie_ddr_clk_wiz_0_0.xci | 12 +- .../pcie_ddr_clk_wiz_0_0.xml | 12 +- .../ip/pcie_ddr_mig_7series_0_0/mig_a.prj | 6 +- .../ip/pcie_ddr_mig_7series_0_0/mig_b.prj | 228 + .../pcie_ddr_mig_7series_0_0.veo | 8 +- .../pcie_ddr_mig_7series_0_0.xci | 42 +- .../pcie_ddr_mig_7series_0_0.xml | 52 +- .../pcie_ddr_mig_7series_0_0/datasheet.txt | 2 +- .../example_design/par/example_top.xdc | 2 +- .../example_design/rtl/example_top.v | 2 +- .../example_design/sim/sim_tb_top.v | 2 +- .../pcie_ddr_mig_7series_0_0/mig.prj | 2 +- .../constraints/pcie_ddr_mig_7series_0_0.xdc | 2 +- .../pcie_ddr_mig_7series_0_0_ooc.xdc | 2 +- .../rtl/pcie_ddr_mig_7series_0_0.v | 8 +- .../rtl/pcie_ddr_mig_7series_0_0_mig.v | 2 +- .../rtl/pcie_ddr_mig_7series_0_0_mig_sim.v | 2 +- .../ip/pcie_ddr_mig_7series_0_0/xil_txt.in | 6 +- .../pcie_ddr_rst_clk_wiz_0_200M_0.xci | 85 + .../pcie_ddr_rst_clk_wiz_0_200M_0.xml | 680 ++ .../pcie_ddr_rst_mig_7series_0_100M_4.xci} | 24 +- .../pcie_ddr_rst_mig_7series_0_100M_4.xml} | 24 +- .../pcie_ddr_s01_mmu_1/pcie_ddr_s01_mmu_1.xci | 998 +++ .../pcie_ddr_s01_mmu_1/pcie_ddr_s01_mmu_1.xml | 7556 +++++++++++++++++ .../pcie_ddr_util_ds_buf_0_0.xci | 4 +- .../pcie_ddr_util_ds_buf_0_0.xml | 4 +- .../pcie_ddr_xbar_1.xci} | 233 +- .../pcie_ddr_xbar_1.xml} | 883 +- .../pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xci | 6 +- .../pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xml | 6 +- .../sources_1/bd/pcie_ddr/pcie_ddr.bd | 517 +- .../sources_1/bd/pcie_ddr/pcie_ddr.bxml | 70 +- .../sources_1/bd/pcie_ddr/pcie_ddr_ooc.xdc | 12 + .../sources_1/bd/pcie_ddr/sim/pcie_ddr.v | 2977 +++++++ .../sources_1/bd/pcie_ddr/synth/pcie_ddr.v | 2977 +++++++ .../sources_1/bd/pcie_ddr/ui/bd_c1e426c2.ui | 96 +- .../sources_1/ip/ddr3_mig/ddr3_mig.xci | 2803 ++++++ .../ip/fifo_ddr_addr/fifo_ddr_addr.xci | 556 ++ .../ip/fifo_ddr_rdata/fifo_ddr_rdata.xci | 556 ++ .../ip/fifo_ddr_wdara/fifo_ddr_wdara.xci | 556 ++ .../sources_1/new/ddr_axi_rd.v | 137 + .../sources_1/new/ddr_axi_wr.v | 183 + .../sources_1/new/ddr_ctrl.v | 307 + ddr_general_design.xpr | 203 +- others/ddr3_top.vsdx | Bin 31001 -> 33876 bytes others/~$$ddr3_top.~vsdx | Bin 0 -> 4096 bytes 59 files changed, 42551 insertions(+), 841 deletions(-) create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/hdl/pcie_ddr_wrapper.v create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_1/pcie_ddr_auto_cc_1.xci create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_1/pcie_ddr_auto_cc_1.xml create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_2/pcie_ddr_auto_cc_2.xci create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_2/pcie_ddr_auto_cc_2.xml create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_3/pcie_ddr_auto_cc_3.xci create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_3/pcie_ddr_auto_cc_3.xml create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_us_0/pcie_ddr_auto_us_0.xci create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_us_0/pcie_ddr_auto_us_0.xml create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_us_1/pcie_ddr_auto_us_1.xci create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_us_1/pcie_ddr_auto_us_1.xml rename ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/{pcie_ddr_axi_interconnect_0_0/pcie_ddr_axi_interconnect_0_0.xci => pcie_ddr_axi_interconnect_0_1/pcie_ddr_axi_interconnect_0_1.xci} (99%) rename ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/{pcie_ddr_axi_interconnect_0_0/pcie_ddr_axi_interconnect_0_0.xml => pcie_ddr_axi_interconnect_0_1/pcie_ddr_axi_interconnect_0_1.xml} (99%) create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_b.prj create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_clk_wiz_0_200M_0/pcie_ddr_rst_clk_wiz_0_200M_0.xci create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_clk_wiz_0_200M_0/pcie_ddr_rst_clk_wiz_0_200M_0.xml rename ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/{pcie_ddr_rst_mig_7series_0_100M_2/pcie_ddr_rst_mig_7series_0_100M_2.xci => pcie_ddr_rst_mig_7series_0_100M_4/pcie_ddr_rst_mig_7series_0_100M_4.xci} (89%) rename ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/{pcie_ddr_rst_mig_7series_0_100M_2/pcie_ddr_rst_mig_7series_0_100M_2.xml => pcie_ddr_rst_mig_7series_0_100M_4/pcie_ddr_rst_mig_7series_0_100M_4.xml} (97%) create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_s01_mmu_1/pcie_ddr_s01_mmu_1.xci create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_s01_mmu_1/pcie_ddr_s01_mmu_1.xml rename ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/{pcie_ddr_xbar_0/pcie_ddr_xbar_0.xci => pcie_ddr_xbar_1/pcie_ddr_xbar_1.xci} (97%) rename ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/{pcie_ddr_xbar_0/pcie_ddr_xbar_0.xml => pcie_ddr_xbar_1/pcie_ddr_xbar_1.xml} (98%) create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr_ooc.xdc create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/sim/pcie_ddr.v create mode 100644 ddr_general_design.srcs/sources_1/bd/pcie_ddr/synth/pcie_ddr.v create mode 100644 ddr_general_design.srcs/sources_1/ip/ddr3_mig/ddr3_mig.xci create mode 100644 ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci create mode 100644 ddr_general_design.srcs/sources_1/ip/fifo_ddr_rdata/fifo_ddr_rdata.xci create mode 100644 ddr_general_design.srcs/sources_1/ip/fifo_ddr_wdara/fifo_ddr_wdara.xci create mode 100644 ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v create mode 100644 ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v create mode 100644 ddr_general_design.srcs/sources_1/new/ddr_ctrl.v create mode 100644 others/~$$ddr3_top.~vsdx diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/hdl/pcie_ddr_wrapper.v b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/hdl/pcie_ddr_wrapper.v new file mode 100644 index 0000000..edfa7e0 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/hdl/pcie_ddr_wrapper.v @@ -0,0 +1,276 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +//Date : Tue Mar 18 13:48:36 2025 +//Host : BHKLaptop running 64-bit major release (build 9200) +//Command : generate_target pcie_ddr_wrapper.bd +//Design : pcie_ddr_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module pcie_ddr_wrapper + (ddr_addr, + ddr_axi_araddr, + ddr_axi_arburst, + ddr_axi_arcache, + ddr_axi_arid, + ddr_axi_arlen, + ddr_axi_arlock, + ddr_axi_arprot, + ddr_axi_arqos, + ddr_axi_arready, + ddr_axi_arsize, + ddr_axi_arvalid, + ddr_axi_awaddr, + ddr_axi_awburst, + ddr_axi_awcache, + ddr_axi_awid, + ddr_axi_awlen, + ddr_axi_awlock, + ddr_axi_awprot, + ddr_axi_awqos, + ddr_axi_awready, + ddr_axi_awsize, + ddr_axi_awvalid, + ddr_axi_bid, + ddr_axi_bready, + ddr_axi_bresp, + ddr_axi_bvalid, + ddr_axi_rdata, + ddr_axi_rid, + ddr_axi_rlast, + ddr_axi_rready, + ddr_axi_rresp, + ddr_axi_rvalid, + ddr_axi_wdata, + ddr_axi_wlast, + ddr_axi_wready, + ddr_axi_wstrb, + ddr_axi_wvalid, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + init_calib_complete, + pcie_clk_clk_n, + pcie_clk_clk_p, + pcie_mgt_rxn, + pcie_mgt_rxp, + pcie_mgt_txn, + pcie_mgt_txp, + pcie_msi_enable, + pcie_user_lnk_up, + pcie_usr_irq_req, + sys_clk, + sys_rst_n_0, + sys_rstn); + output [15:0]ddr_addr; + input [31:0]ddr_axi_araddr; + input [1:0]ddr_axi_arburst; + input [3:0]ddr_axi_arcache; + input [0:0]ddr_axi_arid; + input [7:0]ddr_axi_arlen; + input [0:0]ddr_axi_arlock; + input [2:0]ddr_axi_arprot; + input [3:0]ddr_axi_arqos; + output ddr_axi_arready; + input [2:0]ddr_axi_arsize; + input ddr_axi_arvalid; + input [31:0]ddr_axi_awaddr; + input [1:0]ddr_axi_awburst; + input [3:0]ddr_axi_awcache; + input [0:0]ddr_axi_awid; + input [7:0]ddr_axi_awlen; + input [0:0]ddr_axi_awlock; + input [2:0]ddr_axi_awprot; + input [3:0]ddr_axi_awqos; + output ddr_axi_awready; + input [2:0]ddr_axi_awsize; + input ddr_axi_awvalid; + output [0:0]ddr_axi_bid; + input ddr_axi_bready; + output [1:0]ddr_axi_bresp; + output ddr_axi_bvalid; + output [31:0]ddr_axi_rdata; + output [0:0]ddr_axi_rid; + output ddr_axi_rlast; + input ddr_axi_rready; + output [1:0]ddr_axi_rresp; + output ddr_axi_rvalid; + input [31:0]ddr_axi_wdata; + input ddr_axi_wlast; + output ddr_axi_wready; + input [3:0]ddr_axi_wstrb; + input ddr_axi_wvalid; + output [2:0]ddr_ba; + output ddr_cas_n; + output [1:0]ddr_ck_n; + output [1:0]ddr_ck_p; + output [1:0]ddr_cke; + output [1:0]ddr_cs_n; + output [7:0]ddr_dm; + inout [63:0]ddr_dq; + inout [7:0]ddr_dqs_n; + inout [7:0]ddr_dqs_p; + output [1:0]ddr_odt; + output ddr_ras_n; + output ddr_reset_n; + output ddr_we_n; + output init_calib_complete; + input [0:0]pcie_clk_clk_n; + input [0:0]pcie_clk_clk_p; + input [7:0]pcie_mgt_rxn; + input [7:0]pcie_mgt_rxp; + output [7:0]pcie_mgt_txn; + output [7:0]pcie_mgt_txp; + output pcie_msi_enable; + output pcie_user_lnk_up; + input [0:0]pcie_usr_irq_req; + input sys_clk; + input sys_rst_n_0; + input sys_rstn; + + wire [15:0]ddr_addr; + wire [31:0]ddr_axi_araddr; + wire [1:0]ddr_axi_arburst; + wire [3:0]ddr_axi_arcache; + wire [0:0]ddr_axi_arid; + wire [7:0]ddr_axi_arlen; + wire [0:0]ddr_axi_arlock; + wire [2:0]ddr_axi_arprot; + wire [3:0]ddr_axi_arqos; + wire ddr_axi_arready; + wire [2:0]ddr_axi_arsize; + wire ddr_axi_arvalid; + wire [31:0]ddr_axi_awaddr; + wire [1:0]ddr_axi_awburst; + wire [3:0]ddr_axi_awcache; + wire [0:0]ddr_axi_awid; + wire [7:0]ddr_axi_awlen; + wire [0:0]ddr_axi_awlock; + wire [2:0]ddr_axi_awprot; + wire [3:0]ddr_axi_awqos; + wire ddr_axi_awready; + wire [2:0]ddr_axi_awsize; + wire ddr_axi_awvalid; + wire [0:0]ddr_axi_bid; + wire ddr_axi_bready; + wire [1:0]ddr_axi_bresp; + wire ddr_axi_bvalid; + wire [31:0]ddr_axi_rdata; + wire [0:0]ddr_axi_rid; + wire ddr_axi_rlast; + wire ddr_axi_rready; + wire [1:0]ddr_axi_rresp; + wire ddr_axi_rvalid; + wire [31:0]ddr_axi_wdata; + wire ddr_axi_wlast; + wire ddr_axi_wready; + wire [3:0]ddr_axi_wstrb; + wire ddr_axi_wvalid; + wire [2:0]ddr_ba; + wire ddr_cas_n; + wire [1:0]ddr_ck_n; + wire [1:0]ddr_ck_p; + wire [1:0]ddr_cke; + wire [1:0]ddr_cs_n; + wire [7:0]ddr_dm; + wire [63:0]ddr_dq; + wire [7:0]ddr_dqs_n; + wire [7:0]ddr_dqs_p; + wire [1:0]ddr_odt; + wire ddr_ras_n; + wire ddr_reset_n; + wire ddr_we_n; + wire init_calib_complete; + wire [0:0]pcie_clk_clk_n; + wire [0:0]pcie_clk_clk_p; + wire [7:0]pcie_mgt_rxn; + wire [7:0]pcie_mgt_rxp; + wire [7:0]pcie_mgt_txn; + wire [7:0]pcie_mgt_txp; + wire pcie_msi_enable; + wire pcie_user_lnk_up; + wire [0:0]pcie_usr_irq_req; + wire sys_clk; + wire sys_rst_n_0; + wire sys_rstn; + + pcie_ddr pcie_ddr_i + (.ddr_addr(ddr_addr), + .ddr_axi_araddr(ddr_axi_araddr), + .ddr_axi_arburst(ddr_axi_arburst), + .ddr_axi_arcache(ddr_axi_arcache), + .ddr_axi_arid(ddr_axi_arid), + .ddr_axi_arlen(ddr_axi_arlen), + .ddr_axi_arlock(ddr_axi_arlock), + .ddr_axi_arprot(ddr_axi_arprot), + .ddr_axi_arqos(ddr_axi_arqos), + .ddr_axi_arready(ddr_axi_arready), + .ddr_axi_arsize(ddr_axi_arsize), + .ddr_axi_arvalid(ddr_axi_arvalid), + .ddr_axi_awaddr(ddr_axi_awaddr), + .ddr_axi_awburst(ddr_axi_awburst), + .ddr_axi_awcache(ddr_axi_awcache), + .ddr_axi_awid(ddr_axi_awid), + .ddr_axi_awlen(ddr_axi_awlen), + .ddr_axi_awlock(ddr_axi_awlock), + .ddr_axi_awprot(ddr_axi_awprot), + .ddr_axi_awqos(ddr_axi_awqos), + .ddr_axi_awready(ddr_axi_awready), + .ddr_axi_awsize(ddr_axi_awsize), + .ddr_axi_awvalid(ddr_axi_awvalid), + .ddr_axi_bid(ddr_axi_bid), + .ddr_axi_bready(ddr_axi_bready), + .ddr_axi_bresp(ddr_axi_bresp), + .ddr_axi_bvalid(ddr_axi_bvalid), + .ddr_axi_rdata(ddr_axi_rdata), + .ddr_axi_rid(ddr_axi_rid), + .ddr_axi_rlast(ddr_axi_rlast), + .ddr_axi_rready(ddr_axi_rready), + .ddr_axi_rresp(ddr_axi_rresp), + .ddr_axi_rvalid(ddr_axi_rvalid), + .ddr_axi_wdata(ddr_axi_wdata), + .ddr_axi_wlast(ddr_axi_wlast), + .ddr_axi_wready(ddr_axi_wready), + .ddr_axi_wstrb(ddr_axi_wstrb), + .ddr_axi_wvalid(ddr_axi_wvalid), + .ddr_ba(ddr_ba), + .ddr_cas_n(ddr_cas_n), + .ddr_ck_n(ddr_ck_n), + .ddr_ck_p(ddr_ck_p), + .ddr_cke(ddr_cke), + .ddr_cs_n(ddr_cs_n), + .ddr_dm(ddr_dm), + .ddr_dq(ddr_dq), + .ddr_dqs_n(ddr_dqs_n), + .ddr_dqs_p(ddr_dqs_p), + .ddr_odt(ddr_odt), + .ddr_ras_n(ddr_ras_n), + .ddr_reset_n(ddr_reset_n), + .ddr_we_n(ddr_we_n), + .init_calib_complete(init_calib_complete), + .pcie_clk_clk_n(pcie_clk_clk_n), + .pcie_clk_clk_p(pcie_clk_clk_p), + .pcie_mgt_rxn(pcie_mgt_rxn), + .pcie_mgt_rxp(pcie_mgt_rxp), + .pcie_mgt_txn(pcie_mgt_txn), + .pcie_mgt_txp(pcie_mgt_txp), + .pcie_msi_enable(pcie_msi_enable), + .pcie_user_lnk_up(pcie_user_lnk_up), + .pcie_usr_irq_req(pcie_usr_irq_req), + .sys_clk(sys_clk), + .sys_rst_n_0(sys_rst_n_0), + .sys_rstn(sys_rstn)); +endmodule diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_1/pcie_ddr_auto_cc_1.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_1/pcie_ddr_auto_cc_1.xci new file mode 100644 index 0000000..fa39641 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_auto_cc_1/pcie_ddr_auto_cc_1.xci @@ -0,0 +1,237 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pcie_ddr_auto_cc_1 + + + M_AXI + M_AXI_ARESETN + pcie_ddr_mig_7series_0_0_ui_clk + 100000000 + 0 + 0 + 0 + ACTIVE_LOW + INTERCONNECT + 33 + 0 + 0 + 0 + pcie_ddr_mig_7series_0_0_ui_clk + 512 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 256 + 8 + 1 + 8 + 1 + 0 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + S_AXI + S_AXI_ARESETN + /clk_wiz_0_clk_out1 + 200000000 + 0 + 0.0 + 0 + ACTIVE_LOW + INTERCONNECT + 33 + 0 + 0 + 0 + /clk_wiz_0_clk_out1 + 512 + 200000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 256 + 8 + 1 + 8 + 1 + 0.0 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 33 + 1 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+ choice_list_22f447d7 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_42702293 + 16:1 + 15:1 + 14:1 + 13:1 + 12:1 + 11:1 + 10:1 + 9:1 + 8:1 + 7:1 + 6:1 + 5:1 + 4:1 + 3:1 + 2:1 + 1:2 + 1:3 + 1:4 + 1:5 + 1:6 + 1:7 + 1:8 + 1:9 + 1:10 + 1:11 + 1:12 + 1:13 + 1:14 + 1:15 + 1:16 + + + choice_list_7235ff92 + AXI4 + AXI3 + AXI4LITE + + + choice_pairs_37189c7b + 0 + 1 + + + choice_pairs_940700f2 + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_a4d18bae + 0 + 1 + 2 + + + choice_pairs_fe99fc86 + 0 + 1 + 2 + + + The AXI Data Width Converter IP provides the facility to increase or decrease the data width of WDATA and RDATA between an AXI4/AXI3/AXI4-Lite master and slave. + + + PROTOCOL + PROTOCOL + AXI4 + + + READ_WRITE_MODE + READ_WRITE Mode + READ_WRITE + + + ADDR_WIDTH + Address Width + 32 + + + PACKING_LEVEL + Packing Level + 1 + + + SI_DATA_WIDTH + SI Data Width + 32 + + + MI_DATA_WIDTH + MI Data Width + 512 + + + SI_ID_WIDTH + SI ID Width + 1 + + + MAX_SPLIT_BEATS + Max Burst Length When Downsizing + 256 + + + FIFO_MODE + Upsizer FIFO + 0 + + + ACLK_ASYNC + Is ACLK Asynchronous + 0 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 3 + + + ACLK_RATIO + SI to MI Clock Ratio + 1:2 + + + Component_Name + pcie_ddr_auto_us_1 + + + + + AXI Data Width Converter + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_0/pcie_ddr_axi_interconnect_0_0.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_1/pcie_ddr_axi_interconnect_0_1.xci similarity index 99% rename from ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_0/pcie_ddr_axi_interconnect_0_0.xci rename to ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_1/pcie_ddr_axi_interconnect_0_1.xci index 3b51bf7..6426c85 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_0/pcie_ddr_axi_interconnect_0_0.xci +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_1/pcie_ddr_axi_interconnect_0_1.xci @@ -6,10 +6,10 @@ 1.0 - pcie_ddr_axi_interconnect_0_0 + pcie_ddr_axi_interconnect_0_1 - pcie_ddr_axi_interconnect_0_0 + pcie_ddr_axi_interconnect_0_1 0 0 0 diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_0/pcie_ddr_axi_interconnect_0_0.xml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_1/pcie_ddr_axi_interconnect_0_1.xml similarity index 99% rename from ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_0/pcie_ddr_axi_interconnect_0_0.xml rename to ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_1/pcie_ddr_axi_interconnect_0_1.xml index c1018d6..fc109bd 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_0/pcie_ddr_axi_interconnect_0_0.xml +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_axi_interconnect_0_1/pcie_ddr_axi_interconnect_0_1.xml @@ -2,7 +2,7 @@ xilinx.com customized_ip - pcie_ddr_axi_interconnect_0_0 + pcie_ddr_axi_interconnect_0_1 1.0 @@ -1622,7 +1622,7 @@ Component_Name - pcie_ddr_axi_interconnect_0_0 + pcie_ddr_axi_interconnect_0_1 diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xci index 24ae903..bd4d715 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xci +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xci @@ -19,13 +19,13 @@ 100000000 - + pcie_ddr_clk_in1_0 200000000 0 0.000 - pcie_ddr_clk_wiz_0_0_clk_out1 + /clk_wiz_0_clk_out1 200000000 0 0.0 @@ -672,14 +672,14 @@ - + - - - + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xml index 4c9687d..dc6081a 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xml +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xml @@ -1031,7 +1031,7 @@ CLK_DOMAIN - + pcie_ddr_clk_in1_0 none @@ -1107,7 +1107,7 @@ CLK_DOMAIN - pcie_ddr_clk_wiz_0_0_clk_out1 + /clk_wiz_0_clk_out1 none @@ -4509,14 +4509,14 @@ - + - - - + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_a.prj b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_a.prj index 9058bfc..19bf3f9 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_a.prj +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_a.prj @@ -1,4 +1,4 @@ - +? @@ -219,8 +219,8 @@ RD_PRI_REG 33 512 - 4 - 0 + 1 + 1 diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_b.prj b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_b.prj new file mode 100644 index 0000000..19bf3f9 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_b.prj @@ -0,0 +1,228 @@ +? + + + + + + + pcie_ddr_mig_7series_0_0 + + 1 + + 1 + + OFF + + 1024 + + ON + + Enabled + + xc7k325t-ffg900/-2 + + 4.2 + + No Buffer + + Use System Clock + + ACTIVE LOW + + FALSE + + 0 + + 50 Ohms + + 0 + + + DDR3_SDRAM/SODIMMs/MT16JTF1G64HZ-1G4 + 2500 + 1.8V + 4:1 + 200 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 64 + 2 + 1 + Disabled + Normal + 4 + FALSE + + 16 + 10 + 3 + 1.5V + 8589934592 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 33 + 512 + 1 + 1 + + + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.veo b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.veo index 8ad586d..08b4222 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.veo +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.veo @@ -98,7 +98,7 @@ .app_ref_ack (app_ref_ack), // output app_ref_ack .app_zq_ack (app_zq_ack), // output app_zq_ack // Slave Interface Write Address Ports - .s_axi_awid (s_axi_awid), // input [3:0] s_axi_awid + .s_axi_awid (s_axi_awid), // input [0:0] s_axi_awid .s_axi_awaddr (s_axi_awaddr), // input [32:0] s_axi_awaddr .s_axi_awlen (s_axi_awlen), // input [7:0] s_axi_awlen .s_axi_awsize (s_axi_awsize), // input [2:0] s_axi_awsize @@ -116,12 +116,12 @@ .s_axi_wvalid (s_axi_wvalid), // input s_axi_wvalid .s_axi_wready (s_axi_wready), // output s_axi_wready // Slave Interface Write Response Ports - .s_axi_bid (s_axi_bid), // output [3:0] s_axi_bid + .s_axi_bid (s_axi_bid), // output [0:0] s_axi_bid .s_axi_bresp (s_axi_bresp), // output [1:0] s_axi_bresp .s_axi_bvalid (s_axi_bvalid), // output s_axi_bvalid .s_axi_bready (s_axi_bready), // input s_axi_bready // Slave Interface Read Address Ports - .s_axi_arid (s_axi_arid), // input [3:0] s_axi_arid + .s_axi_arid (s_axi_arid), // input [0:0] s_axi_arid .s_axi_araddr (s_axi_araddr), // input [32:0] s_axi_araddr .s_axi_arlen (s_axi_arlen), // input [7:0] s_axi_arlen .s_axi_arsize (s_axi_arsize), // input [2:0] s_axi_arsize @@ -133,7 +133,7 @@ .s_axi_arvalid (s_axi_arvalid), // input s_axi_arvalid .s_axi_arready (s_axi_arready), // output s_axi_arready // Slave Interface Read Data Ports - .s_axi_rid (s_axi_rid), // output [3:0] s_axi_rid + .s_axi_rid (s_axi_rid), // output [0:0] s_axi_rid .s_axi_rdata (s_axi_rdata), // output [511:0] s_axi_rdata .s_axi_rresp (s_axi_rresp), // output [1:0] s_axi_rresp .s_axi_rlast (s_axi_rlast), // output s_axi_rlast diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xci index 1180ef9..44c975d 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xci +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xci @@ -1084,19 +1084,20 @@ 0 0 0 + ACTIVE_LOW false 100000000 - - 100000000 + /clk_wiz_0_clk_out1 + 200000000 0 - 0.000 + 0.0 33 0 0 0 - + pcie_ddr_mig_7series_0_0_ui_clk 512 1 1 @@ -1107,14 +1108,14 @@ 0 1 1 - 4 + 1 0 256 8 1 8 1 - 0.000 + 0 AXI4 READ_WRITE 0 @@ -2175,7 +2176,7 @@ 4 1048576 512 - 4 + 1 8589934592 8 3 @@ -2303,7 +2304,7 @@ pcie_ddr_mig_7series_0_0 Custom Custom - mig_a.prj + mig_b.prj kintex7 @@ -2346,28 +2347,29 @@ + - - - + + + - + - - - + + + - - - + + + @@ -2377,11 +2379,11 @@ - + - + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xml index 14a5247..1b7be16 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xml +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xml @@ -24,7 +24,7 @@ POLARITY - ACTIVE_LOW + ACTIVE_LOW BOARD.ASSOCIATED_PARAM @@ -2173,7 +2173,7 @@ ID_WIDTH - 4 + 1 none @@ -2362,7 +2362,7 @@ PHASE - 0.000 + 0 none @@ -2371,7 +2371,7 @@ CLK_DOMAIN - + pcie_ddr_mig_7series_0_0_ui_clk none @@ -2503,7 +2503,7 @@ FREQ_HZ - 100000000 + 200000000 none @@ -2512,7 +2512,7 @@ PHASE - 0.000 + 0.0 none @@ -2521,7 +2521,7 @@ CLK_DOMAIN - + /clk_wiz_0_clk_out1 none @@ -26762,7 +26762,7 @@ in - 3 + 0 0 @@ -27140,7 +27140,7 @@ out - 3 + 0 0 @@ -27205,7 +27205,7 @@ in - 3 + 0 0 @@ -27480,7 +27480,7 @@ out - 3 + 0 0 @@ -103272,7 +103272,7 @@ C_S_AXI_ID_WIDTH AXI ID Width AXI ID Width - 4 + 1 C_S_AXI_DATA_WIDTH @@ -109716,7 +109716,7 @@ XML_INPUT_FILE XML_INPUT_FILE - mig_a.prj + mig_b.prj RESET_BOARD_INTERFACE @@ -109767,12 +109767,12 @@ - + - - - + + + @@ -109780,17 +109780,17 @@ - + - - - + + + - - - + + + @@ -109800,11 +109800,11 @@ - + - + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/datasheet.txt b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/datasheet.txt index 728b127..63ca16f 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/datasheet.txt +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/datasheet.txt @@ -72,7 +72,7 @@ AXI Parameters : Narrow Burst Support : 0 - ID Width : 4 + ID Width : 1 diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/par/example_top.xdc b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/par/example_top.xdc index 0721e78..a9fb14d 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/par/example_top.xdc +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/par/example_top.xdc @@ -1,7 +1,7 @@ ################################################################################################## ## ## Xilinx, Inc. 2010 www.xilinx.com -## Mon Mar 17 17:32:15 2025 +## Tue Mar 18 13:45:42 2025 ## Generated by MIG Version 4.2 ## diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/rtl/example_top.v b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/rtl/example_top.v index e2334a3..814546d 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/rtl/example_top.v +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/rtl/example_top.v @@ -191,7 +191,7 @@ module example_top # //*************************************************************************** // AXI4 Shim parameters //*************************************************************************** - parameter C_S_AXI_ID_WIDTH = 4, + parameter C_S_AXI_ID_WIDTH = 1, // Width of all master and slave ID signals. // # = >= 1. parameter C_S_AXI_ADDR_WIDTH = 33, diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/sim/sim_tb_top.v b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/sim/sim_tb_top.v index 0567c06..cebfafe 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/sim/sim_tb_top.v +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/example_design/sim/sim_tb_top.v @@ -174,7 +174,7 @@ module sim_tb_top; //*************************************************************************** // AXI4 Shim parameters //*************************************************************************** - parameter C_S_AXI_ID_WIDTH = 4; + parameter C_S_AXI_ID_WIDTH = 1; // Width of all master and slave ID signals. // # = >= 1. parameter C_S_AXI_ADDR_WIDTH = 33; diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/mig.prj b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/mig.prj index 62e9441..5c0a524 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/mig.prj +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/mig.prj @@ -217,7 +217,7 @@ RD_PRI_REG 33 512 - 4 + 1 0 diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/constraints/pcie_ddr_mig_7series_0_0.xdc b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/constraints/pcie_ddr_mig_7series_0_0.xdc index 7fcb94f..cae717d 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/constraints/pcie_ddr_mig_7series_0_0.xdc +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/constraints/pcie_ddr_mig_7series_0_0.xdc @@ -1,7 +1,7 @@ ################################################################################################## ## ## Xilinx, Inc. 2010 www.xilinx.com -## Mon Mar 17 17:32:14 2025 +## Tue Mar 18 13:45:42 2025 ## Generated by MIG Version 4.2 ## diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/constraints/pcie_ddr_mig_7series_0_0_ooc.xdc b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/constraints/pcie_ddr_mig_7series_0_0_ooc.xdc index fdd1605..4d666e5 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/constraints/pcie_ddr_mig_7series_0_0_ooc.xdc +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/constraints/pcie_ddr_mig_7series_0_0_ooc.xdc @@ -9,7 +9,7 @@ ################################################################################################## ## ## Xilinx, Inc. 2010 www.xilinx.com -## Mon Mar 17 17:32:14 2025 +## Tue Mar 18 13:45:42 2025 ## Generated by MIG Version 4.2 ## diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0.v b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0.v index 078fe23..bc6198b 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0.v +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0.v @@ -97,7 +97,7 @@ module pcie_ddr_mig_7series_0_0 ( output app_ref_ack, output app_zq_ack, // Slave Interface Write Address Ports - input [3:0] s_axi_awid, + input [0:0] s_axi_awid, input [32:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, @@ -116,11 +116,11 @@ module pcie_ddr_mig_7series_0_0 ( output s_axi_wready, // Slave Interface Write Response Ports input s_axi_bready, - output [3:0] s_axi_bid, + output [0:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, // Slave Interface Read Address Ports - input [3:0] s_axi_arid, + input [0:0] s_axi_arid, input [32:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, @@ -133,7 +133,7 @@ module pcie_ddr_mig_7series_0_0 ( output s_axi_arready, // Slave Interface Read Data Ports input s_axi_rready, - output [3:0] s_axi_rid, + output [0:0] s_axi_rid, output [511:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig.v b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig.v index 6f114f2..d4de955 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig.v +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig.v @@ -476,7 +476,7 @@ module pcie_ddr_mig_7series_0_0_mig # // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection - parameter C_S_AXI_ID_WIDTH = 4, + parameter C_S_AXI_ID_WIDTH = 1, // Width of all master and slave ID signals. // # = >= 1. parameter C_S_AXI_MEM_SIZE = "8589934592", diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig_sim.v b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig_sim.v index 878f4eb..937b955 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig_sim.v +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig_sim.v @@ -476,7 +476,7 @@ module pcie_ddr_mig_7series_0_0_mig # // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection - parameter C_S_AXI_ID_WIDTH = 4, + parameter C_S_AXI_ID_WIDTH = 1, // Width of all master and slave ID signals. // # = >= 1. parameter C_S_AXI_MEM_SIZE = "8589934592", diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/xil_txt.in b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/xil_txt.in index 8a6f1d1..9c94b31 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/xil_txt.in +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/xil_txt.in @@ -9,14 +9,14 @@ SET_PREFERENCE package ffg900 SET_PREFERENCE verilogsim true SET_PREFERENCE vhdlsim false SET_PREFERENCE designentry Verilog -SET_PREFERENCE outputdirectory d:/project/Vivado/project/AX7325/ddr_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/_tmp/ -SET_PREFERENCE subworkingdirectory d:/project/Vivado/project/AX7325/ddr_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/_tmp/ +SET_PREFERENCE outputdirectory d:/Project/Vivado/AX7325/ddr3_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/_tmp/ +SET_PREFERENCE subworkingdirectory d:/Project/Vivado/AX7325/ddr3_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/_tmp/ SET_PREFERENCE flowvendor Other SET_PREFERENCE tool vivado SET_PARAMETER component_name pcie_ddr_mig_7series_0_0 SET_PREFERENCE compnamestatus 1 SET_PARAMETER component_name pcie_ddr_mig_7series_0_0 -SET_PARAMETER xml_input_file D:/project/Vivado/project/AX7325/ddr_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_a.prj +SET_PARAMETER xml_input_file D:/Project/Vivado/AX7325/ddr3_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_b.prj SET_PARAMETER data_dir_path c:/Xilinx/Vivado/2019.2/data/ip/xilinx/mig_7series_v4_2 SET_CORE_NAME Memory Interface Generator (MIG 7 Series) SET_CORE_VERSION 4.2 diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_clk_wiz_0_200M_0/pcie_ddr_rst_clk_wiz_0_200M_0.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_clk_wiz_0_200M_0/pcie_ddr_rst_clk_wiz_0_200M_0.xci new file mode 100644 index 0000000..33ec9b9 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_clk_wiz_0_200M_0/pcie_ddr_rst_clk_wiz_0_200M_0.xci @@ -0,0 +1,85 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pcie_ddr_rst_clk_wiz_0_200M_0 + + + 0 + ACTIVE_LOW + 0 + + /clk_wiz_0_clk_out1 + 200000000 + 0 + 0.0 + 0 + 0 + ACTIVE_LOW + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 4 + kintex7 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 4 + 1 + 1 + 1 + 1 + pcie_ddr_rst_clk_wiz_0_200M_0 + Custom + false + kintex7 + + + xc7k325t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Integrator + 13 + TRUE + . + + ../../ipshared + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_clk_wiz_0_200M_0/pcie_ddr_rst_clk_wiz_0_200M_0.xml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_clk_wiz_0_200M_0/pcie_ddr_rst_clk_wiz_0_200M_0.xml new file mode 100644 index 0000000..d7d8b11 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_clk_wiz_0_200M_0/pcie_ddr_rst_clk_wiz_0_200M_0.xml @@ -0,0 +1,680 @@ + + + xilinx.com + customized_ip + pcie_ddr_rst_clk_wiz_0_200M_0 + 1.0 + + + clock + Clock + + + + + + + CLK + + + slowest_sync_clk + + + + + + ASSOCIATED_RESET + mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset + + + FREQ_HZ + Slowest Sync clock frequency + Slowest Synchronous clock frequency + 200000000 + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + ext_reset + Ext_Reset + + + + + + + RST + + + ext_reset_in + + + + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + required + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + aux_reset + aux_reset + + + + + + + RST + + + aux_reset_in + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + dbg_reset + DBG_Reset + + + + + + + RST + + + mb_debug_sys_rst + + + + + + POLARITY + ACTIVE_HIGH + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + mb_rst + MB_rst + + + + + + + RST + + + mb_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PROCESSOR + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + bus_struct_reset + bus_struct_reset + + + + + + + RST + + + bus_struct_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + interconnect_low_rst + interconnect_low_rst + + + + + + + RST + + + interconnect_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + peripheral_high_rst + peripheral_high_rst + + + + + + + RST + + + peripheral_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + peripheral_low_rst + peripheral_low_rst + + + + + + + RST + + + peripheral_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + slowest_sync_clk + + in + + + std_logic + dummy_view + + + + + + ext_reset_in + + in + + + std_logic + dummy_view + + + + + + aux_reset_in + + in + + + std_logic + dummy_view + + + + 1 + + + + + mb_debug_sys_rst + + in + + + std_logic + dummy_view + + + + 0 + + + + + dcm_locked + + in + + + std_logic + dummy_view + + + + 0x1 + + + + + mb_reset + + out + + + std_logic + dummy_view + + + + 0x0 + + + + + bus_struct_reset + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + peripheral_reset + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 0 + + + + + interconnect_aresetn + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 1 + + + + + peripheral_aresetn + + out + + 0 + 0 + + + + std_logic_vector + dummy_view + + + + 1 + + + + + + + C_FAMILY + kintex7 + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RESET_HIGH + Ext Reset High + 0 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + + + + choice_list_ac75ef1e + Custom + + + Processor Reset System + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_EXT_RESET_HIGH + Ext Reset High + 0 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + Component_Name + pcie_ddr_rst_clk_wiz_0_200M_0 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + RESET_BOARD_INTERFACE + Custom + + + + + Processor System Reset + 13 + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_2/pcie_ddr_rst_mig_7series_0_100M_2.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_4/pcie_ddr_rst_mig_7series_0_100M_4.xci similarity index 89% rename from ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_2/pcie_ddr_rst_mig_7series_0_100M_2.xci rename to ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_4/pcie_ddr_rst_mig_7series_0_100M_4.xci index 8a8cd76..f528f40 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_2/pcie_ddr_rst_mig_7series_0_100M_2.xci +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_4/pcie_ddr_rst_mig_7series_0_100M_4.xci @@ -6,25 +6,25 @@ 1.0 - pcie_ddr_rst_mig_7series_0_100M_2 + pcie_ddr_rst_mig_7series_0_100M_4 0 ACTIVE_LOW 0 - + pcie_ddr_mig_7series_0_0_ui_clk 100000000 0 - 0.000 + 0 0 0 - ACTIVE_LOW + ACTIVE_HIGH 0 0 0 0 - 1 + 0 4 1 4 @@ -33,7 +33,7 @@ 1 1 1 - 1 + 0 4 1 4 @@ -41,7 +41,7 @@ 1 1 1 - pcie_ddr_rst_mig_7series_0_100M_2 + pcie_ddr_rst_mig_7series_0_100M_4 Custom false kintex7 @@ -71,12 +71,12 @@ - + - - - - + + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_2/pcie_ddr_rst_mig_7series_0_100M_2.xml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_4/pcie_ddr_rst_mig_7series_0_100M_4.xml similarity index 97% rename from ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_2/pcie_ddr_rst_mig_7series_0_100M_2.xml rename to ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_4/pcie_ddr_rst_mig_7series_0_100M_4.xml index 3d60278..19df551 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_2/pcie_ddr_rst_mig_7series_0_100M_2.xml +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_rst_mig_7series_0_100M_4/pcie_ddr_rst_mig_7series_0_100M_4.xml @@ -2,7 +2,7 @@ xilinx.com customized_ip - pcie_ddr_rst_mig_7series_0_100M_2 + pcie_ddr_rst_mig_7series_0_100M_4 1.0 @@ -34,7 +34,7 @@ PHASE - 0.000 + 0 none @@ -43,7 +43,7 @@ CLK_DOMAIN - + pcie_ddr_mig_7series_0_0_ui_clk none @@ -100,7 +100,7 @@ POLARITY - ACTIVE_LOW + ACTIVE_HIGH none @@ -554,7 +554,7 @@ C_AUX_RESET_HIGH Aux Reset High - 1 + 0 C_NUM_BUS_RST @@ -609,7 +609,7 @@ C_AUX_RESET_HIGH Aux Reset High - 1 + 0 C_EXT_RESET_HIGH @@ -628,7 +628,7 @@ Component_Name - pcie_ddr_rst_mig_7series_0_100M_2 + pcie_ddr_rst_mig_7series_0_100M_4 USE_BOARD_FLOW @@ -650,12 +650,12 @@ - + - + - + @@ -664,8 +664,8 @@ - - + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_s01_mmu_1/pcie_ddr_s01_mmu_1.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_s01_mmu_1/pcie_ddr_s01_mmu_1.xci new file mode 100644 index 0000000..2807b4f --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_s01_mmu_1/pcie_ddr_s01_mmu_1.xci @@ -0,0 +1,998 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pcie_ddr_s01_mmu_1 + + + S_AXI:M_AXI + ARESETN + pcie_ddr_clk_in1_0 + 200000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + pcie_ddr_clk_in1_0 + 32 + 200000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0 + 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true + + + + + + m_axi_wready + + in + + + wire + dummy_view + + + + 0x0 + + + + + + true + + + + + + m_axi_bid + + in + + 0 + 0 + + + + wire + dummy_view + + + + 0x0 + + + + + + true + + + + + + m_axi_bresp + + in + + 1 + 0 + + + + wire + dummy_view + + + + 0x0 + + + + + + true + + + + + + m_axi_buser + + in + + 0 + 0 + + + + wire + dummy_view + + + + 0x0 + + + + + + false + + + + + + m_axi_bvalid + + in + + + wire + dummy_view + + + + 0x0 + + + + + + true + + + + + + m_axi_bready + + out + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arid + + out + + 0 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_araddr + + out + + 31 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arlen + + out + + 7 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arsize + + out + + 2 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arburst + + out + + 1 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arlock + + out + + 0 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arcache + + out + + 3 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arprot + + out + + 2 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arqos + + out + + 3 + 0 + + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_aruser + + out + + 0 + 0 + + + + wire + dummy_view + + + + + + + false + + + + + + m_axi_arvalid + + out + + + wire + dummy_view + + + + + + + true + + + + + + m_axi_arready + + in + + + wire + dummy_view + + + + 0x0 + + + + + + true + + + + + + m_axi_rid + + in + + 0 + 0 + + + + wire + dummy_view + + + + 0x0 + + + + + + true + + + + + + m_axi_rdata + + in + + 31 + 0 + + + + wire + dummy_view + + + + 0x00000000 + + + + + + true + + + + + + m_axi_rresp + + in + + 1 + 0 + + + + wire + dummy_view + + + + 0x0 + + + + + + true + + + + + + m_axi_rlast + + in + + + wire + dummy_view + + + + 0x1 + + + + + + true + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + wire + dummy_view + + + + 0x0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + wire + dummy_view + + + + 0x0 + + + + + + true + + + + + + m_axi_rready + + out + + + wire + dummy_view + + + + + + + true + + + + + + + + C_FAMILY + kintex7 + + + C_AXI_PROTOCOL + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_S_AXI_ADDR_WIDTH + 32 + + + C_M_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 32 + + + C_AXI_SUPPORTS_USER_SIGNALS + 0 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_NUM_RANGES + 1 + + + C_BASE_ADDR + 0x0000000000000000 + + + C_RANGE_SIZE + 0x00000020 + + + C_USES_DEST + 0 + + + C_DEST_WIDTH + 1 + + + C_DEST + 0x0000000000000000 + + + C_PREFIX_WIDTH + 1 + + + C_PREFIX + 0x0000000000000000 + + + C_S_AXI_SUPPORTS_WRITE + 1 + + + C_S_AXI_SUPPORTS_READ + 1 + + + C_M_AXI_SUPPORTS_WRITE + 0x0000000000000001 + + + C_M_AXI_SUPPORTS_READ + 0x0000000000000001 + + + + + + choice_list_0e867c35 + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_7235ff92 + AXI4 + AXI3 + AXI4LITE + + + The AXI MMU IP provides addres range decoding and remapping services for AXI Interconnect. + + + NUM_RANGES + Number of Address Ranges + 1 + + + SI_ADDR_WIDTH + SI Address Width + 32 + + + MI_ADDR_WIDTH + MI Address Width + 32 + + + PROTOCOL + Protocol + AXI4 + + + READ_WRITE_MODE + READ_WRITE Mode + READ_WRITE + + + DATA_WIDTH + Data Width + 32 + + + ID_WIDTH + ID Width + 1 + + + AWUSER_WIDTH + AWUSER Signal Width + 0 + + + ARUSER_WIDTH + ARUSER Signal Width + 0 + + + WUSER_WIDTH + WUSER Signal Width + 0 + + + RUSER_WIDTH + RUSER Signal Width + 0 + + + BUSER_WIDTH + BUSER Signal Width + 0 + + + D000_BASE_ADDR + Range 0 base + 0x0000000000000000 + + + D000_ADDR_WIDTH + Range 0 size + 32 + + + D000_READ_WRITE_MODE + Range 0 access mode + READ_WRITE + + + D001_BASE_ADDR + Range 1 base + 0x0000000000010000 + + + D001_ADDR_WIDTH + Range 1 size + 16 + + + D001_READ_WRITE_MODE + Range 1 access mode + READ_WRITE + + + D002_BASE_ADDR + Range 2 base + 0x0000000000020000 + + + D002_ADDR_WIDTH + Range 2 size + 16 + + + D002_READ_WRITE_MODE + Range 2 access mode + READ_WRITE + + + D003_BASE_ADDR + Range 3 base + 0x0000000000030000 + + + D003_ADDR_WIDTH + Range 3 size + 16 + + + D003_READ_WRITE_MODE + Range 3 access mode + READ_WRITE + + + D004_BASE_ADDR + Range 4 base + 0x0000000000040000 + + + D004_ADDR_WIDTH + Range 4 size + 16 + + + D004_READ_WRITE_MODE + Range 4 access mode + READ_WRITE + + + D005_BASE_ADDR + Range 5 base + 0x0000000000050000 + + + D005_ADDR_WIDTH + Range 5 size + 16 + + + D005_READ_WRITE_MODE + Range 5 access mode + READ_WRITE + + + D006_BASE_ADDR + Range 6 base + 0x0000000000060000 + + + D006_ADDR_WIDTH + Range 6 size + 16 + + + D006_READ_WRITE_MODE + Range 6 access mode + READ_WRITE + + + D007_BASE_ADDR + Range 7 base + 0x0000000000070000 + + + D007_ADDR_WIDTH + Range 7 size + 16 + + + D007_READ_WRITE_MODE + Range 7 access mode + READ_WRITE + + + D008_BASE_ADDR + Range 8 base + 0x0000000000080000 + + + D008_ADDR_WIDTH + Range 8 size + 16 + + + D008_READ_WRITE_MODE + Range 8 access mode + READ_WRITE + + + D009_BASE_ADDR + Range 9 base + 0x0000000000090000 + + + D009_ADDR_WIDTH + Range 9 size + 16 + + + D009_READ_WRITE_MODE + Range 9 access mode + READ_WRITE + + + D010_BASE_ADDR + Range 10 base + 0x00000000000a0000 + + + D010_ADDR_WIDTH + Range 10 size + 16 + + + D010_READ_WRITE_MODE + Range 10 access mode + READ_WRITE + + + D011_BASE_ADDR + Range 11 base + 0x00000000000b0000 + + + D011_ADDR_WIDTH + Range 11 size + 16 + + + D011_READ_WRITE_MODE + Range 11 access mode + READ_WRITE + + + D012_BASE_ADDR + Range 12 base + 0x00000000000c0000 + + + D012_ADDR_WIDTH + Range 12 size + 16 + + + D012_READ_WRITE_MODE + Range 12 access mode + READ_WRITE + + + D013_BASE_ADDR + Range 13 base + 0x00000000000d0000 + + + D013_ADDR_WIDTH + Range 13 size + 16 + + + D013_READ_WRITE_MODE + Range 13 access mode + READ_WRITE + + + D014_BASE_ADDR + Range 14 base + 0x00000000000e0000 + + + D014_ADDR_WIDTH + Range 14 size + 16 + + + D014_READ_WRITE_MODE + Range 14 access mode + READ_WRITE + + + D015_BASE_ADDR + Range 15 base + 0x00000000000f0000 + + + D015_ADDR_WIDTH + Range 15 size + 16 + + + D015_READ_WRITE_MODE + Range 15 access mode + READ_WRITE + + + D016_BASE_ADDR + Range 16 base + 0x0000000000100000 + + + D016_ADDR_WIDTH + Range 16 size + 16 + + + D016_READ_WRITE_MODE + Range 16 access mode + READ_WRITE + + + D017_BASE_ADDR + Range 17 base + 0x0000000000110000 + + + D017_ADDR_WIDTH + Range 17 size + 16 + + + D017_READ_WRITE_MODE + Range 17 access mode + READ_WRITE + + + D018_BASE_ADDR + Range 18 base + 0x0000000000120000 + + + D018_ADDR_WIDTH + Range 18 size + 16 + + + D018_READ_WRITE_MODE + Range 18 access mode + READ_WRITE + + + D019_BASE_ADDR + Range 19 base + 0x0000000000130000 + + + D019_ADDR_WIDTH + Range 19 size + 16 + + + D019_READ_WRITE_MODE + Range 19 access mode + READ_WRITE + + + D020_BASE_ADDR + Range 20 base + 0x0000000000140000 + + + D020_ADDR_WIDTH + Range 20 size + 16 + + + D020_READ_WRITE_MODE + Range 20 access mode + READ_WRITE + + + D021_BASE_ADDR + Range 21 base + 0x0000000000150000 + + + D021_ADDR_WIDTH + Range 21 size + 16 + + + D021_READ_WRITE_MODE + Range 21 access mode + READ_WRITE + + + D022_BASE_ADDR + Range 22 base + 0x0000000000160000 + + + D022_ADDR_WIDTH + Range 22 size + 16 + + + D022_READ_WRITE_MODE + Range 22 access mode + READ_WRITE + + + D023_BASE_ADDR + Range 23 base + 0x0000000000170000 + + + D023_ADDR_WIDTH + Range 23 size + 16 + + + D023_READ_WRITE_MODE + Range 23 access mode + READ_WRITE + + + D024_BASE_ADDR + Range 24 base + 0x0000000000180000 + + + D024_ADDR_WIDTH + Range 24 size + 16 + + + D024_READ_WRITE_MODE + Range 24 access mode + READ_WRITE + + + D025_BASE_ADDR + Range 25 base + 0x0000000000190000 + + + D025_ADDR_WIDTH + Range 25 size + 16 + + + D025_READ_WRITE_MODE + Range 25 access mode + READ_WRITE + + + D026_BASE_ADDR + Range 26 base + 0x00000000001a0000 + + + D026_ADDR_WIDTH + Range 26 size + 16 + + + D026_READ_WRITE_MODE + Range 26 access mode + READ_WRITE + + + D027_BASE_ADDR + Range 27 base + 0x00000000001b0000 + + + D027_ADDR_WIDTH + Range 27 size + 16 + + + D027_READ_WRITE_MODE + Range 27 access mode + READ_WRITE + + + D028_BASE_ADDR + Range 28 base + 0x00000000001c0000 + + + D028_ADDR_WIDTH + Range 28 size + 16 + + + D028_READ_WRITE_MODE + Range 28 access mode + READ_WRITE + + + D029_BASE_ADDR + Range 29 base + 0x00000000001d0000 + + + D029_ADDR_WIDTH + Range 29 size + 16 + + + D029_READ_WRITE_MODE + Range 29 access mode + READ_WRITE + + + D030_BASE_ADDR + Range 30 base + 0x00000000001e0000 + + + D030_ADDR_WIDTH + Range 30 size + 16 + + + D030_READ_WRITE_MODE + Range 30 access mode + READ_WRITE + + + D031_BASE_ADDR + Range 31 base + 0x00000000001f0000 + + + D031_ADDR_WIDTH + Range 31 size + 16 + + + D031_READ_WRITE_MODE + Range 31 access mode + READ_WRITE + + + D032_BASE_ADDR + Range 32 base + 0x0000000000200000 + + + D032_ADDR_WIDTH + Range 32 size + 16 + + + D032_READ_WRITE_MODE + Range 32 access mode + READ_WRITE + + + D033_BASE_ADDR + Range 33 base + 0x0000000000210000 + + + D033_ADDR_WIDTH + Range 33 size + 16 + + + D033_READ_WRITE_MODE + Range 33 access mode + READ_WRITE + + + D034_BASE_ADDR + Range 34 base + 0x0000000000220000 + + + D034_ADDR_WIDTH + Range 34 size + 16 + + + D034_READ_WRITE_MODE + Range 34 access mode + READ_WRITE + + + D035_BASE_ADDR + Range 35 base + 0x0000000000230000 + + + D035_ADDR_WIDTH + Range 35 size + 16 + + + D035_READ_WRITE_MODE + Range 35 access mode + READ_WRITE + + + D036_BASE_ADDR + Range 36 base + 0x0000000000240000 + + + D036_ADDR_WIDTH + Range 36 size + 16 + + + D036_READ_WRITE_MODE + Range 36 access mode + READ_WRITE + + + D037_BASE_ADDR + Range 37 base + 0x0000000000250000 + + + D037_ADDR_WIDTH + Range 37 size + 16 + + + D037_READ_WRITE_MODE + Range 37 access mode + READ_WRITE + + + D038_BASE_ADDR + Range 38 base + 0x0000000000260000 + + + D038_ADDR_WIDTH + Range 38 size + 16 + + + D038_READ_WRITE_MODE + Range 38 access mode + READ_WRITE + + + D039_BASE_ADDR + Range 39 base + 0x0000000000270000 + + + D039_ADDR_WIDTH + Range 39 size + 16 + + + D039_READ_WRITE_MODE + Range 39 access mode + READ_WRITE + + + D040_BASE_ADDR + Range 40 base + 0x0000000000280000 + + + D040_ADDR_WIDTH + Range 40 size + 16 + + + D040_READ_WRITE_MODE + Range 40 access mode + READ_WRITE + + + D041_BASE_ADDR + Range 41 base + 0x0000000000290000 + + + D041_ADDR_WIDTH + Range 41 size + 16 + + + D041_READ_WRITE_MODE + Range 41 access mode + READ_WRITE + + + D042_BASE_ADDR + Range 42 base + 0x00000000002a0000 + + + D042_ADDR_WIDTH + Range 42 size + 16 + + + D042_READ_WRITE_MODE + Range 42 access mode + READ_WRITE + + + D043_BASE_ADDR + Range 43 base + 0x00000000002b0000 + + + D043_ADDR_WIDTH + Range 43 size + 16 + + + D043_READ_WRITE_MODE + Range 43 access mode + READ_WRITE + + + D044_BASE_ADDR + Range 44 base + 0x00000000002c0000 + + + D044_ADDR_WIDTH + Range 44 size + 16 + + + D044_READ_WRITE_MODE + Range 44 access mode + READ_WRITE + + + D045_BASE_ADDR + Range 45 base + 0x00000000002d0000 + + + D045_ADDR_WIDTH + Range 45 size + 16 + + + D045_READ_WRITE_MODE + Range 45 access mode + READ_WRITE + + + D046_BASE_ADDR + Range 46 base + 0x00000000002e0000 + + + D046_ADDR_WIDTH + Range 46 size + 16 + + + D046_READ_WRITE_MODE + Range 46 access mode + READ_WRITE + + + D047_BASE_ADDR + Range 47 base + 0x00000000002f0000 + + + D047_ADDR_WIDTH + Range 47 size + 16 + + + D047_READ_WRITE_MODE + Range 47 access mode + READ_WRITE + + + D048_BASE_ADDR + Range 48 base + 0x0000000000300000 + + + D048_ADDR_WIDTH + Range 48 size + 16 + + + D048_READ_WRITE_MODE + Range 48 access mode + READ_WRITE + + + D049_BASE_ADDR + Range 49 base + 0x0000000000310000 + + + D049_ADDR_WIDTH + Range 49 size + 16 + + + D049_READ_WRITE_MODE + Range 49 access mode + READ_WRITE + + + D050_BASE_ADDR + Range 50 base + 0x0000000000320000 + + + D050_ADDR_WIDTH + Range 50 size + 16 + + + D050_READ_WRITE_MODE + Range 50 access mode + READ_WRITE + + + D051_BASE_ADDR + Range 51 base + 0x0000000000330000 + + + D051_ADDR_WIDTH + Range 51 size + 16 + + + D051_READ_WRITE_MODE + Range 51 access mode + READ_WRITE + + + D052_BASE_ADDR + Range 52 base + 0x0000000000340000 + + + D052_ADDR_WIDTH + Range 52 size + 16 + + + D052_READ_WRITE_MODE + Range 52 access mode + READ_WRITE + + + D053_BASE_ADDR + Range 53 base + 0x0000000000350000 + + + D053_ADDR_WIDTH + Range 53 size + 16 + + + D053_READ_WRITE_MODE + Range 53 access mode + READ_WRITE + + + D054_BASE_ADDR + Range 54 base + 0x0000000000360000 + + + D054_ADDR_WIDTH + Range 54 size + 16 + + + D054_READ_WRITE_MODE + Range 54 access mode + READ_WRITE + + + D055_BASE_ADDR + Range 55 base + 0x0000000000370000 + + + D055_ADDR_WIDTH + Range 55 size + 16 + + + D055_READ_WRITE_MODE + Range 55 access mode + READ_WRITE + + + D056_BASE_ADDR + Range 56 base + 0x0000000000380000 + + + D056_ADDR_WIDTH + Range 56 size + 16 + + + D056_READ_WRITE_MODE + Range 56 access mode + READ_WRITE + + + D057_BASE_ADDR + Range 57 base + 0x0000000000390000 + + + D057_ADDR_WIDTH + Range 57 size + 16 + + + D057_READ_WRITE_MODE + Range 57 access mode + READ_WRITE + + + D058_BASE_ADDR + Range 58 base + 0x00000000003a0000 + + + D058_ADDR_WIDTH + Range 58 size + 16 + + + D058_READ_WRITE_MODE + Range 58 access mode + READ_WRITE + + + D059_BASE_ADDR + Range 59 base + 0x00000000003b0000 + + + D059_ADDR_WIDTH + Range 59 size + 16 + + + D059_READ_WRITE_MODE + Range 59 access mode + READ_WRITE + + + D060_BASE_ADDR + Range 60 base + 0x00000000003c0000 + + + D060_ADDR_WIDTH + Range 60 size + 16 + + + D060_READ_WRITE_MODE + Range 60 access mode + READ_WRITE + + + D061_BASE_ADDR + Range 61 base + 0x00000000003d0000 + + + D061_ADDR_WIDTH + Range 61 size + 16 + + + D061_READ_WRITE_MODE + Range 61 access mode + READ_WRITE + + + D062_BASE_ADDR + Range 62 base + 0x00000000003e0000 + + + D062_ADDR_WIDTH + Range 62 size + 16 + + + D062_READ_WRITE_MODE + Range 62 access mode + READ_WRITE + + + D063_BASE_ADDR + Range 63 base + 0x00000000003f0000 + + + D063_ADDR_WIDTH + Range 63 size + 16 + + + D063_READ_WRITE_MODE + Range 63 access mode + READ_WRITE + + + D064_BASE_ADDR + Range 64 base + 0x0000000000400000 + + + D064_ADDR_WIDTH + Range 64 size + 16 + + + D064_READ_WRITE_MODE + Range 64 access mode + READ_WRITE + + + D065_BASE_ADDR + Range 65 base + 0x0000000000410000 + + + D065_ADDR_WIDTH + Range 65 size + 16 + + + D065_READ_WRITE_MODE + Range 65 access mode + READ_WRITE + + + D066_BASE_ADDR + Range 66 base + 0x0000000000420000 + + + D066_ADDR_WIDTH + Range 66 size + 16 + + + D066_READ_WRITE_MODE + Range 66 access mode + READ_WRITE + + + D067_BASE_ADDR + Range 67 base + 0x0000000000430000 + + + D067_ADDR_WIDTH + Range 67 size + 16 + + + D067_READ_WRITE_MODE + Range 67 access mode + READ_WRITE + + + D068_BASE_ADDR + Range 68 base + 0x0000000000440000 + + + D068_ADDR_WIDTH + Range 68 size + 16 + + + D068_READ_WRITE_MODE + Range 68 access mode + READ_WRITE + + + D069_BASE_ADDR + Range 69 base + 0x0000000000450000 + + + D069_ADDR_WIDTH + Range 69 size + 16 + + + D069_READ_WRITE_MODE + Range 69 access mode + READ_WRITE + + + D070_BASE_ADDR + Range 70 base + 0x0000000000460000 + + + D070_ADDR_WIDTH + Range 70 size + 16 + + + D070_READ_WRITE_MODE + Range 70 access mode + READ_WRITE + + + D071_BASE_ADDR + Range 71 base + 0x0000000000470000 + + + D071_ADDR_WIDTH + Range 71 size + 16 + + + D071_READ_WRITE_MODE + Range 71 access mode + READ_WRITE + + + D072_BASE_ADDR + Range 72 base + 0x0000000000480000 + + + D072_ADDR_WIDTH + Range 72 size + 16 + + + D072_READ_WRITE_MODE + Range 72 access mode + READ_WRITE + + + D073_BASE_ADDR + Range 73 base + 0x0000000000490000 + + + D073_ADDR_WIDTH + Range 73 size + 16 + + + D073_READ_WRITE_MODE + Range 73 access mode + READ_WRITE + + + D074_BASE_ADDR + Range 74 base + 0x00000000004a0000 + + + D074_ADDR_WIDTH + Range 74 size + 16 + + + D074_READ_WRITE_MODE + Range 74 access mode + READ_WRITE + + + D075_BASE_ADDR + Range 75 base + 0x00000000004b0000 + + + D075_ADDR_WIDTH + Range 75 size + 16 + + + D075_READ_WRITE_MODE + Range 75 access mode + READ_WRITE + + + D076_BASE_ADDR + Range 76 base + 0x00000000004c0000 + + + D076_ADDR_WIDTH + Range 76 size + 16 + + + D076_READ_WRITE_MODE + Range 76 access mode + READ_WRITE + + + D077_BASE_ADDR + Range 77 base + 0x00000000004d0000 + + + D077_ADDR_WIDTH + Range 77 size + 16 + + + D077_READ_WRITE_MODE + Range 77 access mode + READ_WRITE + + + D078_BASE_ADDR + Range 78 base + 0x00000000004e0000 + + + D078_ADDR_WIDTH + Range 78 size + 16 + + + D078_READ_WRITE_MODE + Range 78 access mode + READ_WRITE + + + D079_BASE_ADDR + Range 79 base + 0x00000000004f0000 + + + D079_ADDR_WIDTH + Range 79 size + 16 + + + D079_READ_WRITE_MODE + Range 79 access mode + READ_WRITE + + + D080_BASE_ADDR + Range 80 base + 0x0000000000500000 + + + D080_ADDR_WIDTH + Range 80 size + 16 + + + D080_READ_WRITE_MODE + Range 80 access mode + READ_WRITE + + + D081_BASE_ADDR + Range 81 base + 0x0000000000510000 + + + D081_ADDR_WIDTH + Range 81 size + 16 + + + D081_READ_WRITE_MODE + Range 81 access mode + READ_WRITE + + + D082_BASE_ADDR + Range 82 base + 0x0000000000520000 + + + D082_ADDR_WIDTH + Range 82 size + 16 + + + D082_READ_WRITE_MODE + Range 82 access mode + READ_WRITE + + + D083_BASE_ADDR + Range 83 base + 0x0000000000530000 + + + D083_ADDR_WIDTH + Range 83 size + 16 + + + D083_READ_WRITE_MODE + Range 83 access mode + READ_WRITE + + + D084_BASE_ADDR + Range 84 base + 0x0000000000540000 + + + D084_ADDR_WIDTH + Range 84 size + 16 + + + D084_READ_WRITE_MODE + Range 84 access mode + READ_WRITE + + + D085_BASE_ADDR + Range 85 base + 0x0000000000550000 + + + D085_ADDR_WIDTH + Range 85 size + 16 + + + D085_READ_WRITE_MODE + Range 85 access mode + READ_WRITE + + + D086_BASE_ADDR + Range 86 base + 0x0000000000560000 + + + D086_ADDR_WIDTH + Range 86 size + 16 + + + D086_READ_WRITE_MODE + Range 86 access mode + READ_WRITE + + + D087_BASE_ADDR + Range 87 base + 0x0000000000570000 + + + D087_ADDR_WIDTH + Range 87 size + 16 + + + D087_READ_WRITE_MODE + Range 87 access mode + READ_WRITE + + + D088_BASE_ADDR + Range 88 base + 0x0000000000580000 + + + D088_ADDR_WIDTH + Range 88 size + 16 + + + D088_READ_WRITE_MODE + Range 88 access mode + READ_WRITE + + + D089_BASE_ADDR + Range 89 base + 0x0000000000590000 + + + D089_ADDR_WIDTH + Range 89 size + 16 + + + D089_READ_WRITE_MODE + Range 89 access mode + READ_WRITE + + + D090_BASE_ADDR + Range 90 base + 0x00000000005a0000 + + + D090_ADDR_WIDTH + Range 90 size + 16 + + + D090_READ_WRITE_MODE + Range 90 access mode + READ_WRITE + + + D091_BASE_ADDR + Range 91 base + 0x00000000005b0000 + + + D091_ADDR_WIDTH + Range 91 size + 16 + + + D091_READ_WRITE_MODE + Range 91 access mode + READ_WRITE + + + D092_BASE_ADDR + Range 92 base + 0x00000000005c0000 + + + D092_ADDR_WIDTH + Range 92 size + 16 + + + D092_READ_WRITE_MODE + Range 92 access mode + READ_WRITE + + + D093_BASE_ADDR + Range 93 base + 0x00000000005d0000 + + + D093_ADDR_WIDTH + Range 93 size + 16 + + + D093_READ_WRITE_MODE + Range 93 access mode + READ_WRITE + + + D094_BASE_ADDR + Range 94 base + 0x00000000005e0000 + + + D094_ADDR_WIDTH + Range 94 size + 16 + + + D094_READ_WRITE_MODE + Range 94 access mode + READ_WRITE + + + D095_BASE_ADDR + Range 95 base + 0x00000000005f0000 + + + D095_ADDR_WIDTH + Range 95 size + 16 + + + D095_READ_WRITE_MODE + Range 95 access mode + READ_WRITE + + + D096_BASE_ADDR + Range 96 base + 0x0000000000600000 + + + D096_ADDR_WIDTH + Range 96 size + 16 + + + D096_READ_WRITE_MODE + Range 96 access mode + READ_WRITE + + + D097_BASE_ADDR + Range 97 base + 0x0000000000610000 + + + D097_ADDR_WIDTH + Range 97 size + 16 + + + D097_READ_WRITE_MODE + Range 97 access mode + READ_WRITE + + + D098_BASE_ADDR + Range 98 base + 0x0000000000620000 + + + D098_ADDR_WIDTH + Range 98 size + 16 + + + D098_READ_WRITE_MODE + Range 98 access mode + READ_WRITE + + + D099_BASE_ADDR + Range 99 base + 0x0000000000630000 + + + D099_ADDR_WIDTH + Range 99 size + 16 + + + D099_READ_WRITE_MODE + Range 99 access mode + READ_WRITE + + + D100_BASE_ADDR + Range 100 base + 0x0000000000640000 + + + D100_ADDR_WIDTH + Range 100 size + 16 + + + D100_READ_WRITE_MODE + Range 100 access mode + READ_WRITE + + + D101_BASE_ADDR + Range 101 base + 0x0000000000650000 + + + D101_ADDR_WIDTH + Range 101 size + 16 + + + D101_READ_WRITE_MODE + Range 101 access mode + READ_WRITE + + + D102_BASE_ADDR + Range 102 base + 0x0000000000660000 + + + D102_ADDR_WIDTH + Range 102 size + 16 + + + D102_READ_WRITE_MODE + Range 102 access mode + READ_WRITE + + + D103_BASE_ADDR + Range 103 base + 0x0000000000670000 + + + D103_ADDR_WIDTH + Range 103 size + 16 + + + D103_READ_WRITE_MODE + Range 103 access mode + READ_WRITE + + + D104_BASE_ADDR + Range 104 base + 0x0000000000680000 + + + D104_ADDR_WIDTH + Range 104 size + 16 + + + D104_READ_WRITE_MODE + Range 104 access mode + READ_WRITE + + + D105_BASE_ADDR + Range 105 base + 0x0000000000690000 + + + D105_ADDR_WIDTH + Range 105 size + 16 + + + D105_READ_WRITE_MODE + Range 105 access mode + READ_WRITE + + + D106_BASE_ADDR + Range 106 base + 0x00000000006a0000 + + + D106_ADDR_WIDTH + Range 106 size + 16 + + + D106_READ_WRITE_MODE + Range 106 access mode + READ_WRITE + + + D107_BASE_ADDR + Range 107 base + 0x00000000006b0000 + + + D107_ADDR_WIDTH + Range 107 size + 16 + + + D107_READ_WRITE_MODE + Range 107 access mode + READ_WRITE + + + D108_BASE_ADDR + Range 108 base + 0x00000000006c0000 + + + D108_ADDR_WIDTH + Range 108 size + 16 + + + D108_READ_WRITE_MODE + Range 108 access mode + READ_WRITE + + + D109_BASE_ADDR + Range 109 base + 0x00000000006d0000 + + + D109_ADDR_WIDTH + Range 109 size + 16 + + + D109_READ_WRITE_MODE + Range 109 access mode + READ_WRITE + + + D110_BASE_ADDR + Range 110 base + 0x00000000006e0000 + + + D110_ADDR_WIDTH + Range 110 size + 16 + + + D110_READ_WRITE_MODE + Range 110 access mode + READ_WRITE + + + D111_BASE_ADDR + Range 111 base + 0x00000000006f0000 + + + D111_ADDR_WIDTH + Range 111 size + 16 + + + D111_READ_WRITE_MODE + Range 111 access mode + READ_WRITE + + + D112_BASE_ADDR + Range 112 base + 0x0000000000700000 + + + D112_ADDR_WIDTH + Range 112 size + 16 + + + D112_READ_WRITE_MODE + Range 112 access mode + READ_WRITE + + + D113_BASE_ADDR + Range 113 base + 0x0000000000710000 + + + D113_ADDR_WIDTH + Range 113 size + 16 + + + D113_READ_WRITE_MODE + Range 113 access mode + READ_WRITE + + + D114_BASE_ADDR + Range 114 base + 0x0000000000720000 + + + D114_ADDR_WIDTH + Range 114 size + 16 + + + D114_READ_WRITE_MODE + Range 114 access mode + READ_WRITE + + + D115_BASE_ADDR + Range 115 base + 0x0000000000730000 + + + D115_ADDR_WIDTH + Range 115 size + 16 + + + D115_READ_WRITE_MODE + Range 115 access mode + READ_WRITE + + + D116_BASE_ADDR + Range 116 base + 0x0000000000740000 + + + D116_ADDR_WIDTH + Range 116 size + 16 + + + D116_READ_WRITE_MODE + Range 116 access mode + READ_WRITE + + + D117_BASE_ADDR + Range 117 base + 0x0000000000750000 + + + D117_ADDR_WIDTH + Range 117 size + 16 + + + D117_READ_WRITE_MODE + Range 117 access mode + READ_WRITE + + + D118_BASE_ADDR + Range 118 base + 0x0000000000760000 + + + D118_ADDR_WIDTH + Range 118 size + 16 + + + D118_READ_WRITE_MODE + Range 118 access mode + READ_WRITE + + + D119_BASE_ADDR + Range 119 base + 0x0000000000770000 + + + D119_ADDR_WIDTH + Range 119 size + 16 + + + D119_READ_WRITE_MODE + Range 119 access mode + READ_WRITE + + + D120_BASE_ADDR + Range 120 base + 0x0000000000780000 + + + D120_ADDR_WIDTH + Range 120 size + 16 + + + D120_READ_WRITE_MODE + Range 120 access mode + READ_WRITE + + + D121_BASE_ADDR + Range 121 base + 0x0000000000790000 + + + D121_ADDR_WIDTH + Range 121 size + 16 + + + D121_READ_WRITE_MODE + Range 121 access mode + READ_WRITE + + + D122_BASE_ADDR + Range 122 base + 0x00000000007a0000 + + + D122_ADDR_WIDTH + Range 122 size + 16 + + + D122_READ_WRITE_MODE + Range 122 access mode + READ_WRITE + + + D123_BASE_ADDR + Range 123 base + 0x00000000007b0000 + + + D123_ADDR_WIDTH + Range 123 size + 16 + + + D123_READ_WRITE_MODE + Range 123 access mode + READ_WRITE + + + D124_BASE_ADDR + Range 124 base + 0x00000000007c0000 + + + D124_ADDR_WIDTH + Range 124 size + 16 + + + D124_READ_WRITE_MODE + Range 124 access mode + READ_WRITE + + + D125_BASE_ADDR + Range 125 base + 0x00000000007d0000 + + + D125_ADDR_WIDTH + Range 125 size + 16 + + + D125_READ_WRITE_MODE + Range 125 access mode + READ_WRITE + + + D126_BASE_ADDR + Range 126 base + 0x00000000007e0000 + + + D126_ADDR_WIDTH + Range 126 size + 16 + + + D126_READ_WRITE_MODE + Range 126 access mode + READ_WRITE + + + D127_BASE_ADDR + Range 127 base + 0x00000000007f0000 + + + D127_ADDR_WIDTH + Range 127 size + 16 + + + D127_READ_WRITE_MODE + Range 127 access mode + READ_WRITE + + + D128_BASE_ADDR + Range 128 base + 0x0000000000800000 + + + D128_ADDR_WIDTH + Range 128 size + 16 + + + D128_READ_WRITE_MODE + Range 128 access mode + READ_WRITE + + + D129_BASE_ADDR + Range 129 base + 0x0000000000810000 + + + D129_ADDR_WIDTH + Range 129 size + 16 + + + D129_READ_WRITE_MODE + Range 129 access mode + READ_WRITE + + + D130_BASE_ADDR + Range 130 base + 0x0000000000820000 + + + D130_ADDR_WIDTH + Range 130 size + 16 + + + D130_READ_WRITE_MODE + Range 130 access mode + READ_WRITE + + + D131_BASE_ADDR + Range 131 base + 0x0000000000830000 + + + D131_ADDR_WIDTH + Range 131 size + 16 + + + D131_READ_WRITE_MODE + Range 131 access mode + READ_WRITE + + + D132_BASE_ADDR + Range 132 base + 0x0000000000840000 + + + D132_ADDR_WIDTH + Range 132 size + 16 + + + D132_READ_WRITE_MODE + Range 132 access mode + READ_WRITE + + + D133_BASE_ADDR + Range 133 base + 0x0000000000850000 + + + D133_ADDR_WIDTH + Range 133 size + 16 + + + D133_READ_WRITE_MODE + Range 133 access mode + READ_WRITE + + + D134_BASE_ADDR + Range 134 base + 0x0000000000860000 + + + D134_ADDR_WIDTH + Range 134 size + 16 + + + D134_READ_WRITE_MODE + Range 134 access mode + READ_WRITE + + + D135_BASE_ADDR + Range 135 base + 0x0000000000870000 + + + D135_ADDR_WIDTH + Range 135 size + 16 + + + D135_READ_WRITE_MODE + Range 135 access mode + READ_WRITE + + + D136_BASE_ADDR + Range 136 base + 0x0000000000880000 + + + D136_ADDR_WIDTH + Range 136 size + 16 + + + D136_READ_WRITE_MODE + Range 136 access mode + READ_WRITE + + + D137_BASE_ADDR + Range 137 base + 0x0000000000890000 + + + D137_ADDR_WIDTH + Range 137 size + 16 + + + D137_READ_WRITE_MODE + Range 137 access mode + READ_WRITE + + + D138_BASE_ADDR + Range 138 base + 0x00000000008a0000 + + + D138_ADDR_WIDTH + Range 138 size + 16 + + + D138_READ_WRITE_MODE + Range 138 access mode + READ_WRITE + + + D139_BASE_ADDR + Range 139 base + 0x00000000008b0000 + + + D139_ADDR_WIDTH + Range 139 size + 16 + + + D139_READ_WRITE_MODE + Range 139 access mode + READ_WRITE + + + D140_BASE_ADDR + Range 140 base + 0x00000000008c0000 + + + D140_ADDR_WIDTH + Range 140 size + 16 + + + D140_READ_WRITE_MODE + Range 140 access mode + READ_WRITE + + + D141_BASE_ADDR + Range 141 base + 0x00000000008d0000 + + + D141_ADDR_WIDTH + Range 141 size + 16 + + + D141_READ_WRITE_MODE + Range 141 access mode + READ_WRITE + + + D142_BASE_ADDR + Range 142 base + 0x00000000008e0000 + + + D142_ADDR_WIDTH + Range 142 size + 16 + + + D142_READ_WRITE_MODE + Range 142 access mode + READ_WRITE + + + D143_BASE_ADDR + Range 143 base + 0x00000000008f0000 + + + D143_ADDR_WIDTH + Range 143 size + 16 + + + D143_READ_WRITE_MODE + Range 143 access mode + READ_WRITE + + + D144_BASE_ADDR + Range 144 base + 0x0000000000900000 + + + D144_ADDR_WIDTH + Range 144 size + 16 + + + D144_READ_WRITE_MODE + Range 144 access mode + READ_WRITE + + + D145_BASE_ADDR + Range 145 base + 0x0000000000910000 + + + D145_ADDR_WIDTH + Range 145 size + 16 + + + D145_READ_WRITE_MODE + Range 145 access mode + READ_WRITE + + + D146_BASE_ADDR + Range 146 base + 0x0000000000920000 + + + D146_ADDR_WIDTH + Range 146 size + 16 + + + D146_READ_WRITE_MODE + Range 146 access mode + READ_WRITE + + + D147_BASE_ADDR + Range 147 base + 0x0000000000930000 + + + D147_ADDR_WIDTH + Range 147 size + 16 + + + D147_READ_WRITE_MODE + Range 147 access mode + READ_WRITE + + + D148_BASE_ADDR + Range 148 base + 0x0000000000940000 + + + D148_ADDR_WIDTH + Range 148 size + 16 + + + D148_READ_WRITE_MODE + Range 148 access mode + READ_WRITE + + + D149_BASE_ADDR + Range 149 base + 0x0000000000950000 + + + D149_ADDR_WIDTH + Range 149 size + 16 + + + D149_READ_WRITE_MODE + Range 149 access mode + READ_WRITE + + + D150_BASE_ADDR + Range 150 base + 0x0000000000960000 + + + D150_ADDR_WIDTH + Range 150 size + 16 + + + D150_READ_WRITE_MODE + Range 150 access mode + READ_WRITE + + + D151_BASE_ADDR + Range 151 base + 0x0000000000970000 + + + D151_ADDR_WIDTH + Range 151 size + 16 + + + D151_READ_WRITE_MODE + Range 151 access mode + READ_WRITE + + + D152_BASE_ADDR + Range 152 base + 0x0000000000980000 + + + D152_ADDR_WIDTH + Range 152 size + 16 + + + D152_READ_WRITE_MODE + Range 152 access mode + READ_WRITE + + + D153_BASE_ADDR + Range 153 base + 0x0000000000990000 + + + D153_ADDR_WIDTH + Range 153 size + 16 + + + D153_READ_WRITE_MODE + Range 153 access mode + READ_WRITE + + + D154_BASE_ADDR + Range 154 base + 0x00000000009a0000 + + + D154_ADDR_WIDTH + Range 154 size + 16 + + + D154_READ_WRITE_MODE + Range 154 access mode + READ_WRITE + + + D155_BASE_ADDR + Range 155 base + 0x00000000009b0000 + + + D155_ADDR_WIDTH + Range 155 size + 16 + + + D155_READ_WRITE_MODE + Range 155 access mode + READ_WRITE + + + D156_BASE_ADDR + Range 156 base + 0x00000000009c0000 + + + D156_ADDR_WIDTH + Range 156 size + 16 + + + D156_READ_WRITE_MODE + Range 156 access mode + READ_WRITE + + + D157_BASE_ADDR + Range 157 base + 0x00000000009d0000 + + + D157_ADDR_WIDTH + Range 157 size + 16 + + + D157_READ_WRITE_MODE + Range 157 access mode + READ_WRITE + + + D158_BASE_ADDR + Range 158 base + 0x00000000009e0000 + + + D158_ADDR_WIDTH + Range 158 size + 16 + + + D158_READ_WRITE_MODE + Range 158 access mode + READ_WRITE + + + D159_BASE_ADDR + Range 159 base + 0x00000000009f0000 + + + D159_ADDR_WIDTH + Range 159 size + 16 + + + D159_READ_WRITE_MODE + Range 159 access mode + READ_WRITE + + + D160_BASE_ADDR + Range 160 base + 0x0000000000a00000 + + + D160_ADDR_WIDTH + Range 160 size + 16 + + + D160_READ_WRITE_MODE + Range 160 access mode + READ_WRITE + + + D161_BASE_ADDR + Range 161 base + 0x0000000000a10000 + + + D161_ADDR_WIDTH + Range 161 size + 16 + + + D161_READ_WRITE_MODE + Range 161 access mode + READ_WRITE + + + D162_BASE_ADDR + Range 162 base + 0x0000000000a20000 + + + D162_ADDR_WIDTH + Range 162 size + 16 + + + D162_READ_WRITE_MODE + Range 162 access mode + READ_WRITE + + + D163_BASE_ADDR + Range 163 base + 0x0000000000a30000 + + + D163_ADDR_WIDTH + Range 163 size + 16 + + + D163_READ_WRITE_MODE + Range 163 access mode + READ_WRITE + + + D164_BASE_ADDR + Range 164 base + 0x0000000000a40000 + + + D164_ADDR_WIDTH + Range 164 size + 16 + + + D164_READ_WRITE_MODE + Range 164 access mode + READ_WRITE + + + D165_BASE_ADDR + Range 165 base + 0x0000000000a50000 + + + D165_ADDR_WIDTH + Range 165 size + 16 + + + D165_READ_WRITE_MODE + Range 165 access mode + READ_WRITE + + + D166_BASE_ADDR + Range 166 base + 0x0000000000a60000 + + + D166_ADDR_WIDTH + Range 166 size + 16 + + + D166_READ_WRITE_MODE + Range 166 access mode + READ_WRITE + + + D167_BASE_ADDR + Range 167 base + 0x0000000000a70000 + + + D167_ADDR_WIDTH + Range 167 size + 16 + + + D167_READ_WRITE_MODE + Range 167 access mode + READ_WRITE + + + D168_BASE_ADDR + Range 168 base + 0x0000000000a80000 + + + D168_ADDR_WIDTH + Range 168 size + 16 + + + D168_READ_WRITE_MODE + Range 168 access mode + READ_WRITE + + + D169_BASE_ADDR + Range 169 base + 0x0000000000a90000 + + + D169_ADDR_WIDTH + Range 169 size + 16 + + + D169_READ_WRITE_MODE + Range 169 access mode + READ_WRITE + + + D170_BASE_ADDR + Range 170 base + 0x0000000000aa0000 + + + D170_ADDR_WIDTH + Range 170 size + 16 + + + D170_READ_WRITE_MODE + Range 170 access mode + READ_WRITE + + + D171_BASE_ADDR + Range 171 base + 0x0000000000ab0000 + + + D171_ADDR_WIDTH + Range 171 size + 16 + + + D171_READ_WRITE_MODE + Range 171 access mode + READ_WRITE + + + D172_BASE_ADDR + Range 172 base + 0x0000000000ac0000 + + + D172_ADDR_WIDTH + Range 172 size + 16 + + + D172_READ_WRITE_MODE + Range 172 access mode + READ_WRITE + + + D173_BASE_ADDR + Range 173 base + 0x0000000000ad0000 + + + D173_ADDR_WIDTH + Range 173 size + 16 + + + D173_READ_WRITE_MODE + Range 173 access mode + READ_WRITE + + + D174_BASE_ADDR + Range 174 base + 0x0000000000ae0000 + + + D174_ADDR_WIDTH + Range 174 size + 16 + + + D174_READ_WRITE_MODE + Range 174 access mode + READ_WRITE + + + D175_BASE_ADDR + Range 175 base + 0x0000000000af0000 + + + D175_ADDR_WIDTH + Range 175 size + 16 + + + D175_READ_WRITE_MODE + Range 175 access mode + READ_WRITE + + + D176_BASE_ADDR + Range 176 base + 0x0000000000b00000 + + + D176_ADDR_WIDTH + Range 176 size + 16 + + + D176_READ_WRITE_MODE + Range 176 access mode + READ_WRITE + + + D177_BASE_ADDR + Range 177 base + 0x0000000000b10000 + + + D177_ADDR_WIDTH + Range 177 size + 16 + + + D177_READ_WRITE_MODE + Range 177 access mode + READ_WRITE + + + D178_BASE_ADDR + Range 178 base + 0x0000000000b20000 + + + D178_ADDR_WIDTH + Range 178 size + 16 + + + D178_READ_WRITE_MODE + Range 178 access mode + READ_WRITE + + + D179_BASE_ADDR + Range 179 base + 0x0000000000b30000 + + + D179_ADDR_WIDTH + Range 179 size + 16 + + + D179_READ_WRITE_MODE + Range 179 access mode + READ_WRITE + + + D180_BASE_ADDR + Range 180 base + 0x0000000000b40000 + + + D180_ADDR_WIDTH + Range 180 size + 16 + + + D180_READ_WRITE_MODE + Range 180 access mode + READ_WRITE + + + D181_BASE_ADDR + Range 181 base + 0x0000000000b50000 + + + D181_ADDR_WIDTH + Range 181 size + 16 + + + D181_READ_WRITE_MODE + Range 181 access mode + READ_WRITE + + + D182_BASE_ADDR + Range 182 base + 0x0000000000b60000 + + + D182_ADDR_WIDTH + Range 182 size + 16 + + + D182_READ_WRITE_MODE + Range 182 access mode + READ_WRITE + + + D183_BASE_ADDR + Range 183 base + 0x0000000000b70000 + + + D183_ADDR_WIDTH + Range 183 size + 16 + + + D183_READ_WRITE_MODE + Range 183 access mode + READ_WRITE + + + D184_BASE_ADDR + Range 184 base + 0x0000000000b80000 + + + D184_ADDR_WIDTH + Range 184 size + 16 + + + D184_READ_WRITE_MODE + Range 184 access mode + READ_WRITE + + + D185_BASE_ADDR + Range 185 base + 0x0000000000b90000 + + + D185_ADDR_WIDTH + Range 185 size + 16 + + + D185_READ_WRITE_MODE + Range 185 access mode + READ_WRITE + + + D186_BASE_ADDR + Range 186 base + 0x0000000000ba0000 + + + D186_ADDR_WIDTH + Range 186 size + 16 + + + D186_READ_WRITE_MODE + Range 186 access mode + READ_WRITE + + + D187_BASE_ADDR + Range 187 base + 0x0000000000bb0000 + + + D187_ADDR_WIDTH + Range 187 size + 16 + + + D187_READ_WRITE_MODE + Range 187 access mode + READ_WRITE + + + D188_BASE_ADDR + Range 188 base + 0x0000000000bc0000 + + + D188_ADDR_WIDTH + Range 188 size + 16 + + + D188_READ_WRITE_MODE + Range 188 access mode + READ_WRITE + + + D189_BASE_ADDR + Range 189 base + 0x0000000000bd0000 + + + D189_ADDR_WIDTH + Range 189 size + 16 + + + D189_READ_WRITE_MODE + Range 189 access mode + READ_WRITE + + + D190_BASE_ADDR + Range 190 base + 0x0000000000be0000 + + + D190_ADDR_WIDTH + Range 190 size + 16 + + + D190_READ_WRITE_MODE + Range 190 access mode + READ_WRITE + + + D191_BASE_ADDR + Range 191 base + 0x0000000000bf0000 + + + D191_ADDR_WIDTH + Range 191 size + 16 + + + D191_READ_WRITE_MODE + Range 191 access mode + READ_WRITE + + + D192_BASE_ADDR + Range 192 base + 0x0000000000c00000 + + + D192_ADDR_WIDTH + Range 192 size + 16 + + + D192_READ_WRITE_MODE + Range 192 access mode + READ_WRITE + + + D193_BASE_ADDR + Range 193 base + 0x0000000000c10000 + + + D193_ADDR_WIDTH + Range 193 size + 16 + + + D193_READ_WRITE_MODE + Range 193 access mode + READ_WRITE + + + D194_BASE_ADDR + Range 194 base + 0x0000000000c20000 + + + D194_ADDR_WIDTH + Range 194 size + 16 + + + D194_READ_WRITE_MODE + Range 194 access mode + READ_WRITE + + + D195_BASE_ADDR + Range 195 base + 0x0000000000c30000 + + + D195_ADDR_WIDTH + Range 195 size + 16 + + + D195_READ_WRITE_MODE + Range 195 access mode + READ_WRITE + + + D196_BASE_ADDR + Range 196 base + 0x0000000000c40000 + + + D196_ADDR_WIDTH + Range 196 size + 16 + + + D196_READ_WRITE_MODE + Range 196 access mode + READ_WRITE + + + D197_BASE_ADDR + Range 197 base + 0x0000000000c50000 + + + D197_ADDR_WIDTH + Range 197 size + 16 + + + D197_READ_WRITE_MODE + Range 197 access mode + READ_WRITE + + + D198_BASE_ADDR + Range 198 base + 0x0000000000c60000 + + + D198_ADDR_WIDTH + Range 198 size + 16 + + + D198_READ_WRITE_MODE + Range 198 access mode + READ_WRITE + + + D199_BASE_ADDR + Range 199 base + 0x0000000000c70000 + + + D199_ADDR_WIDTH + Range 199 size + 16 + + + D199_READ_WRITE_MODE + Range 199 access mode + READ_WRITE + + + D200_BASE_ADDR + Range 200 base + 0x0000000000c80000 + + + D200_ADDR_WIDTH + Range 200 size + 16 + + + D200_READ_WRITE_MODE + Range 200 access mode + READ_WRITE + + + D201_BASE_ADDR + Range 201 base + 0x0000000000c90000 + + + D201_ADDR_WIDTH + Range 201 size + 16 + + + D201_READ_WRITE_MODE + Range 201 access mode + READ_WRITE + + + D202_BASE_ADDR + Range 202 base + 0x0000000000ca0000 + + + D202_ADDR_WIDTH + Range 202 size + 16 + + + D202_READ_WRITE_MODE + Range 202 access mode + READ_WRITE + + + D203_BASE_ADDR + Range 203 base + 0x0000000000cb0000 + + + D203_ADDR_WIDTH + Range 203 size + 16 + + + D203_READ_WRITE_MODE + Range 203 access mode + READ_WRITE + + + D204_BASE_ADDR + Range 204 base + 0x0000000000cc0000 + + + D204_ADDR_WIDTH + Range 204 size + 16 + + + D204_READ_WRITE_MODE + Range 204 access mode + READ_WRITE + + + D205_BASE_ADDR + Range 205 base + 0x0000000000cd0000 + + + D205_ADDR_WIDTH + Range 205 size + 16 + + + D205_READ_WRITE_MODE + Range 205 access mode + READ_WRITE + + + D206_BASE_ADDR + Range 206 base + 0x0000000000ce0000 + + + D206_ADDR_WIDTH + Range 206 size + 16 + + + D206_READ_WRITE_MODE + Range 206 access mode + READ_WRITE + + + D207_BASE_ADDR + Range 207 base + 0x0000000000cf0000 + + + D207_ADDR_WIDTH + Range 207 size + 16 + + + D207_READ_WRITE_MODE + Range 207 access mode + READ_WRITE + + + D208_BASE_ADDR + Range 208 base + 0x0000000000d00000 + + + D208_ADDR_WIDTH + Range 208 size + 16 + + + D208_READ_WRITE_MODE + Range 208 access mode + READ_WRITE + + + D209_BASE_ADDR + Range 209 base + 0x0000000000d10000 + + + D209_ADDR_WIDTH + Range 209 size + 16 + + + D209_READ_WRITE_MODE + Range 209 access mode + READ_WRITE + + + D210_BASE_ADDR + Range 210 base + 0x0000000000d20000 + + + D210_ADDR_WIDTH + Range 210 size + 16 + + + D210_READ_WRITE_MODE + Range 210 access mode + READ_WRITE + + + D211_BASE_ADDR + Range 211 base + 0x0000000000d30000 + + + D211_ADDR_WIDTH + Range 211 size + 16 + + + D211_READ_WRITE_MODE + Range 211 access mode + READ_WRITE + + + D212_BASE_ADDR + Range 212 base + 0x0000000000d40000 + + + D212_ADDR_WIDTH + Range 212 size + 16 + + + D212_READ_WRITE_MODE + Range 212 access mode + READ_WRITE + + + D213_BASE_ADDR + Range 213 base + 0x0000000000d50000 + + + D213_ADDR_WIDTH + Range 213 size + 16 + + + D213_READ_WRITE_MODE + Range 213 access mode + READ_WRITE + + + D214_BASE_ADDR + Range 214 base + 0x0000000000d60000 + + + D214_ADDR_WIDTH + Range 214 size + 16 + + + D214_READ_WRITE_MODE + Range 214 access mode + READ_WRITE + + + D215_BASE_ADDR + Range 215 base + 0x0000000000d70000 + + + D215_ADDR_WIDTH + Range 215 size + 16 + + + D215_READ_WRITE_MODE + Range 215 access mode + READ_WRITE + + + D216_BASE_ADDR + Range 216 base + 0x0000000000d80000 + + + D216_ADDR_WIDTH + Range 216 size + 16 + + + D216_READ_WRITE_MODE + Range 216 access mode + READ_WRITE + + + D217_BASE_ADDR + Range 217 base + 0x0000000000d90000 + + + D217_ADDR_WIDTH + Range 217 size + 16 + + + D217_READ_WRITE_MODE + Range 217 access mode + READ_WRITE + + + D218_BASE_ADDR + Range 218 base + 0x0000000000da0000 + + + D218_ADDR_WIDTH + Range 218 size + 16 + + + D218_READ_WRITE_MODE + Range 218 access mode + READ_WRITE + + + D219_BASE_ADDR + Range 219 base + 0x0000000000db0000 + + + D219_ADDR_WIDTH + Range 219 size + 16 + + + D219_READ_WRITE_MODE + Range 219 access mode + READ_WRITE + + + D220_BASE_ADDR + Range 220 base + 0x0000000000dc0000 + + + D220_ADDR_WIDTH + Range 220 size + 16 + + + D220_READ_WRITE_MODE + Range 220 access mode + READ_WRITE + + + D221_BASE_ADDR + Range 221 base + 0x0000000000dd0000 + + + D221_ADDR_WIDTH + Range 221 size + 16 + + + D221_READ_WRITE_MODE + Range 221 access mode + READ_WRITE + + + D222_BASE_ADDR + Range 222 base + 0x0000000000de0000 + + + D222_ADDR_WIDTH + Range 222 size + 16 + + + D222_READ_WRITE_MODE + Range 222 access mode + READ_WRITE + + + D223_BASE_ADDR + Range 223 base + 0x0000000000df0000 + + + D223_ADDR_WIDTH + Range 223 size + 16 + + + D223_READ_WRITE_MODE + Range 223 access mode + READ_WRITE + + + D224_BASE_ADDR + Range 224 base + 0x0000000000e00000 + + + D224_ADDR_WIDTH + Range 224 size + 16 + + + D224_READ_WRITE_MODE + Range 224 access mode + READ_WRITE + + + D225_BASE_ADDR + Range 225 base + 0x0000000000e10000 + + + D225_ADDR_WIDTH + Range 225 size + 16 + + + D225_READ_WRITE_MODE + Range 225 access mode + READ_WRITE + + + D226_BASE_ADDR + Range 226 base + 0x0000000000e20000 + + + D226_ADDR_WIDTH + Range 226 size + 16 + + + D226_READ_WRITE_MODE + Range 226 access mode + READ_WRITE + + + D227_BASE_ADDR + Range 227 base + 0x0000000000e30000 + + + D227_ADDR_WIDTH + Range 227 size + 16 + + + D227_READ_WRITE_MODE + Range 227 access mode + READ_WRITE + + + D228_BASE_ADDR + Range 228 base + 0x0000000000e40000 + + + D228_ADDR_WIDTH + Range 228 size + 16 + + + D228_READ_WRITE_MODE + Range 228 access mode + READ_WRITE + + + D229_BASE_ADDR + Range 229 base + 0x0000000000e50000 + + + D229_ADDR_WIDTH + Range 229 size + 16 + + + D229_READ_WRITE_MODE + Range 229 access mode + READ_WRITE + + + D230_BASE_ADDR + Range 230 base + 0x0000000000e60000 + + + D230_ADDR_WIDTH + Range 230 size + 16 + + + D230_READ_WRITE_MODE + Range 230 access mode + READ_WRITE + + + D231_BASE_ADDR + Range 231 base + 0x0000000000e70000 + + + D231_ADDR_WIDTH + Range 231 size + 16 + + + D231_READ_WRITE_MODE + Range 231 access mode + READ_WRITE + + + D232_BASE_ADDR + Range 232 base + 0x0000000000e80000 + + + D232_ADDR_WIDTH + Range 232 size + 16 + + + D232_READ_WRITE_MODE + Range 232 access mode + READ_WRITE + + + D233_BASE_ADDR + Range 233 base + 0x0000000000e90000 + + + D233_ADDR_WIDTH + Range 233 size + 16 + + + D233_READ_WRITE_MODE + Range 233 access mode + READ_WRITE + + + D234_BASE_ADDR + Range 234 base + 0x0000000000ea0000 + + + D234_ADDR_WIDTH + Range 234 size + 16 + + + D234_READ_WRITE_MODE + Range 234 access mode + READ_WRITE + + + D235_BASE_ADDR + Range 235 base + 0x0000000000eb0000 + + + D235_ADDR_WIDTH + Range 235 size + 16 + + + D235_READ_WRITE_MODE + Range 235 access mode + READ_WRITE + + + D236_BASE_ADDR + Range 236 base + 0x0000000000ec0000 + + + D236_ADDR_WIDTH + Range 236 size + 16 + + + D236_READ_WRITE_MODE + Range 236 access mode + READ_WRITE + + + D237_BASE_ADDR + Range 237 base + 0x0000000000ed0000 + + + D237_ADDR_WIDTH + Range 237 size + 16 + + + D237_READ_WRITE_MODE + Range 237 access mode + READ_WRITE + + + D238_BASE_ADDR + Range 238 base + 0x0000000000ee0000 + + + D238_ADDR_WIDTH + Range 238 size + 16 + + + D238_READ_WRITE_MODE + Range 238 access mode + READ_WRITE + + + D239_BASE_ADDR + Range 239 base + 0x0000000000ef0000 + + + D239_ADDR_WIDTH + Range 239 size + 16 + + + D239_READ_WRITE_MODE + Range 239 access mode + READ_WRITE + + + D240_BASE_ADDR + Range 240 base + 0x0000000000f00000 + + + D240_ADDR_WIDTH + Range 240 size + 16 + + + D240_READ_WRITE_MODE + Range 240 access mode + READ_WRITE + + + D241_BASE_ADDR + Range 241 base + 0x0000000000f10000 + + + D241_ADDR_WIDTH + Range 241 size + 16 + + + D241_READ_WRITE_MODE + Range 241 access mode + READ_WRITE + + + D242_BASE_ADDR + Range 242 base + 0x0000000000f20000 + + + D242_ADDR_WIDTH + Range 242 size + 16 + + + D242_READ_WRITE_MODE + Range 242 access mode + READ_WRITE + + + D243_BASE_ADDR + Range 243 base + 0x0000000000f30000 + + + D243_ADDR_WIDTH + Range 243 size + 16 + + + D243_READ_WRITE_MODE + Range 243 access mode + READ_WRITE + + + D244_BASE_ADDR + Range 244 base + 0x0000000000f40000 + + + D244_ADDR_WIDTH + Range 244 size + 16 + + + D244_READ_WRITE_MODE + Range 244 access mode + READ_WRITE + + + D245_BASE_ADDR + Range 245 base + 0x0000000000f50000 + + + D245_ADDR_WIDTH + Range 245 size + 16 + + + D245_READ_WRITE_MODE + Range 245 access mode + READ_WRITE + + + D246_BASE_ADDR + Range 246 base + 0x0000000000f60000 + + + D246_ADDR_WIDTH + Range 246 size + 16 + + + D246_READ_WRITE_MODE + Range 246 access mode + READ_WRITE + + + D247_BASE_ADDR + Range 247 base + 0x0000000000f70000 + + + D247_ADDR_WIDTH + Range 247 size + 16 + + + D247_READ_WRITE_MODE + Range 247 access mode + READ_WRITE + + + D248_BASE_ADDR + Range 248 base + 0x0000000000f80000 + + + D248_ADDR_WIDTH + Range 248 size + 16 + + + D248_READ_WRITE_MODE + Range 248 access mode + READ_WRITE + + + D249_BASE_ADDR + Range 249 base + 0x0000000000f90000 + + + D249_ADDR_WIDTH + Range 249 size + 16 + + + D249_READ_WRITE_MODE + Range 249 access mode + READ_WRITE + + + D250_BASE_ADDR + Range 250 base + 0x0000000000fa0000 + + + D250_ADDR_WIDTH + Range 250 size + 16 + + + D250_READ_WRITE_MODE + Range 250 access mode + READ_WRITE + + + D251_BASE_ADDR + Range 251 base + 0x0000000000fb0000 + + + D251_ADDR_WIDTH + Range 251 size + 16 + + + D251_READ_WRITE_MODE + Range 251 access mode + READ_WRITE + + + D252_BASE_ADDR + Range 252 base + 0x0000000000fc0000 + + + D252_ADDR_WIDTH + Range 252 size + 16 + + + D252_READ_WRITE_MODE + Range 252 access mode + READ_WRITE + + + D253_BASE_ADDR + Range 253 base + 0x0000000000fd0000 + + + D253_ADDR_WIDTH + Range 253 size + 16 + + + D253_READ_WRITE_MODE + Range 253 access mode + READ_WRITE + + + D254_BASE_ADDR + Range 254 base + 0x0000000000fe0000 + + + D254_ADDR_WIDTH + Range 254 size + 16 + + + D254_READ_WRITE_MODE + Range 254 access mode + READ_WRITE + + + D255_BASE_ADDR + Range 255 base + 0x0000000000ff0000 + + + D255_ADDR_WIDTH + Range 255 size + 16 + + + D255_READ_WRITE_MODE + Range 255 access mode + READ_WRITE + + + Component_Name + pcie_ddr_s01_mmu_1 + + + + + AXI MMU + 18 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xci index f2cc307..3f51892 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xci +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xci @@ -119,12 +119,12 @@ - + - + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xml index 855a636..4517404 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xml +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xml @@ -1869,12 +1869,12 @@ - + - + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_0/pcie_ddr_xbar_0.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_1/pcie_ddr_xbar_1.xci similarity index 97% rename from ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_0/pcie_ddr_xbar_0.xci rename to ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_1/pcie_ddr_xbar_1.xci index 5cd53d1..d76c076 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_0/pcie_ddr_xbar_0.xci +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_1/pcie_ddr_xbar_1.xci @@ -6,39 +6,39 @@ 1.0 - pcie_ddr_xbar_0 + pcie_ddr_xbar_1 M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI ARESETN - - 10000000 + /clk_wiz_0_clk_out1 + 200000000 0 - 0.000 - 32 + 0.0 + 64 0 0 0 - - 32 - 100000000 + /clk_wiz_0_clk_out1 + 512 + 200000000 1 1 1 1 1 1 - 1 + 0 1 1 1 0 256 - 2 + 8 1 - 2 + 8 1 - 0.000 + 0.0 AXI4 READ_WRITE 0 @@ -514,13 +514,13 @@ 0 ACTIVE_LOW INTERCONNECT - 32 + 64 0 0 0 - - 32 - 100000000 + /clk_wiz_0_clk_out1 + 512 + 200000000 1 1 1 @@ -533,11 +533,11 @@ 1 0 256 - 2 - 1 - 2 - 1 - 0.000 + 8 + 2 + 8 + 2 + 0.0 AXI4 READ_WRITE 0 @@ -545,13 +545,13 @@ 1 0 0 - 32 + 64 0 0 0 - - 32 - 100000000 + /clk_wiz_0_clk_out1 + 512 + 200000000 1 1 1 @@ -568,7 +568,7 @@ 1 2 1 - 0.000 + 0.0 AXI4 READ_WRITE 0 @@ -1010,11 +1010,11 @@ 1 0 0 - 32 + 64 1 1 1 - 32 + 512 1 0 1 @@ -1022,34 +1022,34 @@ 1 1 kintex7 - 0x00000000 - 0xffffffffffffffff + 0x00000021 + 0x0000000000000000 0x00000003 - 0x00000004 + 0x00000008 0x00000000 0x00000003 - 0x00000004 + 0x00000008 1 1 2 0 0x0000000000000000 0x0000000100000000 - 0x0000000200000002 + 0x0000000200000008 0x0000000000000000 0x0000000000000000 - 0x0000000200000002 + 0x0000000200000008 1 - 32 + 64 0 0 0 SAMD - pcie_ddr_xbar_0 - 32 + pcie_ddr_xbar_1 + 512 1 - 0 - 0xffffffffffffffff + 33 + 0x0000000000000000 0 0xffffffffffffffff 0 @@ -1081,7 +1081,7 @@ 0 0xffffffffffffffff 0 - 4 + 8 1 1 1 @@ -1115,7 +1115,7 @@ 1 1 0 - 4 + 8 0 0xffffffffffffffff 0 @@ -2143,10 +2143,10 @@ 0 0 0x00000000 - 2 + 8 0 0 - 2 + 8 0 0x00000001 2 @@ -2266,37 +2266,37 @@ - - - - + + + + - + - + - - + + - + - - - + + + - + - + - + @@ -2330,44 +2330,43 @@ - - - - - - - - + + + + + + + - + - + - + - - - - - - + + + + + + - + - - - - - - - - + + + + + + + + @@ -2377,29 +2376,29 @@ - + - + - - - + + + - - + + - - - - - - - - - - - + + + + + + + + + + + @@ -2430,11 +2429,11 @@ - - - - - + + + + + @@ -2463,7 +2462,7 @@ - + @@ -3456,14 +3455,14 @@ - - - - - - - - + + + + + + + + @@ -3507,7 +3506,7 @@ - + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_0/pcie_ddr_xbar_0.xml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_1/pcie_ddr_xbar_1.xml similarity index 98% rename from ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_0/pcie_ddr_xbar_0.xml rename to ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_1/pcie_ddr_xbar_1.xml index 86cd31f..0679747 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_0/pcie_ddr_xbar_0.xml +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xbar_1/pcie_ddr_xbar_1.xml @@ -2,7 +2,7 @@ xilinx.com customized_ip - pcie_ddr_xbar_0 + pcie_ddr_xbar_1 1.0 @@ -72,11 +72,11 @@ FREQ_HZ aclk frequency aclk frequency - 10000000 + 200000000 PHASE - 0.000 + 0.0 none @@ -85,7 +85,7 @@ CLK_DOMAIN - + /clk_wiz_0_clk_out1 none @@ -147,7 +147,7 @@ s_axi_awaddr - 31 + 63 0 @@ -291,7 +291,7 @@ s_axi_wdata - 31 + 511 0 @@ -303,7 +303,7 @@ s_axi_wstrb - 3 + 63 0 @@ -435,7 +435,7 @@ s_axi_araddr - 31 + 63 0 @@ -579,7 +579,7 @@ s_axi_rdata - 31 + 511 0 @@ -648,7 +648,7 @@ DATA_WIDTH - 32 + 512 none @@ -666,7 +666,7 @@ FREQ_HZ - 100000000 + 200000000 none @@ -684,7 +684,7 @@ ADDR_WIDTH - 32 + 64 none @@ -837,7 +837,7 @@ NUM_READ_OUTSTANDING - 2 + 8 none @@ -846,7 +846,7 @@ NUM_WRITE_OUTSTANDING - 2 + 8 none @@ -864,7 +864,7 @@ PHASE - 0.000 + 0.0 none @@ -873,7 +873,7 @@ CLK_DOMAIN - + /clk_wiz_0_clk_out1 none @@ -882,7 +882,7 @@ NUM_READ_THREADS - 1 + 2 none @@ -891,7 +891,7 @@ NUM_WRITE_THREADS - 1 + 2 none @@ -960,7 +960,7 @@ m_axi_awaddr - 31 + 63 0 @@ -1116,7 +1116,7 @@ m_axi_wdata - 31 + 511 0 @@ -1128,7 +1128,7 @@ m_axi_wstrb - 3 + 63 0 @@ -1260,7 +1260,7 @@ m_axi_araddr - 31 + 63 0 @@ -1416,7 +1416,7 @@ m_axi_rdata - 31 + 511 0 @@ -1485,7 +1485,7 @@ DATA_WIDTH - 32 + 512 none @@ -1503,7 +1503,7 @@ FREQ_HZ - 100000000 + 200000000 none @@ -1521,7 +1521,7 @@ ADDR_WIDTH - 32 + 64 none @@ -1629,7 +1629,7 @@ HAS_REGION - 1 + 0 none @@ -1674,7 +1674,7 @@ NUM_READ_OUTSTANDING - 2 + 8 none @@ -1683,7 +1683,7 @@ NUM_WRITE_OUTSTANDING - 2 + 8 none @@ -1701,7 +1701,7 @@ PHASE - 0.000 + 0.0 none @@ -1710,7 +1710,7 @@ CLK_DOMAIN - + /clk_wiz_0_clk_out1 none @@ -1797,8 +1797,8 @@ s_axi_awaddr - 63 - 32 + 127 + 64 @@ -1941,8 +1941,8 @@ s_axi_wdata - 63 - 32 + 1023 + 512 @@ -1953,8 +1953,8 @@ s_axi_wstrb - 7 - 4 + 127 + 64 @@ -2085,8 +2085,8 @@ s_axi_araddr - 63 - 32 + 127 + 64 @@ -2229,8 +2229,8 @@ s_axi_rdata - 63 - 32 + 1023 + 512 @@ -2298,7 +2298,7 @@ DATA_WIDTH - 32 + 512 none @@ -2316,7 +2316,7 @@ FREQ_HZ - 100000000 + 200000000 none @@ -2334,7 +2334,7 @@ ADDR_WIDTH - 32 + 64 none @@ -2514,7 +2514,7 @@ PHASE - 0.000 + 0.0 none @@ -2523,7 +2523,7 @@ CLK_DOMAIN - + /clk_wiz_0_clk_out1 none @@ -2610,8 +2610,8 @@ m_axi_awaddr - 63 - 32 + 127 + 64 @@ -2766,8 +2766,8 @@ m_axi_wdata - 63 - 32 + 1023 + 512 @@ -2778,8 +2778,8 @@ m_axi_wstrb - 7 - 4 + 127 + 64 @@ -2910,8 +2910,8 @@ m_axi_araddr - 63 - 32 + 127 + 64 @@ -3066,8 +3066,8 @@ m_axi_rdata - 63 - 32 + 1023 + 512 @@ -3447,8 +3447,8 @@ s_axi_awaddr - 95 - 64 + 191 + 128 @@ -3591,8 +3591,8 @@ s_axi_wdata - 95 - 64 + 1535 + 1024 @@ -3603,8 +3603,8 @@ s_axi_wstrb - 11 - 8 + 191 + 128 @@ -3735,8 +3735,8 @@ s_axi_araddr - 95 - 64 + 191 + 128 @@ -3879,8 +3879,8 @@ s_axi_rdata - 95 - 64 + 1535 + 1024 @@ -4260,8 +4260,8 @@ m_axi_awaddr - 95 - 64 + 191 + 128 @@ -4416,8 +4416,8 @@ m_axi_wdata - 95 - 64 + 1535 + 1024 @@ -4428,8 +4428,8 @@ m_axi_wstrb - 11 - 8 + 191 + 128 @@ -4560,8 +4560,8 @@ m_axi_araddr - 95 - 64 + 191 + 128 @@ -4716,8 +4716,8 @@ m_axi_rdata - 95 - 64 + 1535 + 1024 @@ -5097,8 +5097,8 @@ s_axi_awaddr - 127 - 96 + 255 + 192 @@ -5241,8 +5241,8 @@ s_axi_wdata - 127 - 96 + 2047 + 1536 @@ -5253,8 +5253,8 @@ s_axi_wstrb - 15 - 12 + 255 + 192 @@ -5385,8 +5385,8 @@ s_axi_araddr - 127 - 96 + 255 + 192 @@ -5529,8 +5529,8 @@ s_axi_rdata - 127 - 96 + 2047 + 1536 @@ -5910,8 +5910,8 @@ m_axi_awaddr - 127 - 96 + 255 + 192 @@ -6066,8 +6066,8 @@ m_axi_wdata - 127 - 96 + 2047 + 1536 @@ -6078,8 +6078,8 @@ m_axi_wstrb - 15 - 12 + 255 + 192 @@ -6210,8 +6210,8 @@ m_axi_araddr - 127 - 96 + 255 + 192 @@ -6366,8 +6366,8 @@ m_axi_rdata - 127 - 96 + 2047 + 1536 @@ -6747,8 +6747,8 @@ s_axi_awaddr - 159 - 128 + 319 + 256 @@ -6891,8 +6891,8 @@ s_axi_wdata - 159 - 128 + 2559 + 2048 @@ -6903,8 +6903,8 @@ s_axi_wstrb - 19 - 16 + 319 + 256 @@ -7035,8 +7035,8 @@ s_axi_araddr - 159 - 128 + 319 + 256 @@ -7179,8 +7179,8 @@ s_axi_rdata - 159 - 128 + 2559 + 2048 @@ -7560,8 +7560,8 @@ m_axi_awaddr - 159 - 128 + 319 + 256 @@ -7716,8 +7716,8 @@ m_axi_wdata - 159 - 128 + 2559 + 2048 @@ -7728,8 +7728,8 @@ m_axi_wstrb - 19 - 16 + 319 + 256 @@ -7860,8 +7860,8 @@ m_axi_araddr - 159 - 128 + 319 + 256 @@ -8016,8 +8016,8 @@ m_axi_rdata - 159 - 128 + 2559 + 2048 @@ -8397,8 +8397,8 @@ s_axi_awaddr - 191 - 160 + 383 + 320 @@ -8541,8 +8541,8 @@ s_axi_wdata - 191 - 160 + 3071 + 2560 @@ -8553,8 +8553,8 @@ s_axi_wstrb - 23 - 20 + 383 + 320 @@ -8685,8 +8685,8 @@ s_axi_araddr - 191 - 160 + 383 + 320 @@ -8829,8 +8829,8 @@ s_axi_rdata - 191 - 160 + 3071 + 2560 @@ -9210,8 +9210,8 @@ m_axi_awaddr - 191 - 160 + 383 + 320 @@ -9366,8 +9366,8 @@ m_axi_wdata - 191 - 160 + 3071 + 2560 @@ -9378,8 +9378,8 @@ m_axi_wstrb - 23 - 20 + 383 + 320 @@ -9510,8 +9510,8 @@ m_axi_araddr - 191 - 160 + 383 + 320 @@ -9666,8 +9666,8 @@ m_axi_rdata - 191 - 160 + 3071 + 2560 @@ -10047,8 +10047,8 @@ s_axi_awaddr - 223 - 192 + 447 + 384 @@ -10191,8 +10191,8 @@ s_axi_wdata - 223 - 192 + 3583 + 3072 @@ -10203,8 +10203,8 @@ s_axi_wstrb - 27 - 24 + 447 + 384 @@ -10335,8 +10335,8 @@ s_axi_araddr - 223 - 192 + 447 + 384 @@ -10479,8 +10479,8 @@ s_axi_rdata - 223 - 192 + 3583 + 3072 @@ -10860,8 +10860,8 @@ m_axi_awaddr - 223 - 192 + 447 + 384 @@ -11016,8 +11016,8 @@ m_axi_wdata - 223 - 192 + 3583 + 3072 @@ -11028,8 +11028,8 @@ m_axi_wstrb - 27 - 24 + 447 + 384 @@ -11160,8 +11160,8 @@ m_axi_araddr - 223 - 192 + 447 + 384 @@ -11316,8 +11316,8 @@ m_axi_rdata - 223 - 192 + 3583 + 3072 @@ -11697,8 +11697,8 @@ s_axi_awaddr - 255 - 224 + 511 + 448 @@ -11841,8 +11841,8 @@ s_axi_wdata - 255 - 224 + 4095 + 3584 @@ -11853,8 +11853,8 @@ s_axi_wstrb - 31 - 28 + 511 + 448 @@ -11985,8 +11985,8 @@ s_axi_araddr - 255 - 224 + 511 + 448 @@ -12129,8 +12129,8 @@ s_axi_rdata - 255 - 224 + 4095 + 3584 @@ -12510,8 +12510,8 @@ m_axi_awaddr - 255 - 224 + 511 + 448 @@ -12666,8 +12666,8 @@ m_axi_wdata - 255 - 224 + 4095 + 3584 @@ -12678,8 +12678,8 @@ m_axi_wstrb - 31 - 28 + 511 + 448 @@ -12810,8 +12810,8 @@ m_axi_araddr - 255 - 224 + 511 + 448 @@ -12966,8 +12966,8 @@ m_axi_rdata - 255 - 224 + 4095 + 3584 @@ -13347,8 +13347,8 @@ s_axi_awaddr - 287 - 256 + 575 + 512 @@ -13491,8 +13491,8 @@ s_axi_wdata - 287 - 256 + 4607 + 4096 @@ -13503,8 +13503,8 @@ s_axi_wstrb - 35 - 32 + 575 + 512 @@ -13635,8 +13635,8 @@ s_axi_araddr - 287 - 256 + 575 + 512 @@ -13779,8 +13779,8 @@ s_axi_rdata - 287 - 256 + 4607 + 4096 @@ -14160,8 +14160,8 @@ m_axi_awaddr - 287 - 256 + 575 + 512 @@ -14316,8 +14316,8 @@ m_axi_wdata - 287 - 256 + 4607 + 4096 @@ -14328,8 +14328,8 @@ m_axi_wstrb - 35 - 32 + 575 + 512 @@ -14460,8 +14460,8 @@ m_axi_araddr - 287 - 256 + 575 + 512 @@ -14616,8 +14616,8 @@ m_axi_rdata - 287 - 256 + 4607 + 4096 @@ -14997,8 +14997,8 @@ s_axi_awaddr - 319 - 288 + 639 + 576 @@ -15141,8 +15141,8 @@ s_axi_wdata - 319 - 288 + 5119 + 4608 @@ -15153,8 +15153,8 @@ s_axi_wstrb - 39 - 36 + 639 + 576 @@ -15285,8 +15285,8 @@ s_axi_araddr - 319 - 288 + 639 + 576 @@ -15429,8 +15429,8 @@ s_axi_rdata - 319 - 288 + 5119 + 4608 @@ -15810,8 +15810,8 @@ m_axi_awaddr - 319 - 288 + 639 + 576 @@ -15966,8 +15966,8 @@ m_axi_wdata - 319 - 288 + 5119 + 4608 @@ -15978,8 +15978,8 @@ m_axi_wstrb - 39 - 36 + 639 + 576 @@ -16110,8 +16110,8 @@ m_axi_araddr - 319 - 288 + 639 + 576 @@ -16266,8 +16266,8 @@ m_axi_rdata - 319 - 288 + 5119 + 4608 @@ -16647,8 +16647,8 @@ s_axi_awaddr - 351 - 320 + 703 + 640 @@ -16791,8 +16791,8 @@ s_axi_wdata - 351 - 320 + 5631 + 5120 @@ -16803,8 +16803,8 @@ s_axi_wstrb - 43 - 40 + 703 + 640 @@ -16935,8 +16935,8 @@ s_axi_araddr - 351 - 320 + 703 + 640 @@ -17079,8 +17079,8 @@ s_axi_rdata - 351 - 320 + 5631 + 5120 @@ -17460,8 +17460,8 @@ m_axi_awaddr - 351 - 320 + 703 + 640 @@ -17616,8 +17616,8 @@ m_axi_wdata - 351 - 320 + 5631 + 5120 @@ -17628,8 +17628,8 @@ m_axi_wstrb - 43 - 40 + 703 + 640 @@ -17760,8 +17760,8 @@ m_axi_araddr - 351 - 320 + 703 + 640 @@ -17916,8 +17916,8 @@ m_axi_rdata - 351 - 320 + 5631 + 5120 @@ -18297,8 +18297,8 @@ s_axi_awaddr - 383 - 352 + 767 + 704 @@ -18441,8 +18441,8 @@ s_axi_wdata - 383 - 352 + 6143 + 5632 @@ -18453,8 +18453,8 @@ s_axi_wstrb - 47 - 44 + 767 + 704 @@ -18585,8 +18585,8 @@ s_axi_araddr - 383 - 352 + 767 + 704 @@ -18729,8 +18729,8 @@ s_axi_rdata - 383 - 352 + 6143 + 5632 @@ -19110,8 +19110,8 @@ m_axi_awaddr - 383 - 352 + 767 + 704 @@ -19266,8 +19266,8 @@ m_axi_wdata - 383 - 352 + 6143 + 5632 @@ -19278,8 +19278,8 @@ m_axi_wstrb - 47 - 44 + 767 + 704 @@ -19410,8 +19410,8 @@ m_axi_araddr - 383 - 352 + 767 + 704 @@ -19566,8 +19566,8 @@ m_axi_rdata - 383 - 352 + 6143 + 5632 @@ -19947,8 +19947,8 @@ s_axi_awaddr - 415 - 384 + 831 + 768 @@ -20091,8 +20091,8 @@ s_axi_wdata - 415 - 384 + 6655 + 6144 @@ -20103,8 +20103,8 @@ s_axi_wstrb - 51 - 48 + 831 + 768 @@ -20235,8 +20235,8 @@ s_axi_araddr - 415 - 384 + 831 + 768 @@ -20379,8 +20379,8 @@ s_axi_rdata - 415 - 384 + 6655 + 6144 @@ -20760,8 +20760,8 @@ m_axi_awaddr - 415 - 384 + 831 + 768 @@ -20916,8 +20916,8 @@ m_axi_wdata - 415 - 384 + 6655 + 6144 @@ -20928,8 +20928,8 @@ m_axi_wstrb - 51 - 48 + 831 + 768 @@ -21060,8 +21060,8 @@ m_axi_araddr - 415 - 384 + 831 + 768 @@ -21216,8 +21216,8 @@ m_axi_rdata - 415 - 384 + 6655 + 6144 @@ -21597,8 +21597,8 @@ s_axi_awaddr - 447 - 416 + 895 + 832 @@ -21741,8 +21741,8 @@ s_axi_wdata - 447 - 416 + 7167 + 6656 @@ -21753,8 +21753,8 @@ s_axi_wstrb - 55 - 52 + 895 + 832 @@ -21885,8 +21885,8 @@ s_axi_araddr - 447 - 416 + 895 + 832 @@ -22029,8 +22029,8 @@ s_axi_rdata - 447 - 416 + 7167 + 6656 @@ -22410,8 +22410,8 @@ m_axi_awaddr - 447 - 416 + 895 + 832 @@ -22566,8 +22566,8 @@ m_axi_wdata - 447 - 416 + 7167 + 6656 @@ -22578,8 +22578,8 @@ m_axi_wstrb - 55 - 52 + 895 + 832 @@ -22710,8 +22710,8 @@ m_axi_araddr - 447 - 416 + 895 + 832 @@ -22866,8 +22866,8 @@ m_axi_rdata - 447 - 416 + 7167 + 6656 @@ -23247,8 +23247,8 @@ s_axi_awaddr - 479 - 448 + 959 + 896 @@ -23391,8 +23391,8 @@ s_axi_wdata - 479 - 448 + 7679 + 7168 @@ -23403,8 +23403,8 @@ s_axi_wstrb - 59 - 56 + 959 + 896 @@ -23535,8 +23535,8 @@ s_axi_araddr - 479 - 448 + 959 + 896 @@ -23679,8 +23679,8 @@ s_axi_rdata - 479 - 448 + 7679 + 7168 @@ -24060,8 +24060,8 @@ m_axi_awaddr - 479 - 448 + 959 + 896 @@ -24216,8 +24216,8 @@ m_axi_wdata - 479 - 448 + 7679 + 7168 @@ -24228,8 +24228,8 @@ m_axi_wstrb - 59 - 56 + 959 + 896 @@ -24360,8 +24360,8 @@ m_axi_araddr - 479 - 448 + 959 + 896 @@ -24516,8 +24516,8 @@ m_axi_rdata - 479 - 448 + 7679 + 7168 @@ -24897,8 +24897,8 @@ s_axi_awaddr - 511 - 480 + 1023 + 960 @@ -25041,8 +25041,8 @@ s_axi_wdata - 511 - 480 + 8191 + 7680 @@ -25053,8 +25053,8 @@ s_axi_wstrb - 63 - 60 + 1023 + 960 @@ -25185,8 +25185,8 @@ s_axi_araddr - 511 - 480 + 1023 + 960 @@ -25329,8 +25329,8 @@ s_axi_rdata - 511 - 480 + 8191 + 7680 @@ -25710,8 +25710,8 @@ m_axi_awaddr - 511 - 480 + 1023 + 960 @@ -25866,8 +25866,8 @@ m_axi_wdata - 511 - 480 + 8191 + 7680 @@ -25878,8 +25878,8 @@ m_axi_wstrb - 63 - 60 + 1023 + 960 @@ -26010,8 +26010,8 @@ m_axi_araddr - 511 - 480 + 1023 + 960 @@ -26166,8 +26166,8 @@ m_axi_rdata - 511 - 480 + 8191 + 7680 @@ -26579,7 +26579,7 @@ in - 63 + 127 0 @@ -26589,7 +26589,7 @@ - 0x0000000000000000 + 0x00000000000000000000000000000000 @@ -26867,7 +26867,7 @@ in - 63 + 1023 0 @@ -26877,7 +26877,7 @@ - 0x0000000000000000 + 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -26886,7 +26886,7 @@ in - 7 + 127 0 @@ -26896,7 +26896,7 @@ - 0xFF + 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF @@ -27129,7 +27129,7 @@ in - 63 + 127 0 @@ -27139,7 +27139,7 @@ - 0x0000000000000000 + 0x00000000000000000000000000000000 @@ -27414,7 +27414,7 @@ out - 63 + 1023 0 @@ -27557,7 +27557,7 @@ out - 31 + 63 0 @@ -27838,7 +27838,7 @@ out - 31 + 511 0 @@ -27854,7 +27854,7 @@ out - 3 + 63 0 @@ -28094,7 +28094,7 @@ out - 31 + 63 0 @@ -28378,7 +28378,7 @@ in - 31 + 511 0 @@ -28388,7 +28388,7 @@ - 0x00000000 + 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -28525,11 +28525,11 @@ C_AXI_ADDR_WIDTH - 32 + 64 C_AXI_DATA_WIDTH - 32 + 512 C_AXI_PROTOCOL @@ -28541,11 +28541,11 @@ C_M_AXI_BASE_ADDR - 0xffffffffffffffff + 0x0000000000000000 C_M_AXI_ADDR_WIDTH - 0x00000000 + 0x00000021 C_S_AXI_BASE_ID @@ -28597,19 +28597,19 @@ C_S_AXI_WRITE_ACCEPTANCE - 0x0000000200000002 + 0x0000000200000008 C_S_AXI_READ_ACCEPTANCE - 0x0000000200000002 + 0x0000000200000008 C_M_AXI_WRITE_ISSUING - 0x00000004 + 0x00000008 C_M_AXI_READ_ISSUING - 0x00000004 + 0x00000008 C_S_AXI_ARB_PRIORITY @@ -28735,7 +28735,7 @@ ADDR_WIDTH Address Width - 32 + 64 @@ -28771,7 +28771,7 @@ DATA_WIDTH Data Width - 32 + 512 @@ -35215,7 +35215,7 @@ S00_WRITE_ACCEPTANCE My S00_WRITE_ACCEPTANCE - 2 + 8 @@ -35407,7 +35407,7 @@ S00_READ_ACCEPTANCE My S00_READ_ACCEPTANCE - 2 + 8 @@ -35599,7 +35599,7 @@ M00_WRITE_ISSUING My M00_WRITE_ISSUING - 4 + 8 @@ -35791,7 +35791,7 @@ M00_READ_ISSUING My M00_READ_ISSUING - 4 + 8 @@ -36943,7 +36943,7 @@ M00_A00_BASE_ADDR My M00_A00_BASE_ADDR - 0xffffffffffffffff + 0x0000000000000000 @@ -40015,7 +40015,7 @@ M00_A00_ADDR_WIDTH My M00_A00_ADDR_WIDTH - 0 + 33 @@ -43086,7 +43086,7 @@ Component_Name - pcie_ddr_xbar_0 + pcie_ddr_xbar_1 @@ -43096,37 +43096,37 @@ - - - - + + + + - + - + - - + + - + - - - + + + - + - + - + @@ -43160,44 +43160,43 @@ - - - - - - - - + + + + + + + - + - + - + - - - - - - + + + + + + - + - - - - - - - - + + + + + + + + @@ -43207,29 +43206,29 @@ - + - + - - - + + + - - + + - - - - - - - - - - - + + + + + + + + + + + @@ -43260,11 +43259,11 @@ - - - - - + + + + + @@ -43293,7 +43292,7 @@ - + @@ -44286,14 +44285,14 @@ - - - - - - - - + + + + + + + + @@ -44337,7 +44336,7 @@ - + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xci b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xci index c8ae901..8a80ea7 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xci +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xci @@ -64,7 +64,7 @@ 0.000 - + pcie_ddr_util_ds_buf_0_0_IBUF_OUT 100000000 0 0.000 @@ -102,7 +102,7 @@ 0 0 0 - + pcie_ddr_xdma_0_0_axi_aclk 128 250000000 1 @@ -2010,7 +2010,7 @@ - + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xml index 4855082..fb1c38b 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xml +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xml @@ -41,7 +41,7 @@ CLK_DOMAIN - + pcie_ddr_util_ds_buf_0_0_IBUF_OUT none @@ -1590,7 +1590,7 @@ CLK_DOMAIN - + pcie_ddr_xdma_0_0_axi_aclk none @@ -59373,7 +59373,7 @@ - + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr.bd b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr.bd index 0cb83a9..c1277cd 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr.bd +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr.bd @@ -1,11 +1,12 @@ { "design": { "design_info": { - "boundary_crc": "0x0", + "boundary_crc": "0x2D40D29FDD4A3A57", "device": "xc7k325tffg900-2", "name": "pcie_ddr", "synth_flow_mode": "Hierarchical", - "tool_version": "2019.2" + "tool_version": "2019.2", + "validated": "true" }, "design_tree": { "xdma_0": "", @@ -14,26 +15,96 @@ "clk_wiz_0": "", "axi_interconnect_0": { "xbar": "", - "s00_couplers": {}, - "s01_couplers": {}, - "m00_couplers": {} + "s00_couplers": { + "auto_us": "", + "auto_cc": "" + }, + "s01_couplers": { + "auto_us": "", + "auto_cc": "" + }, + "m00_couplers": { + "auto_cc": "" + }, + "s01_mmu": "" }, + "rst_clk_wiz_0_200M": "", "rst_mig_7series_0_100M": "" }, "interface_ports": { - "CLK_IN_D_0": { + "pcie_clk": { "mode": "Slave", - "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0" + "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + } + } }, - "DDR3_0": { + "ddr": { "mode": "Master", - "vlnv": "xilinx.com:interface:ddrx_rtl:1.0" + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + } + } }, - "pcie_mgt_0": { + "pcie_mgt": { "mode": "Master", "vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0" }, - "S01_AXI_0": { + "ddr_axi": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0", "parameters": { @@ -43,6 +114,9 @@ "PROTOCOL": { "value": "AXI4" }, + "FREQ_HZ": { + "value": "200000000" + }, "ID_WIDTH": { "value": "1" }, @@ -106,6 +180,14 @@ "MAX_BURST_LENGTH": { "value": "256" }, + "PHASE": { + "value": "0.000", + "value_src": "default" + }, + "CLK_DOMAIN": { + "value": "pcie_ddr_clk_in1_0", + "value_src": "default" + }, "NUM_READ_THREADS": { "value": "1" }, @@ -117,46 +199,82 @@ }, "WUSER_BITS_PER_BYTE": { "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" } } } }, "ports": { - "clk_in1_0": { + "sys_clk": { "type": "clk", "direction": "I", "parameters": { + "ASSOCIATED_BUSIF": { + "value": "ddr_axi", + "value_src": "default" + }, + "ASSOCIATED_RESET": { + "value": "sys_rstn", + "value_src": "default" + }, + "CLK_DOMAIN": { + "value": "pcie_ddr_clk_in1_0", + "value_src": "default" + }, "FREQ_HZ": { "value": "200000000" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" } } }, - "resetn_0": { + "sys_rstn": { "type": "rst", - "direction": "I" + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } }, "sys_rst_n_0": { "type": "rst", - "direction": "I" + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } }, - "init_calib_complete_0": { + "init_calib_complete": { "direction": "O" }, - "user_lnk_up_0": { + "pcie_user_lnk_up": { "direction": "O" }, - "msi_enable_0": { + "pcie_msi_enable": { "direction": "O" }, - "S01_ACLK_0": { - "type": "clk", - "direction": "I" - }, - "S01_ARESETN_0": { - "type": "rst", - "direction": "I" - }, - "usr_irq_req_0": { + "pcie_usr_irq_req": { "direction": "I", "left": "0", "right": "0" @@ -224,14 +342,11 @@ "BOARD_MIG_PARAM": { "value": "Custom" }, - "MIG_DONT_TOUCH_PARAM": { - "value": "Custom" - }, "RESET_BOARD_INTERFACE": { "value": "Custom" }, "XML_INPUT_FILE": { - "value": "mig_a.prj" + "value": "mig_b.prj" } } }, @@ -285,7 +400,7 @@ }, "axi_interconnect_0": { "vlnv": "xilinx.com:ip:axi_interconnect:2.1", - "xci_name": "pcie_ddr_axi_interconnect_0_0", + "xci_name": "pcie_ddr_axi_interconnect_0_1", "parameters": { "NUM_MI": { "value": "1" @@ -374,7 +489,7 @@ "components": { "xbar": { "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "pcie_ddr_xbar_0", + "xci_name": "pcie_ddr_xbar_1", "parameters": { "NUM_MI": { "value": "1" @@ -432,11 +547,69 @@ "direction": "I" } }, + "components": { + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "pcie_ddr_auto_us_0", + "parameters": { + "MI_DATA_WIDTH": { + "value": "512" + }, + "SI_DATA_WIDTH": { + "value": "128" + } + } + }, + "auto_cc": { + "vlnv": "xilinx.com:ip:axi_clock_converter:2.1", + "xci_name": "pcie_ddr_auto_cc_2" + } + }, "interface_nets": { - "s00_couplers_to_s00_couplers": { + "s00_couplers_to_auto_us": { "interface_ports": [ "S_AXI", - "M_AXI" + "auto_us/S_AXI" + ] + }, + "auto_cc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_cc/M_AXI" + ] + }, + "auto_us_to_auto_cc": { + "interface_ports": [ + "auto_us/M_AXI", + "auto_cc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk", + "auto_cc/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn", + "auto_cc/s_axi_aresetn" + ] + }, + "M_ACLK_1": { + "ports": [ + "M_ACLK", + "auto_cc/m_axi_aclk" + ] + }, + "M_ARESETN_1": { + "ports": [ + "M_ARESETN", + "auto_cc/m_axi_aresetn" ] } } @@ -486,11 +659,69 @@ "direction": "I" } }, + "components": { + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "pcie_ddr_auto_us_1", + "parameters": { + "MI_DATA_WIDTH": { + "value": "512" + }, + "SI_DATA_WIDTH": { + "value": "32" + } + } + }, + "auto_cc": { + "vlnv": "xilinx.com:ip:axi_clock_converter:2.1", + "xci_name": "pcie_ddr_auto_cc_3" + } + }, "interface_nets": { - "s01_couplers_to_s01_couplers": { + "s01_couplers_to_auto_us": { "interface_ports": [ "S_AXI", - "M_AXI" + "auto_us/S_AXI" + ] + }, + "auto_cc_to_s01_couplers": { + "interface_ports": [ + "M_AXI", + "auto_cc/M_AXI" + ] + }, + "auto_us_to_auto_cc": { + "interface_ports": [ + "auto_us/M_AXI", + "auto_cc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk", + "auto_cc/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn", + "auto_cc/s_axi_aresetn" + ] + }, + "M_ACLK_1": { + "ports": [ + "M_ACLK", + "auto_cc/m_axi_aclk" + ] + }, + "M_ARESETN_1": { + "ports": [ + "M_ARESETN", + "auto_cc/m_axi_aresetn" ] } } @@ -540,17 +771,65 @@ "direction": "I" } }, + "components": { + "auto_cc": { + "vlnv": "xilinx.com:ip:axi_clock_converter:2.1", + "xci_name": "pcie_ddr_auto_cc_1" + } + }, "interface_nets": { - "m00_couplers_to_m00_couplers": { + "auto_cc_to_m00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_cc/M_AXI" + ] + }, + "m00_couplers_to_auto_cc": { "interface_ports": [ "S_AXI", - "M_AXI" + "auto_cc/S_AXI" + ] + } + }, + "nets": { + "M_ACLK_1": { + "ports": [ + "M_ACLK", + "auto_cc/m_axi_aclk" + ] + }, + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_cc/s_axi_aclk" + ] + }, + "M_ARESETN_1": { + "ports": [ + "M_ARESETN", + "auto_cc/m_axi_aresetn" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_cc/s_axi_aresetn" ] } } + }, + "s01_mmu": { + "vlnv": "xilinx.com:ip:axi_mmu:2.1", + "xci_name": "pcie_ddr_s01_mmu_1" } }, "interface_nets": { + "s01_couplers_to_xbar": { + "interface_ports": [ + "s01_couplers/M_AXI", + "xbar/S01_AXI" + ] + }, "m00_couplers_to_axi_interconnect_0": { "interface_ports": [ "M00_AXI", @@ -563,6 +842,18 @@ "m00_couplers/S_AXI" ] }, + "s01_mmu_M_AXI": { + "interface_ports": [ + "s01_mmu/M_AXI", + "s01_couplers/S_AXI" + ] + }, + "S01_AXI_1": { + "interface_ports": [ + "S01_AXI", + "s01_mmu/S_AXI" + ] + }, "axi_interconnect_0_to_s00_couplers": { "interface_ports": [ "S00_AXI", @@ -574,18 +865,6 @@ "s00_couplers/M_AXI", "xbar/S00_AXI" ] - }, - "s01_couplers_to_xbar": { - "interface_ports": [ - "s01_couplers/M_AXI", - "xbar/S01_AXI" - ] - }, - "axi_interconnect_0_to_s01_couplers": { - "interface_ports": [ - "S01_AXI", - "s01_couplers/S_AXI" - ] } }, "nets": { @@ -593,11 +872,8 @@ "ports": [ "ACLK", "xbar/aclk", - "s00_couplers/S_ACLK", - "s01_couplers/S_ACLK", "s00_couplers/M_ACLK", "s01_couplers/M_ACLK", - "m00_couplers/M_ACLK", "m00_couplers/S_ACLK" ] }, @@ -605,38 +881,83 @@ "ports": [ "ARESETN", "xbar/aresetn", - "s00_couplers/S_ARESETN", - "s01_couplers/S_ARESETN", "s00_couplers/M_ARESETN", "s01_couplers/M_ARESETN", - "m00_couplers/M_ARESETN", "m00_couplers/S_ARESETN" ] + }, + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "S01_ACLK_1": { + "ports": [ + "S01_ACLK", + "s01_couplers/S_ACLK", + "s01_mmu/aclk" + ] + }, + "S01_ARESETN_1": { + "ports": [ + "S01_ARESETN", + "s01_couplers/S_ARESETN", + "s01_mmu/aresetn" + ] + }, + "M00_ACLK_1": { + "ports": [ + "M00_ACLK", + "m00_couplers/M_ACLK" + ] + }, + "M00_ARESETN_1": { + "ports": [ + "M00_ARESETN", + "m00_couplers/M_ARESETN" + ] } } }, + "rst_clk_wiz_0_200M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "pcie_ddr_rst_clk_wiz_0_200M_0" + }, "rst_mig_7series_0_100M": { "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", - "xci_name": "pcie_ddr_rst_mig_7series_0_100M_2" + "xci_name": "pcie_ddr_rst_mig_7series_0_100M_4" } }, "interface_nets": { + "mig_7series_0_DDR3": { + "interface_ports": [ + "ddr", + "mig_7series_0/DDR3" + ] + }, "xdma_0_pcie_mgt": { "interface_ports": [ - "pcie_mgt_0", + "pcie_mgt", "xdma_0/pcie_mgt" ] }, "CLK_IN_D_0_1": { "interface_ports": [ - "CLK_IN_D_0", + "pcie_clk", "util_ds_buf_0/CLK_IN_D" ] }, - "mig_7series_0_DDR3": { + "S01_AXI_0_1": { "interface_ports": [ - "DDR3_0", - "mig_7series_0/DDR3" + "ddr_axi", + "axi_interconnect_0/S01_AXI" ] }, "xdma_0_M_AXI": { @@ -645,12 +966,6 @@ "axi_interconnect_0/S00_AXI" ] }, - "S01_AXI_0_1": { - "interface_ports": [ - "S01_AXI_0", - "axi_interconnect_0/S01_AXI" - ] - }, "axi_interconnect_0_M00_AXI": { "interface_ports": [ "axi_interconnect_0/M00_AXI", @@ -661,21 +976,25 @@ "nets": { "clk_in1_0_1": { "ports": [ - "clk_in1_0", - "clk_wiz_0/clk_in1" + "sys_clk", + "clk_wiz_0/clk_in1", + "axi_interconnect_0/S01_ACLK" ] }, "resetn_0_1": { "ports": [ - "resetn_0", - "clk_wiz_0/resetn" + "sys_rstn", + "clk_wiz_0/resetn", + "rst_clk_wiz_0_200M/ext_reset_in", + "axi_interconnect_0/S01_ARESETN" ] }, "clk_wiz_0_clk_out1": { "ports": [ "clk_wiz_0/clk_out1", "mig_7series_0/sys_clk_i", - "axi_interconnect_0/ACLK" + "axi_interconnect_0/ACLK", + "rst_clk_wiz_0_200M/slowest_sync_clk" ] }, "util_ds_buf_0_IBUF_OUT": { @@ -693,25 +1012,38 @@ "clk_wiz_0_locked": { "ports": [ "clk_wiz_0/locked", - "mig_7series_0/sys_rst" + "mig_7series_0/sys_rst", + "rst_clk_wiz_0_200M/dcm_locked" ] }, "mig_7series_0_init_calib_complete": { "ports": [ "mig_7series_0/init_calib_complete", - "init_calib_complete_0" + "init_calib_complete" ] }, "xdma_0_user_lnk_up": { "ports": [ "xdma_0/user_lnk_up", - "user_lnk_up_0" + "pcie_user_lnk_up" ] }, "xdma_0_msi_enable": { "ports": [ "xdma_0/msi_enable", - "msi_enable_0" + "pcie_msi_enable" + ] + }, + "usr_irq_req_0_1": { + "ports": [ + "pcie_usr_irq_req", + "xdma_0/usr_irq_req" + ] + }, + "rst_clk_wiz_0_200M_peripheral_aresetn": { + "ports": [ + "rst_clk_wiz_0_200M/peripheral_aresetn", + "axi_interconnect_0/ARESETN" ] }, "xdma_0_axi_aclk": { @@ -751,32 +1083,21 @@ "mig_7series_0/aresetn", "axi_interconnect_0/M00_ARESETN" ] - }, - "S01_ACLK_0_1": { - "ports": [ - "S01_ACLK_0", - "axi_interconnect_0/S01_ACLK" - ] - }, - "S01_ARESETN_0_1": { - "ports": [ - "S01_ARESETN_0", - "axi_interconnect_0/S01_ARESETN" - ] - }, - "usr_irq_req_0_1": { - "ports": [ - "usr_irq_req_0", - "xdma_0/usr_irq_req" - ] } }, "addressing": { "/": { "address_spaces": { - "S01_AXI_0": { + "ddr_axi": { "range": "4G", - "width": "32" + "width": "32", + "segments": { + "SEG_mig_7series_0_memaddr": { + "address_block": "/mig_7series_0/memmap/memaddr", + "offset": "0x00000000", + "range": "4G" + } + } } } }, diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr.bxml b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr.bxml index f1f7b27..d8b7c6d 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr.bxml +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + @@ -39,7 +39,7 @@ - + @@ -47,7 +47,55 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -55,7 +103,15 @@ - + + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr_ooc.xdc b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr_ooc.xdc new file mode 100644 index 0000000..d0eae90 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/pcie_ddr_ooc.xdc @@ -0,0 +1,12 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ +create_clock -name sys_clk -period 5 [get_ports sys_clk] +create_clock -name pcie_clk_clk_p -period 10 [get_ports pcie_clk_clk_p] + +################################################################################ \ No newline at end of file diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/sim/pcie_ddr.v b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/sim/pcie_ddr.v new file mode 100644 index 0000000..f9bc3ac --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/sim/pcie_ddr.v @@ -0,0 +1,2977 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +//Date : Tue Mar 18 13:48:36 2025 +//Host : BHKLaptop running 64-bit major release (build 9200) +//Command : generate_target pcie_ddr.bd +//Design : pcie_ddr +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module m00_couplers_imp_1FLA7NN + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arid, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awid, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rid, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arregion, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awregion, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [32:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [0:0]M_AXI_arid; + output [7:0]M_AXI_arlen; + output [0:0]M_AXI_arlock; + output [2:0]M_AXI_arprot; + output [3:0]M_AXI_arqos; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [32:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [0:0]M_AXI_awid; + output [7:0]M_AXI_awlen; + output [0:0]M_AXI_awlock; + output [2:0]M_AXI_awprot; + output [3:0]M_AXI_awqos; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + input [0:0]M_AXI_bid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [511:0]M_AXI_rdata; + input [0:0]M_AXI_rid; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [511:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [63:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [63:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [0:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + input [3:0]S_AXI_arqos; + output S_AXI_arready; + input [3:0]S_AXI_arregion; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [63:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [0:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + input [3:0]S_AXI_awqos; + output S_AXI_awready; + input [3:0]S_AXI_awregion; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [0:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [511:0]S_AXI_rdata; + output [0:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [511:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [63:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire M_ACLK_1; + wire M_ARESETN_1; + wire S_ACLK_1; + wire S_ARESETN_1; + wire [32:0]auto_cc_to_m00_couplers_ARADDR; + wire [1:0]auto_cc_to_m00_couplers_ARBURST; + wire [3:0]auto_cc_to_m00_couplers_ARCACHE; + wire [0:0]auto_cc_to_m00_couplers_ARID; + wire [7:0]auto_cc_to_m00_couplers_ARLEN; + wire [0:0]auto_cc_to_m00_couplers_ARLOCK; + wire [2:0]auto_cc_to_m00_couplers_ARPROT; + wire [3:0]auto_cc_to_m00_couplers_ARQOS; + wire auto_cc_to_m00_couplers_ARREADY; + wire [2:0]auto_cc_to_m00_couplers_ARSIZE; + wire auto_cc_to_m00_couplers_ARVALID; + wire [32:0]auto_cc_to_m00_couplers_AWADDR; + wire [1:0]auto_cc_to_m00_couplers_AWBURST; + wire [3:0]auto_cc_to_m00_couplers_AWCACHE; + wire [0:0]auto_cc_to_m00_couplers_AWID; + wire [7:0]auto_cc_to_m00_couplers_AWLEN; + wire [0:0]auto_cc_to_m00_couplers_AWLOCK; + wire [2:0]auto_cc_to_m00_couplers_AWPROT; + wire [3:0]auto_cc_to_m00_couplers_AWQOS; + wire auto_cc_to_m00_couplers_AWREADY; + wire [2:0]auto_cc_to_m00_couplers_AWSIZE; + wire auto_cc_to_m00_couplers_AWVALID; + wire [0:0]auto_cc_to_m00_couplers_BID; + wire auto_cc_to_m00_couplers_BREADY; + wire [1:0]auto_cc_to_m00_couplers_BRESP; + wire auto_cc_to_m00_couplers_BVALID; + wire [511:0]auto_cc_to_m00_couplers_RDATA; + wire [0:0]auto_cc_to_m00_couplers_RID; + wire auto_cc_to_m00_couplers_RLAST; + wire auto_cc_to_m00_couplers_RREADY; + wire [1:0]auto_cc_to_m00_couplers_RRESP; + wire auto_cc_to_m00_couplers_RVALID; + wire [511:0]auto_cc_to_m00_couplers_WDATA; + wire auto_cc_to_m00_couplers_WLAST; + wire auto_cc_to_m00_couplers_WREADY; + wire [63:0]auto_cc_to_m00_couplers_WSTRB; + wire auto_cc_to_m00_couplers_WVALID; + wire [63:0]m00_couplers_to_auto_cc_ARADDR; + wire [1:0]m00_couplers_to_auto_cc_ARBURST; + wire [3:0]m00_couplers_to_auto_cc_ARCACHE; + wire [0:0]m00_couplers_to_auto_cc_ARID; + wire [7:0]m00_couplers_to_auto_cc_ARLEN; + wire [0:0]m00_couplers_to_auto_cc_ARLOCK; + wire [2:0]m00_couplers_to_auto_cc_ARPROT; + wire [3:0]m00_couplers_to_auto_cc_ARQOS; + wire m00_couplers_to_auto_cc_ARREADY; + wire [3:0]m00_couplers_to_auto_cc_ARREGION; + wire [2:0]m00_couplers_to_auto_cc_ARSIZE; + wire m00_couplers_to_auto_cc_ARVALID; + wire [63:0]m00_couplers_to_auto_cc_AWADDR; + wire [1:0]m00_couplers_to_auto_cc_AWBURST; + wire [3:0]m00_couplers_to_auto_cc_AWCACHE; + wire [0:0]m00_couplers_to_auto_cc_AWID; + wire [7:0]m00_couplers_to_auto_cc_AWLEN; + wire [0:0]m00_couplers_to_auto_cc_AWLOCK; + wire [2:0]m00_couplers_to_auto_cc_AWPROT; + wire [3:0]m00_couplers_to_auto_cc_AWQOS; + wire m00_couplers_to_auto_cc_AWREADY; + wire [3:0]m00_couplers_to_auto_cc_AWREGION; + wire [2:0]m00_couplers_to_auto_cc_AWSIZE; + wire m00_couplers_to_auto_cc_AWVALID; + wire [0:0]m00_couplers_to_auto_cc_BID; + wire m00_couplers_to_auto_cc_BREADY; + wire [1:0]m00_couplers_to_auto_cc_BRESP; + wire m00_couplers_to_auto_cc_BVALID; + wire [511:0]m00_couplers_to_auto_cc_RDATA; + wire [0:0]m00_couplers_to_auto_cc_RID; + wire m00_couplers_to_auto_cc_RLAST; + wire m00_couplers_to_auto_cc_RREADY; + wire [1:0]m00_couplers_to_auto_cc_RRESP; + wire m00_couplers_to_auto_cc_RVALID; + wire [511:0]m00_couplers_to_auto_cc_WDATA; + wire m00_couplers_to_auto_cc_WLAST; + wire m00_couplers_to_auto_cc_WREADY; + wire [63:0]m00_couplers_to_auto_cc_WSTRB; + wire m00_couplers_to_auto_cc_WVALID; + + assign M_ACLK_1 = M_ACLK; + assign M_ARESETN_1 = M_ARESETN; + assign M_AXI_araddr[32:0] = auto_cc_to_m00_couplers_ARADDR; + assign M_AXI_arburst[1:0] = auto_cc_to_m00_couplers_ARBURST; + assign M_AXI_arcache[3:0] = auto_cc_to_m00_couplers_ARCACHE; + assign M_AXI_arid[0] = auto_cc_to_m00_couplers_ARID; + assign M_AXI_arlen[7:0] = auto_cc_to_m00_couplers_ARLEN; + assign M_AXI_arlock[0] = auto_cc_to_m00_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = auto_cc_to_m00_couplers_ARPROT; + assign M_AXI_arqos[3:0] = auto_cc_to_m00_couplers_ARQOS; + assign M_AXI_arsize[2:0] = auto_cc_to_m00_couplers_ARSIZE; + assign M_AXI_arvalid = auto_cc_to_m00_couplers_ARVALID; + assign M_AXI_awaddr[32:0] = auto_cc_to_m00_couplers_AWADDR; + assign M_AXI_awburst[1:0] = auto_cc_to_m00_couplers_AWBURST; + assign M_AXI_awcache[3:0] = auto_cc_to_m00_couplers_AWCACHE; + assign M_AXI_awid[0] = auto_cc_to_m00_couplers_AWID; + assign M_AXI_awlen[7:0] = auto_cc_to_m00_couplers_AWLEN; + assign M_AXI_awlock[0] = auto_cc_to_m00_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = auto_cc_to_m00_couplers_AWPROT; + assign M_AXI_awqos[3:0] = auto_cc_to_m00_couplers_AWQOS; + assign M_AXI_awsize[2:0] = auto_cc_to_m00_couplers_AWSIZE; + assign M_AXI_awvalid = auto_cc_to_m00_couplers_AWVALID; + assign M_AXI_bready = auto_cc_to_m00_couplers_BREADY; + assign M_AXI_rready = auto_cc_to_m00_couplers_RREADY; + assign M_AXI_wdata[511:0] = auto_cc_to_m00_couplers_WDATA; + assign M_AXI_wlast = auto_cc_to_m00_couplers_WLAST; + assign M_AXI_wstrb[63:0] = auto_cc_to_m00_couplers_WSTRB; + assign M_AXI_wvalid = auto_cc_to_m00_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = m00_couplers_to_auto_cc_ARREADY; + assign S_AXI_awready = m00_couplers_to_auto_cc_AWREADY; + assign S_AXI_bid[0] = m00_couplers_to_auto_cc_BID; + assign S_AXI_bresp[1:0] = m00_couplers_to_auto_cc_BRESP; + assign S_AXI_bvalid = m00_couplers_to_auto_cc_BVALID; + assign S_AXI_rdata[511:0] = m00_couplers_to_auto_cc_RDATA; + assign S_AXI_rid[0] = m00_couplers_to_auto_cc_RID; + assign S_AXI_rlast = m00_couplers_to_auto_cc_RLAST; + assign S_AXI_rresp[1:0] = m00_couplers_to_auto_cc_RRESP; + assign S_AXI_rvalid = m00_couplers_to_auto_cc_RVALID; + assign S_AXI_wready = m00_couplers_to_auto_cc_WREADY; + assign auto_cc_to_m00_couplers_ARREADY = M_AXI_arready; + assign auto_cc_to_m00_couplers_AWREADY = M_AXI_awready; + assign auto_cc_to_m00_couplers_BID = M_AXI_bid[0]; + assign auto_cc_to_m00_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_cc_to_m00_couplers_BVALID = M_AXI_bvalid; + assign auto_cc_to_m00_couplers_RDATA = M_AXI_rdata[511:0]; + assign auto_cc_to_m00_couplers_RID = M_AXI_rid[0]; + assign auto_cc_to_m00_couplers_RLAST = M_AXI_rlast; + assign auto_cc_to_m00_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_cc_to_m00_couplers_RVALID = M_AXI_rvalid; + assign auto_cc_to_m00_couplers_WREADY = M_AXI_wready; + assign m00_couplers_to_auto_cc_ARADDR = S_AXI_araddr[63:0]; + assign m00_couplers_to_auto_cc_ARBURST = S_AXI_arburst[1:0]; + assign m00_couplers_to_auto_cc_ARCACHE = S_AXI_arcache[3:0]; + assign m00_couplers_to_auto_cc_ARID = S_AXI_arid[0]; + assign m00_couplers_to_auto_cc_ARLEN = S_AXI_arlen[7:0]; + assign m00_couplers_to_auto_cc_ARLOCK = S_AXI_arlock[0]; + assign m00_couplers_to_auto_cc_ARPROT = S_AXI_arprot[2:0]; + assign m00_couplers_to_auto_cc_ARQOS = S_AXI_arqos[3:0]; + assign m00_couplers_to_auto_cc_ARREGION = S_AXI_arregion[3:0]; + assign m00_couplers_to_auto_cc_ARSIZE = S_AXI_arsize[2:0]; + assign m00_couplers_to_auto_cc_ARVALID = S_AXI_arvalid; + assign m00_couplers_to_auto_cc_AWADDR = S_AXI_awaddr[63:0]; + assign m00_couplers_to_auto_cc_AWBURST = S_AXI_awburst[1:0]; + assign m00_couplers_to_auto_cc_AWCACHE = S_AXI_awcache[3:0]; + assign m00_couplers_to_auto_cc_AWID = S_AXI_awid[0]; + assign m00_couplers_to_auto_cc_AWLEN = S_AXI_awlen[7:0]; + assign m00_couplers_to_auto_cc_AWLOCK = S_AXI_awlock[0]; + assign m00_couplers_to_auto_cc_AWPROT = S_AXI_awprot[2:0]; + assign m00_couplers_to_auto_cc_AWQOS = S_AXI_awqos[3:0]; + assign m00_couplers_to_auto_cc_AWREGION = S_AXI_awregion[3:0]; + assign m00_couplers_to_auto_cc_AWSIZE = S_AXI_awsize[2:0]; + assign m00_couplers_to_auto_cc_AWVALID = S_AXI_awvalid; + assign m00_couplers_to_auto_cc_BREADY = S_AXI_bready; + assign m00_couplers_to_auto_cc_RREADY = S_AXI_rready; + assign m00_couplers_to_auto_cc_WDATA = S_AXI_wdata[511:0]; + assign m00_couplers_to_auto_cc_WLAST = S_AXI_wlast; + assign m00_couplers_to_auto_cc_WSTRB = S_AXI_wstrb[63:0]; + assign m00_couplers_to_auto_cc_WVALID = S_AXI_wvalid; + pcie_ddr_auto_cc_1 auto_cc + (.m_axi_aclk(M_ACLK_1), + .m_axi_araddr(auto_cc_to_m00_couplers_ARADDR), + .m_axi_arburst(auto_cc_to_m00_couplers_ARBURST), + .m_axi_arcache(auto_cc_to_m00_couplers_ARCACHE), + .m_axi_aresetn(M_ARESETN_1), + .m_axi_arid(auto_cc_to_m00_couplers_ARID), + .m_axi_arlen(auto_cc_to_m00_couplers_ARLEN), + .m_axi_arlock(auto_cc_to_m00_couplers_ARLOCK), + .m_axi_arprot(auto_cc_to_m00_couplers_ARPROT), + .m_axi_arqos(auto_cc_to_m00_couplers_ARQOS), + .m_axi_arready(auto_cc_to_m00_couplers_ARREADY), + .m_axi_arsize(auto_cc_to_m00_couplers_ARSIZE), + .m_axi_arvalid(auto_cc_to_m00_couplers_ARVALID), + .m_axi_awaddr(auto_cc_to_m00_couplers_AWADDR), + .m_axi_awburst(auto_cc_to_m00_couplers_AWBURST), + .m_axi_awcache(auto_cc_to_m00_couplers_AWCACHE), + .m_axi_awid(auto_cc_to_m00_couplers_AWID), + .m_axi_awlen(auto_cc_to_m00_couplers_AWLEN), + .m_axi_awlock(auto_cc_to_m00_couplers_AWLOCK), + .m_axi_awprot(auto_cc_to_m00_couplers_AWPROT), + .m_axi_awqos(auto_cc_to_m00_couplers_AWQOS), + .m_axi_awready(auto_cc_to_m00_couplers_AWREADY), + .m_axi_awsize(auto_cc_to_m00_couplers_AWSIZE), + .m_axi_awvalid(auto_cc_to_m00_couplers_AWVALID), + .m_axi_bid(auto_cc_to_m00_couplers_BID), + .m_axi_bready(auto_cc_to_m00_couplers_BREADY), + .m_axi_bresp(auto_cc_to_m00_couplers_BRESP), + .m_axi_bvalid(auto_cc_to_m00_couplers_BVALID), + .m_axi_rdata(auto_cc_to_m00_couplers_RDATA), + .m_axi_rid(auto_cc_to_m00_couplers_RID), + .m_axi_rlast(auto_cc_to_m00_couplers_RLAST), + .m_axi_rready(auto_cc_to_m00_couplers_RREADY), + .m_axi_rresp(auto_cc_to_m00_couplers_RRESP), + .m_axi_rvalid(auto_cc_to_m00_couplers_RVALID), + .m_axi_wdata(auto_cc_to_m00_couplers_WDATA), + .m_axi_wlast(auto_cc_to_m00_couplers_WLAST), + .m_axi_wready(auto_cc_to_m00_couplers_WREADY), + .m_axi_wstrb(auto_cc_to_m00_couplers_WSTRB), + .m_axi_wvalid(auto_cc_to_m00_couplers_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(m00_couplers_to_auto_cc_ARADDR[32:0]), + .s_axi_arburst(m00_couplers_to_auto_cc_ARBURST), + .s_axi_arcache(m00_couplers_to_auto_cc_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arid(m00_couplers_to_auto_cc_ARID), + .s_axi_arlen(m00_couplers_to_auto_cc_ARLEN), + .s_axi_arlock(m00_couplers_to_auto_cc_ARLOCK), + .s_axi_arprot(m00_couplers_to_auto_cc_ARPROT), + .s_axi_arqos(m00_couplers_to_auto_cc_ARQOS), + .s_axi_arready(m00_couplers_to_auto_cc_ARREADY), + .s_axi_arregion(m00_couplers_to_auto_cc_ARREGION), + .s_axi_arsize(m00_couplers_to_auto_cc_ARSIZE), + .s_axi_arvalid(m00_couplers_to_auto_cc_ARVALID), + .s_axi_awaddr(m00_couplers_to_auto_cc_AWADDR[32:0]), + .s_axi_awburst(m00_couplers_to_auto_cc_AWBURST), + .s_axi_awcache(m00_couplers_to_auto_cc_AWCACHE), + .s_axi_awid(m00_couplers_to_auto_cc_AWID), + .s_axi_awlen(m00_couplers_to_auto_cc_AWLEN), + .s_axi_awlock(m00_couplers_to_auto_cc_AWLOCK), + .s_axi_awprot(m00_couplers_to_auto_cc_AWPROT), + .s_axi_awqos(m00_couplers_to_auto_cc_AWQOS), + .s_axi_awready(m00_couplers_to_auto_cc_AWREADY), + .s_axi_awregion(m00_couplers_to_auto_cc_AWREGION), + .s_axi_awsize(m00_couplers_to_auto_cc_AWSIZE), + .s_axi_awvalid(m00_couplers_to_auto_cc_AWVALID), + .s_axi_bid(m00_couplers_to_auto_cc_BID), + .s_axi_bready(m00_couplers_to_auto_cc_BREADY), + .s_axi_bresp(m00_couplers_to_auto_cc_BRESP), + .s_axi_bvalid(m00_couplers_to_auto_cc_BVALID), + .s_axi_rdata(m00_couplers_to_auto_cc_RDATA), + .s_axi_rid(m00_couplers_to_auto_cc_RID), + .s_axi_rlast(m00_couplers_to_auto_cc_RLAST), + .s_axi_rready(m00_couplers_to_auto_cc_RREADY), + .s_axi_rresp(m00_couplers_to_auto_cc_RRESP), + .s_axi_rvalid(m00_couplers_to_auto_cc_RVALID), + .s_axi_wdata(m00_couplers_to_auto_cc_WDATA), + .s_axi_wlast(m00_couplers_to_auto_cc_WLAST), + .s_axi_wready(m00_couplers_to_auto_cc_WREADY), + .s_axi_wstrb(m00_couplers_to_auto_cc_WSTRB), + .s_axi_wvalid(m00_couplers_to_auto_cc_WVALID)); +endmodule + +(* CORE_GENERATION_INFO = "pcie_ddr,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=pcie_ddr,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=17,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=5,da_clkrst_cnt=2,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "pcie_ddr.hwdef" *) +module pcie_ddr + (ddr_addr, + ddr_axi_araddr, + ddr_axi_arburst, + ddr_axi_arcache, + ddr_axi_arid, + ddr_axi_arlen, + ddr_axi_arlock, + ddr_axi_arprot, + ddr_axi_arqos, + ddr_axi_arready, + ddr_axi_arsize, + ddr_axi_arvalid, + ddr_axi_awaddr, + ddr_axi_awburst, + ddr_axi_awcache, + ddr_axi_awid, + ddr_axi_awlen, + ddr_axi_awlock, + ddr_axi_awprot, + ddr_axi_awqos, + ddr_axi_awready, + ddr_axi_awsize, + ddr_axi_awvalid, + ddr_axi_bid, + ddr_axi_bready, + ddr_axi_bresp, + ddr_axi_bvalid, + ddr_axi_rdata, + ddr_axi_rid, + ddr_axi_rlast, + ddr_axi_rready, + ddr_axi_rresp, + ddr_axi_rvalid, + ddr_axi_wdata, + ddr_axi_wlast, + ddr_axi_wready, + ddr_axi_wstrb, + ddr_axi_wvalid, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + init_calib_complete, + pcie_clk_clk_n, + pcie_clk_clk_p, + pcie_mgt_rxn, + pcie_mgt_rxp, + pcie_mgt_txn, + pcie_mgt_txp, + pcie_msi_enable, + pcie_user_lnk_up, + pcie_usr_irq_req, + sys_clk, + sys_rst_n_0, + sys_rstn); + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ddr, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [15:0]ddr_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ddr_axi, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pcie_ddr_clk_in1_0, DATA_WIDTH 32, FREQ_HZ 200000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]ddr_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [1:0]ddr_axi_arburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_arcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [0:0]ddr_axi_arid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [7:0]ddr_axi_arlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [0:0]ddr_axi_arlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [2:0]ddr_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_arqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [2:0]ddr_axi_arsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [31:0]ddr_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [1:0]ddr_axi_awburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_awcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [0:0]ddr_axi_awid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [7:0]ddr_axi_awlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [0:0]ddr_axi_awlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [2:0]ddr_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_awqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [2:0]ddr_axi_awsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [0:0]ddr_axi_bid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [1:0]ddr_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [31:0]ddr_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [0:0]ddr_axi_rid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_rlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [1:0]ddr_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [31:0]ddr_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_wlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [2:0]ddr_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output ddr_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [7:0]ddr_dm; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) inout [63:0]ddr_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) inout [7:0]ddr_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) inout [7:0]ddr_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output ddr_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output ddr_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output ddr_we_n; + output init_calib_complete; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clk " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME pcie_clk, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]pcie_clk_clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clk " *) input [0:0]pcie_clk_clk_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt " *) input [7:0]pcie_mgt_rxn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt " *) input [7:0]pcie_mgt_rxp; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt " *) output [7:0]pcie_mgt_txn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt " *) output [7:0]pcie_mgt_txp; + output pcie_msi_enable; + output pcie_user_lnk_up; + input [0:0]pcie_usr_irq_req; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYS_CLK, ASSOCIATED_BUSIF ddr_axi, ASSOCIATED_RESET sys_rstn, CLK_DOMAIN pcie_ddr_clk_in1_0, FREQ_HZ 200000000, INSERT_VIP 0, PHASE 0.000" *) input sys_clk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.SYS_RST_N_0 RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.SYS_RST_N_0, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input sys_rst_n_0; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.SYS_RSTN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.SYS_RSTN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input sys_rstn; + + wire [0:0]CLK_IN_D_0_1_CLK_N; + wire [0:0]CLK_IN_D_0_1_CLK_P; + wire [31:0]S01_AXI_0_1_ARADDR; + wire [1:0]S01_AXI_0_1_ARBURST; + wire [3:0]S01_AXI_0_1_ARCACHE; + wire [0:0]S01_AXI_0_1_ARID; + wire [7:0]S01_AXI_0_1_ARLEN; + wire [0:0]S01_AXI_0_1_ARLOCK; + wire [2:0]S01_AXI_0_1_ARPROT; + wire [3:0]S01_AXI_0_1_ARQOS; + wire S01_AXI_0_1_ARREADY; + wire [2:0]S01_AXI_0_1_ARSIZE; + wire S01_AXI_0_1_ARVALID; + wire [31:0]S01_AXI_0_1_AWADDR; + wire [1:0]S01_AXI_0_1_AWBURST; + wire [3:0]S01_AXI_0_1_AWCACHE; + wire [0:0]S01_AXI_0_1_AWID; + wire [7:0]S01_AXI_0_1_AWLEN; + wire [0:0]S01_AXI_0_1_AWLOCK; + wire [2:0]S01_AXI_0_1_AWPROT; + wire [3:0]S01_AXI_0_1_AWQOS; + wire S01_AXI_0_1_AWREADY; + wire [2:0]S01_AXI_0_1_AWSIZE; + wire S01_AXI_0_1_AWVALID; + wire [0:0]S01_AXI_0_1_BID; + wire S01_AXI_0_1_BREADY; + wire [1:0]S01_AXI_0_1_BRESP; + wire S01_AXI_0_1_BVALID; + wire [31:0]S01_AXI_0_1_RDATA; + wire [0:0]S01_AXI_0_1_RID; + wire S01_AXI_0_1_RLAST; + wire S01_AXI_0_1_RREADY; + wire [1:0]S01_AXI_0_1_RRESP; + wire S01_AXI_0_1_RVALID; + wire [31:0]S01_AXI_0_1_WDATA; + wire S01_AXI_0_1_WLAST; + wire S01_AXI_0_1_WREADY; + wire [3:0]S01_AXI_0_1_WSTRB; + wire S01_AXI_0_1_WVALID; + wire [32:0]axi_interconnect_0_M00_AXI_ARADDR; + wire [1:0]axi_interconnect_0_M00_AXI_ARBURST; + wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE; + wire [0:0]axi_interconnect_0_M00_AXI_ARID; + wire [7:0]axi_interconnect_0_M00_AXI_ARLEN; + wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK; + wire [2:0]axi_interconnect_0_M00_AXI_ARPROT; + wire [3:0]axi_interconnect_0_M00_AXI_ARQOS; + wire axi_interconnect_0_M00_AXI_ARREADY; + wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE; + wire axi_interconnect_0_M00_AXI_ARVALID; + wire [32:0]axi_interconnect_0_M00_AXI_AWADDR; + wire [1:0]axi_interconnect_0_M00_AXI_AWBURST; + wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE; + wire [0:0]axi_interconnect_0_M00_AXI_AWID; + wire [7:0]axi_interconnect_0_M00_AXI_AWLEN; + wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK; + wire [2:0]axi_interconnect_0_M00_AXI_AWPROT; + wire [3:0]axi_interconnect_0_M00_AXI_AWQOS; + wire axi_interconnect_0_M00_AXI_AWREADY; + wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE; + wire axi_interconnect_0_M00_AXI_AWVALID; + wire [0:0]axi_interconnect_0_M00_AXI_BID; + wire axi_interconnect_0_M00_AXI_BREADY; + wire [1:0]axi_interconnect_0_M00_AXI_BRESP; + wire axi_interconnect_0_M00_AXI_BVALID; + wire [511:0]axi_interconnect_0_M00_AXI_RDATA; + wire [0:0]axi_interconnect_0_M00_AXI_RID; + wire axi_interconnect_0_M00_AXI_RLAST; + wire axi_interconnect_0_M00_AXI_RREADY; + wire [1:0]axi_interconnect_0_M00_AXI_RRESP; + wire axi_interconnect_0_M00_AXI_RVALID; + wire [511:0]axi_interconnect_0_M00_AXI_WDATA; + wire axi_interconnect_0_M00_AXI_WLAST; + wire axi_interconnect_0_M00_AXI_WREADY; + wire [63:0]axi_interconnect_0_M00_AXI_WSTRB; + wire axi_interconnect_0_M00_AXI_WVALID; + wire clk_in1_0_1; + wire clk_wiz_0_clk_out1; + wire clk_wiz_0_locked; + wire [15:0]mig_7series_0_DDR3_ADDR; + wire [2:0]mig_7series_0_DDR3_BA; + wire mig_7series_0_DDR3_CAS_N; + wire [1:0]mig_7series_0_DDR3_CKE; + wire [1:0]mig_7series_0_DDR3_CK_N; + wire [1:0]mig_7series_0_DDR3_CK_P; + wire [1:0]mig_7series_0_DDR3_CS_N; + wire [7:0]mig_7series_0_DDR3_DM; + wire [63:0]mig_7series_0_DDR3_DQ; + wire [7:0]mig_7series_0_DDR3_DQS_N; + wire [7:0]mig_7series_0_DDR3_DQS_P; + wire [1:0]mig_7series_0_DDR3_ODT; + wire mig_7series_0_DDR3_RAS_N; + wire mig_7series_0_DDR3_RESET_N; + wire mig_7series_0_DDR3_WE_N; + wire mig_7series_0_init_calib_complete; + wire mig_7series_0_mmcm_locked; + wire mig_7series_0_ui_clk; + wire mig_7series_0_ui_clk_sync_rst; + wire resetn_0_1; + wire [0:0]rst_clk_wiz_0_200M_peripheral_aresetn; + wire [0:0]rst_mig_7series_0_100M_peripheral_aresetn; + wire sys_rst_n_0_1; + wire [0:0]usr_irq_req_0_1; + wire [0:0]util_ds_buf_0_IBUF_OUT; + wire [63:0]xdma_0_M_AXI_ARADDR; + wire [1:0]xdma_0_M_AXI_ARBURST; + wire [3:0]xdma_0_M_AXI_ARCACHE; + wire [3:0]xdma_0_M_AXI_ARID; + wire [7:0]xdma_0_M_AXI_ARLEN; + wire xdma_0_M_AXI_ARLOCK; + wire [2:0]xdma_0_M_AXI_ARPROT; + wire xdma_0_M_AXI_ARREADY; + wire [2:0]xdma_0_M_AXI_ARSIZE; + wire xdma_0_M_AXI_ARVALID; + wire [63:0]xdma_0_M_AXI_AWADDR; + wire [1:0]xdma_0_M_AXI_AWBURST; + wire [3:0]xdma_0_M_AXI_AWCACHE; + wire [3:0]xdma_0_M_AXI_AWID; + wire [7:0]xdma_0_M_AXI_AWLEN; + wire xdma_0_M_AXI_AWLOCK; + wire [2:0]xdma_0_M_AXI_AWPROT; + wire xdma_0_M_AXI_AWREADY; + wire [2:0]xdma_0_M_AXI_AWSIZE; + wire xdma_0_M_AXI_AWVALID; + wire [3:0]xdma_0_M_AXI_BID; + wire xdma_0_M_AXI_BREADY; + wire [1:0]xdma_0_M_AXI_BRESP; + wire xdma_0_M_AXI_BVALID; + wire [127:0]xdma_0_M_AXI_RDATA; + wire [3:0]xdma_0_M_AXI_RID; + wire xdma_0_M_AXI_RLAST; + wire xdma_0_M_AXI_RREADY; + wire [1:0]xdma_0_M_AXI_RRESP; + wire xdma_0_M_AXI_RVALID; + wire [127:0]xdma_0_M_AXI_WDATA; + wire xdma_0_M_AXI_WLAST; + wire xdma_0_M_AXI_WREADY; + wire [15:0]xdma_0_M_AXI_WSTRB; + wire xdma_0_M_AXI_WVALID; + wire xdma_0_axi_aclk; + wire xdma_0_axi_aresetn; + wire xdma_0_msi_enable; + wire [7:0]xdma_0_pcie_mgt_rxn; + wire [7:0]xdma_0_pcie_mgt_rxp; + wire [7:0]xdma_0_pcie_mgt_txn; + wire [7:0]xdma_0_pcie_mgt_txp; + wire xdma_0_user_lnk_up; + + assign CLK_IN_D_0_1_CLK_N = pcie_clk_clk_n[0]; + assign CLK_IN_D_0_1_CLK_P = pcie_clk_clk_p[0]; + assign S01_AXI_0_1_ARADDR = ddr_axi_araddr[31:0]; + assign S01_AXI_0_1_ARBURST = ddr_axi_arburst[1:0]; + assign S01_AXI_0_1_ARCACHE = ddr_axi_arcache[3:0]; + assign S01_AXI_0_1_ARID = ddr_axi_arid[0]; + assign S01_AXI_0_1_ARLEN = ddr_axi_arlen[7:0]; + assign S01_AXI_0_1_ARLOCK = ddr_axi_arlock[0]; + assign S01_AXI_0_1_ARPROT = ddr_axi_arprot[2:0]; + assign S01_AXI_0_1_ARQOS = ddr_axi_arqos[3:0]; + assign S01_AXI_0_1_ARSIZE = ddr_axi_arsize[2:0]; + assign S01_AXI_0_1_ARVALID = ddr_axi_arvalid; + assign S01_AXI_0_1_AWADDR = ddr_axi_awaddr[31:0]; + assign S01_AXI_0_1_AWBURST = ddr_axi_awburst[1:0]; + assign S01_AXI_0_1_AWCACHE = ddr_axi_awcache[3:0]; + assign S01_AXI_0_1_AWID = ddr_axi_awid[0]; + assign S01_AXI_0_1_AWLEN = ddr_axi_awlen[7:0]; + assign S01_AXI_0_1_AWLOCK = ddr_axi_awlock[0]; + assign S01_AXI_0_1_AWPROT = ddr_axi_awprot[2:0]; + assign S01_AXI_0_1_AWQOS = ddr_axi_awqos[3:0]; + assign S01_AXI_0_1_AWSIZE = ddr_axi_awsize[2:0]; + assign S01_AXI_0_1_AWVALID = ddr_axi_awvalid; + assign S01_AXI_0_1_BREADY = ddr_axi_bready; + assign S01_AXI_0_1_RREADY = ddr_axi_rready; + assign S01_AXI_0_1_WDATA = ddr_axi_wdata[31:0]; + assign S01_AXI_0_1_WLAST = ddr_axi_wlast; + assign S01_AXI_0_1_WSTRB = ddr_axi_wstrb[3:0]; + assign S01_AXI_0_1_WVALID = ddr_axi_wvalid; + assign clk_in1_0_1 = sys_clk; + assign ddr_addr[15:0] = mig_7series_0_DDR3_ADDR; + assign ddr_axi_arready = S01_AXI_0_1_ARREADY; + assign ddr_axi_awready = S01_AXI_0_1_AWREADY; + assign ddr_axi_bid[0] = S01_AXI_0_1_BID; + assign ddr_axi_bresp[1:0] = S01_AXI_0_1_BRESP; + assign ddr_axi_bvalid = S01_AXI_0_1_BVALID; + assign ddr_axi_rdata[31:0] = S01_AXI_0_1_RDATA; + assign ddr_axi_rid[0] = S01_AXI_0_1_RID; + assign ddr_axi_rlast = S01_AXI_0_1_RLAST; + assign ddr_axi_rresp[1:0] = S01_AXI_0_1_RRESP; + assign ddr_axi_rvalid = S01_AXI_0_1_RVALID; + assign ddr_axi_wready = S01_AXI_0_1_WREADY; + assign ddr_ba[2:0] = mig_7series_0_DDR3_BA; + assign ddr_cas_n = mig_7series_0_DDR3_CAS_N; + assign ddr_ck_n[1:0] = mig_7series_0_DDR3_CK_N; + assign ddr_ck_p[1:0] = mig_7series_0_DDR3_CK_P; + assign ddr_cke[1:0] = mig_7series_0_DDR3_CKE; + assign ddr_cs_n[1:0] = mig_7series_0_DDR3_CS_N; + assign ddr_dm[7:0] = mig_7series_0_DDR3_DM; + assign ddr_odt[1:0] = mig_7series_0_DDR3_ODT; + assign ddr_ras_n = mig_7series_0_DDR3_RAS_N; + assign ddr_reset_n = mig_7series_0_DDR3_RESET_N; + assign ddr_we_n = mig_7series_0_DDR3_WE_N; + assign init_calib_complete = mig_7series_0_init_calib_complete; + assign pcie_mgt_txn[7:0] = xdma_0_pcie_mgt_txn; + assign pcie_mgt_txp[7:0] = xdma_0_pcie_mgt_txp; + assign pcie_msi_enable = xdma_0_msi_enable; + assign pcie_user_lnk_up = xdma_0_user_lnk_up; + assign resetn_0_1 = sys_rstn; + assign sys_rst_n_0_1 = sys_rst_n_0; + assign usr_irq_req_0_1 = pcie_usr_irq_req[0]; + assign xdma_0_pcie_mgt_rxn = pcie_mgt_rxn[7:0]; + assign xdma_0_pcie_mgt_rxp = pcie_mgt_rxp[7:0]; + pcie_ddr_axi_interconnect_0_1 axi_interconnect_0 + (.ACLK(clk_wiz_0_clk_out1), + .ARESETN(rst_clk_wiz_0_200M_peripheral_aresetn), + .M00_ACLK(mig_7series_0_ui_clk), + .M00_ARESETN(rst_mig_7series_0_100M_peripheral_aresetn), + .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR), + .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST), + .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE), + .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID), + .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN), + .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK), + .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT), + .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS), + .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY), + .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE), + .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID), + .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR), + .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST), + .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE), + .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID), + .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN), + .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK), + .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT), + .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS), + .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY), + .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE), + .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID), + .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID), + .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY), + .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP), + .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID), + .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA), + .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID), + .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST), + .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY), + .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP), + .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID), + .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA), + .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST), + .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY), + .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB), + .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID), + .S00_ACLK(xdma_0_axi_aclk), + .S00_ARESETN(xdma_0_axi_aresetn), + .S00_AXI_araddr(xdma_0_M_AXI_ARADDR), + .S00_AXI_arburst(xdma_0_M_AXI_ARBURST), + .S00_AXI_arcache(xdma_0_M_AXI_ARCACHE), + .S00_AXI_arid(xdma_0_M_AXI_ARID), + .S00_AXI_arlen(xdma_0_M_AXI_ARLEN), + .S00_AXI_arlock(xdma_0_M_AXI_ARLOCK), + .S00_AXI_arprot(xdma_0_M_AXI_ARPROT), + .S00_AXI_arready(xdma_0_M_AXI_ARREADY), + .S00_AXI_arsize(xdma_0_M_AXI_ARSIZE), + .S00_AXI_arvalid(xdma_0_M_AXI_ARVALID), + .S00_AXI_awaddr(xdma_0_M_AXI_AWADDR), + .S00_AXI_awburst(xdma_0_M_AXI_AWBURST), + .S00_AXI_awcache(xdma_0_M_AXI_AWCACHE), + .S00_AXI_awid(xdma_0_M_AXI_AWID), + .S00_AXI_awlen(xdma_0_M_AXI_AWLEN), + .S00_AXI_awlock(xdma_0_M_AXI_AWLOCK), + .S00_AXI_awprot(xdma_0_M_AXI_AWPROT), + .S00_AXI_awready(xdma_0_M_AXI_AWREADY), + .S00_AXI_awsize(xdma_0_M_AXI_AWSIZE), + .S00_AXI_awvalid(xdma_0_M_AXI_AWVALID), + .S00_AXI_bid(xdma_0_M_AXI_BID), + .S00_AXI_bready(xdma_0_M_AXI_BREADY), + .S00_AXI_bresp(xdma_0_M_AXI_BRESP), + .S00_AXI_bvalid(xdma_0_M_AXI_BVALID), + .S00_AXI_rdata(xdma_0_M_AXI_RDATA), + .S00_AXI_rid(xdma_0_M_AXI_RID), + .S00_AXI_rlast(xdma_0_M_AXI_RLAST), + .S00_AXI_rready(xdma_0_M_AXI_RREADY), + .S00_AXI_rresp(xdma_0_M_AXI_RRESP), + .S00_AXI_rvalid(xdma_0_M_AXI_RVALID), + .S00_AXI_wdata(xdma_0_M_AXI_WDATA), + .S00_AXI_wlast(xdma_0_M_AXI_WLAST), + .S00_AXI_wready(xdma_0_M_AXI_WREADY), + .S00_AXI_wstrb(xdma_0_M_AXI_WSTRB), + .S00_AXI_wvalid(xdma_0_M_AXI_WVALID), + .S01_ACLK(clk_in1_0_1), + .S01_ARESETN(resetn_0_1), + .S01_AXI_araddr(S01_AXI_0_1_ARADDR), + .S01_AXI_arburst(S01_AXI_0_1_ARBURST), + .S01_AXI_arcache(S01_AXI_0_1_ARCACHE), + .S01_AXI_arid(S01_AXI_0_1_ARID), + .S01_AXI_arlen(S01_AXI_0_1_ARLEN), + .S01_AXI_arlock(S01_AXI_0_1_ARLOCK), + .S01_AXI_arprot(S01_AXI_0_1_ARPROT), + .S01_AXI_arqos(S01_AXI_0_1_ARQOS), + .S01_AXI_arready(S01_AXI_0_1_ARREADY), + .S01_AXI_arsize(S01_AXI_0_1_ARSIZE), + .S01_AXI_arvalid(S01_AXI_0_1_ARVALID), + .S01_AXI_awaddr(S01_AXI_0_1_AWADDR), + .S01_AXI_awburst(S01_AXI_0_1_AWBURST), + .S01_AXI_awcache(S01_AXI_0_1_AWCACHE), + .S01_AXI_awid(S01_AXI_0_1_AWID), + .S01_AXI_awlen(S01_AXI_0_1_AWLEN), + .S01_AXI_awlock(S01_AXI_0_1_AWLOCK), + .S01_AXI_awprot(S01_AXI_0_1_AWPROT), + .S01_AXI_awqos(S01_AXI_0_1_AWQOS), + .S01_AXI_awready(S01_AXI_0_1_AWREADY), + .S01_AXI_awsize(S01_AXI_0_1_AWSIZE), + .S01_AXI_awvalid(S01_AXI_0_1_AWVALID), + .S01_AXI_bid(S01_AXI_0_1_BID), + .S01_AXI_bready(S01_AXI_0_1_BREADY), + .S01_AXI_bresp(S01_AXI_0_1_BRESP), + .S01_AXI_bvalid(S01_AXI_0_1_BVALID), + .S01_AXI_rdata(S01_AXI_0_1_RDATA), + .S01_AXI_rid(S01_AXI_0_1_RID), + .S01_AXI_rlast(S01_AXI_0_1_RLAST), + .S01_AXI_rready(S01_AXI_0_1_RREADY), + .S01_AXI_rresp(S01_AXI_0_1_RRESP), + .S01_AXI_rvalid(S01_AXI_0_1_RVALID), + .S01_AXI_wdata(S01_AXI_0_1_WDATA), + .S01_AXI_wlast(S01_AXI_0_1_WLAST), + .S01_AXI_wready(S01_AXI_0_1_WREADY), + .S01_AXI_wstrb(S01_AXI_0_1_WSTRB), + .S01_AXI_wvalid(S01_AXI_0_1_WVALID)); + pcie_ddr_clk_wiz_0_0 clk_wiz_0 + (.clk_in1(clk_in1_0_1), + .clk_out1(clk_wiz_0_clk_out1), + .locked(clk_wiz_0_locked), + .resetn(resetn_0_1)); + pcie_ddr_mig_7series_0_0 mig_7series_0 + (.aresetn(rst_mig_7series_0_100M_peripheral_aresetn), + .ddr3_addr(mig_7series_0_DDR3_ADDR), + .ddr3_ba(mig_7series_0_DDR3_BA), + .ddr3_cas_n(mig_7series_0_DDR3_CAS_N), + .ddr3_ck_n(mig_7series_0_DDR3_CK_N), + .ddr3_ck_p(mig_7series_0_DDR3_CK_P), + .ddr3_cke(mig_7series_0_DDR3_CKE), + .ddr3_cs_n(mig_7series_0_DDR3_CS_N), + .ddr3_dm(mig_7series_0_DDR3_DM), + .ddr3_dq(ddr_dq[63:0]), + .ddr3_dqs_n(ddr_dqs_n[7:0]), + .ddr3_dqs_p(ddr_dqs_p[7:0]), + .ddr3_odt(mig_7series_0_DDR3_ODT), + .ddr3_ras_n(mig_7series_0_DDR3_RAS_N), + .ddr3_reset_n(mig_7series_0_DDR3_RESET_N), + .ddr3_we_n(mig_7series_0_DDR3_WE_N), + .init_calib_complete(mig_7series_0_init_calib_complete), + .mmcm_locked(mig_7series_0_mmcm_locked), + .s_axi_araddr(axi_interconnect_0_M00_AXI_ARADDR), + .s_axi_arburst(axi_interconnect_0_M00_AXI_ARBURST), + .s_axi_arcache(axi_interconnect_0_M00_AXI_ARCACHE), + .s_axi_arid(axi_interconnect_0_M00_AXI_ARID), + .s_axi_arlen(axi_interconnect_0_M00_AXI_ARLEN), + .s_axi_arlock(axi_interconnect_0_M00_AXI_ARLOCK), + .s_axi_arprot(axi_interconnect_0_M00_AXI_ARPROT), + .s_axi_arqos(axi_interconnect_0_M00_AXI_ARQOS), + .s_axi_arready(axi_interconnect_0_M00_AXI_ARREADY), + .s_axi_arsize(axi_interconnect_0_M00_AXI_ARSIZE), + .s_axi_arvalid(axi_interconnect_0_M00_AXI_ARVALID), + .s_axi_awaddr(axi_interconnect_0_M00_AXI_AWADDR), + .s_axi_awburst(axi_interconnect_0_M00_AXI_AWBURST), + .s_axi_awcache(axi_interconnect_0_M00_AXI_AWCACHE), + .s_axi_awid(axi_interconnect_0_M00_AXI_AWID), + .s_axi_awlen(axi_interconnect_0_M00_AXI_AWLEN), + .s_axi_awlock(axi_interconnect_0_M00_AXI_AWLOCK), + .s_axi_awprot(axi_interconnect_0_M00_AXI_AWPROT), + .s_axi_awqos(axi_interconnect_0_M00_AXI_AWQOS), + .s_axi_awready(axi_interconnect_0_M00_AXI_AWREADY), + .s_axi_awsize(axi_interconnect_0_M00_AXI_AWSIZE), + .s_axi_awvalid(axi_interconnect_0_M00_AXI_AWVALID), + .s_axi_bid(axi_interconnect_0_M00_AXI_BID), + .s_axi_bready(axi_interconnect_0_M00_AXI_BREADY), + .s_axi_bresp(axi_interconnect_0_M00_AXI_BRESP), + .s_axi_bvalid(axi_interconnect_0_M00_AXI_BVALID), + .s_axi_rdata(axi_interconnect_0_M00_AXI_RDATA), + .s_axi_rid(axi_interconnect_0_M00_AXI_RID), + .s_axi_rlast(axi_interconnect_0_M00_AXI_RLAST), + .s_axi_rready(axi_interconnect_0_M00_AXI_RREADY), + .s_axi_rresp(axi_interconnect_0_M00_AXI_RRESP), + .s_axi_rvalid(axi_interconnect_0_M00_AXI_RVALID), + .s_axi_wdata(axi_interconnect_0_M00_AXI_WDATA), + .s_axi_wlast(axi_interconnect_0_M00_AXI_WLAST), + .s_axi_wready(axi_interconnect_0_M00_AXI_WREADY), + .s_axi_wstrb(axi_interconnect_0_M00_AXI_WSTRB), + .s_axi_wvalid(axi_interconnect_0_M00_AXI_WVALID), + .sys_clk_i(clk_wiz_0_clk_out1), + .sys_rst(clk_wiz_0_locked), + .ui_clk(mig_7series_0_ui_clk), + .ui_clk_sync_rst(mig_7series_0_ui_clk_sync_rst)); + pcie_ddr_rst_clk_wiz_0_200M_0 rst_clk_wiz_0_200M + (.aux_reset_in(1'b1), + .dcm_locked(clk_wiz_0_locked), + .ext_reset_in(resetn_0_1), + .mb_debug_sys_rst(1'b0), + .peripheral_aresetn(rst_clk_wiz_0_200M_peripheral_aresetn), + .slowest_sync_clk(clk_wiz_0_clk_out1)); + pcie_ddr_rst_mig_7series_0_100M_4 rst_mig_7series_0_100M + (.aux_reset_in(1'b1), + .dcm_locked(mig_7series_0_mmcm_locked), + .ext_reset_in(mig_7series_0_ui_clk_sync_rst), + .mb_debug_sys_rst(1'b0), + .peripheral_aresetn(rst_mig_7series_0_100M_peripheral_aresetn), + .slowest_sync_clk(mig_7series_0_ui_clk)); + pcie_ddr_util_ds_buf_0_0 util_ds_buf_0 + (.IBUF_DS_N(CLK_IN_D_0_1_CLK_N), + .IBUF_DS_P(CLK_IN_D_0_1_CLK_P), + .IBUF_OUT(util_ds_buf_0_IBUF_OUT)); + pcie_ddr_xdma_0_0 xdma_0 + (.axi_aclk(xdma_0_axi_aclk), + .axi_aresetn(xdma_0_axi_aresetn), + .cfg_mgmt_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .cfg_mgmt_byte_enable({1'b0,1'b0,1'b0,1'b0}), + .cfg_mgmt_read(1'b0), + .cfg_mgmt_type1_cfg_reg_access(1'b0), + .cfg_mgmt_write(1'b0), + .cfg_mgmt_write_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_araddr(xdma_0_M_AXI_ARADDR), + .m_axi_arburst(xdma_0_M_AXI_ARBURST), + .m_axi_arcache(xdma_0_M_AXI_ARCACHE), + .m_axi_arid(xdma_0_M_AXI_ARID), + .m_axi_arlen(xdma_0_M_AXI_ARLEN), + .m_axi_arlock(xdma_0_M_AXI_ARLOCK), + .m_axi_arprot(xdma_0_M_AXI_ARPROT), + .m_axi_arready(xdma_0_M_AXI_ARREADY), + .m_axi_arsize(xdma_0_M_AXI_ARSIZE), + .m_axi_arvalid(xdma_0_M_AXI_ARVALID), + .m_axi_awaddr(xdma_0_M_AXI_AWADDR), + .m_axi_awburst(xdma_0_M_AXI_AWBURST), + .m_axi_awcache(xdma_0_M_AXI_AWCACHE), + .m_axi_awid(xdma_0_M_AXI_AWID), + .m_axi_awlen(xdma_0_M_AXI_AWLEN), + .m_axi_awlock(xdma_0_M_AXI_AWLOCK), + .m_axi_awprot(xdma_0_M_AXI_AWPROT), + .m_axi_awready(xdma_0_M_AXI_AWREADY), + .m_axi_awsize(xdma_0_M_AXI_AWSIZE), + .m_axi_awvalid(xdma_0_M_AXI_AWVALID), + .m_axi_bid(xdma_0_M_AXI_BID), + .m_axi_bready(xdma_0_M_AXI_BREADY), + .m_axi_bresp(xdma_0_M_AXI_BRESP), + .m_axi_bvalid(xdma_0_M_AXI_BVALID), + .m_axi_rdata(xdma_0_M_AXI_RDATA), + .m_axi_rid(xdma_0_M_AXI_RID), + .m_axi_rlast(xdma_0_M_AXI_RLAST), + .m_axi_rready(xdma_0_M_AXI_RREADY), + .m_axi_rresp(xdma_0_M_AXI_RRESP), + .m_axi_rvalid(xdma_0_M_AXI_RVALID), + .m_axi_wdata(xdma_0_M_AXI_WDATA), + .m_axi_wlast(xdma_0_M_AXI_WLAST), + .m_axi_wready(xdma_0_M_AXI_WREADY), + .m_axi_wstrb(xdma_0_M_AXI_WSTRB), + .m_axi_wvalid(xdma_0_M_AXI_WVALID), + .msi_enable(xdma_0_msi_enable), + .pci_exp_rxn(xdma_0_pcie_mgt_rxn), + .pci_exp_rxp(xdma_0_pcie_mgt_rxp), + .pci_exp_txn(xdma_0_pcie_mgt_txn), + .pci_exp_txp(xdma_0_pcie_mgt_txp), + .sys_clk(util_ds_buf_0_IBUF_OUT), + .sys_rst_n(sys_rst_n_0_1), + .user_lnk_up(xdma_0_user_lnk_up), + .usr_irq_req(usr_irq_req_0_1)); +endmodule + +module pcie_ddr_axi_interconnect_0_1 + (ACLK, + ARESETN, + M00_ACLK, + M00_ARESETN, + M00_AXI_araddr, + M00_AXI_arburst, + M00_AXI_arcache, + M00_AXI_arid, + M00_AXI_arlen, + M00_AXI_arlock, + M00_AXI_arprot, + M00_AXI_arqos, + M00_AXI_arready, + M00_AXI_arsize, + M00_AXI_arvalid, + M00_AXI_awaddr, + M00_AXI_awburst, + M00_AXI_awcache, + M00_AXI_awid, + M00_AXI_awlen, + M00_AXI_awlock, + M00_AXI_awprot, + M00_AXI_awqos, + M00_AXI_awready, + M00_AXI_awsize, + M00_AXI_awvalid, + M00_AXI_bid, + M00_AXI_bready, + M00_AXI_bresp, + M00_AXI_bvalid, + M00_AXI_rdata, + M00_AXI_rid, + M00_AXI_rlast, + M00_AXI_rready, + M00_AXI_rresp, + M00_AXI_rvalid, + M00_AXI_wdata, + M00_AXI_wlast, + M00_AXI_wready, + M00_AXI_wstrb, + M00_AXI_wvalid, + S00_ACLK, + S00_ARESETN, + S00_AXI_araddr, + S00_AXI_arburst, + S00_AXI_arcache, + S00_AXI_arid, + S00_AXI_arlen, + S00_AXI_arlock, + S00_AXI_arprot, + S00_AXI_arready, + S00_AXI_arsize, + S00_AXI_arvalid, + S00_AXI_awaddr, + S00_AXI_awburst, + S00_AXI_awcache, + S00_AXI_awid, + S00_AXI_awlen, + S00_AXI_awlock, + S00_AXI_awprot, + S00_AXI_awready, + S00_AXI_awsize, + S00_AXI_awvalid, + S00_AXI_bid, + S00_AXI_bready, + S00_AXI_bresp, + S00_AXI_bvalid, + S00_AXI_rdata, + S00_AXI_rid, + S00_AXI_rlast, + S00_AXI_rready, + S00_AXI_rresp, + S00_AXI_rvalid, + S00_AXI_wdata, + S00_AXI_wlast, + S00_AXI_wready, + S00_AXI_wstrb, + S00_AXI_wvalid, + S01_ACLK, + S01_ARESETN, + S01_AXI_araddr, + S01_AXI_arburst, + S01_AXI_arcache, + S01_AXI_arid, + S01_AXI_arlen, + S01_AXI_arlock, + S01_AXI_arprot, + S01_AXI_arqos, + S01_AXI_arready, + S01_AXI_arsize, + S01_AXI_arvalid, + S01_AXI_awaddr, + S01_AXI_awburst, + S01_AXI_awcache, + S01_AXI_awid, + S01_AXI_awlen, + S01_AXI_awlock, + S01_AXI_awprot, + S01_AXI_awqos, + S01_AXI_awready, + S01_AXI_awsize, + S01_AXI_awvalid, + S01_AXI_bid, + S01_AXI_bready, + S01_AXI_bresp, + S01_AXI_bvalid, + S01_AXI_rdata, + S01_AXI_rid, + S01_AXI_rlast, + S01_AXI_rready, + S01_AXI_rresp, + S01_AXI_rvalid, + S01_AXI_wdata, + S01_AXI_wlast, + S01_AXI_wready, + S01_AXI_wstrb, + S01_AXI_wvalid); + input ACLK; + input ARESETN; + input M00_ACLK; + input M00_ARESETN; + output [32:0]M00_AXI_araddr; + output [1:0]M00_AXI_arburst; + output [3:0]M00_AXI_arcache; + output [0:0]M00_AXI_arid; + output [7:0]M00_AXI_arlen; + output [0:0]M00_AXI_arlock; + output [2:0]M00_AXI_arprot; + output [3:0]M00_AXI_arqos; + input M00_AXI_arready; + output [2:0]M00_AXI_arsize; + output M00_AXI_arvalid; + output [32:0]M00_AXI_awaddr; + output [1:0]M00_AXI_awburst; + output [3:0]M00_AXI_awcache; + output [0:0]M00_AXI_awid; + output [7:0]M00_AXI_awlen; + output [0:0]M00_AXI_awlock; + output [2:0]M00_AXI_awprot; + output [3:0]M00_AXI_awqos; + input M00_AXI_awready; + output [2:0]M00_AXI_awsize; + output M00_AXI_awvalid; + input [0:0]M00_AXI_bid; + output M00_AXI_bready; + input [1:0]M00_AXI_bresp; + input M00_AXI_bvalid; + input [511:0]M00_AXI_rdata; + input [0:0]M00_AXI_rid; + input M00_AXI_rlast; + output M00_AXI_rready; + input [1:0]M00_AXI_rresp; + input M00_AXI_rvalid; + output [511:0]M00_AXI_wdata; + output M00_AXI_wlast; + input M00_AXI_wready; + output [63:0]M00_AXI_wstrb; + output M00_AXI_wvalid; + input S00_ACLK; + input S00_ARESETN; + input [63:0]S00_AXI_araddr; + input [1:0]S00_AXI_arburst; + input [3:0]S00_AXI_arcache; + input [3:0]S00_AXI_arid; + input [7:0]S00_AXI_arlen; + input [0:0]S00_AXI_arlock; + input [2:0]S00_AXI_arprot; + output S00_AXI_arready; + input [2:0]S00_AXI_arsize; + input S00_AXI_arvalid; + input [63:0]S00_AXI_awaddr; + input [1:0]S00_AXI_awburst; + input [3:0]S00_AXI_awcache; + input [3:0]S00_AXI_awid; + input [7:0]S00_AXI_awlen; + input [0:0]S00_AXI_awlock; + input [2:0]S00_AXI_awprot; + output S00_AXI_awready; + input [2:0]S00_AXI_awsize; + input S00_AXI_awvalid; + output [3:0]S00_AXI_bid; + input S00_AXI_bready; + output [1:0]S00_AXI_bresp; + output S00_AXI_bvalid; + output [127:0]S00_AXI_rdata; + output [3:0]S00_AXI_rid; + output S00_AXI_rlast; + input S00_AXI_rready; + output [1:0]S00_AXI_rresp; + output S00_AXI_rvalid; + input [127:0]S00_AXI_wdata; + input S00_AXI_wlast; + output S00_AXI_wready; + input [15:0]S00_AXI_wstrb; + input S00_AXI_wvalid; + input S01_ACLK; + input S01_ARESETN; + input [31:0]S01_AXI_araddr; + input [1:0]S01_AXI_arburst; + input [3:0]S01_AXI_arcache; + input [0:0]S01_AXI_arid; + input [7:0]S01_AXI_arlen; + input [0:0]S01_AXI_arlock; + input [2:0]S01_AXI_arprot; + input [3:0]S01_AXI_arqos; + output S01_AXI_arready; + input [2:0]S01_AXI_arsize; + input S01_AXI_arvalid; + input [31:0]S01_AXI_awaddr; + input [1:0]S01_AXI_awburst; + input [3:0]S01_AXI_awcache; + input [0:0]S01_AXI_awid; + input [7:0]S01_AXI_awlen; + input [0:0]S01_AXI_awlock; + input [2:0]S01_AXI_awprot; + input [3:0]S01_AXI_awqos; + output S01_AXI_awready; + input [2:0]S01_AXI_awsize; + input S01_AXI_awvalid; + output [0:0]S01_AXI_bid; + input S01_AXI_bready; + output [1:0]S01_AXI_bresp; + output S01_AXI_bvalid; + output [31:0]S01_AXI_rdata; + output [0:0]S01_AXI_rid; + output S01_AXI_rlast; + input S01_AXI_rready; + output [1:0]S01_AXI_rresp; + output S01_AXI_rvalid; + input [31:0]S01_AXI_wdata; + input S01_AXI_wlast; + output S01_AXI_wready; + input [3:0]S01_AXI_wstrb; + input S01_AXI_wvalid; + + wire M00_ACLK_1; + wire M00_ARESETN_1; + wire S00_ACLK_1; + wire S00_ARESETN_1; + wire S01_ACLK_1; + wire S01_ARESETN_1; + wire [31:0]S01_AXI_1_ARADDR; + wire [1:0]S01_AXI_1_ARBURST; + wire [3:0]S01_AXI_1_ARCACHE; + wire [0:0]S01_AXI_1_ARID; + wire [7:0]S01_AXI_1_ARLEN; + wire [0:0]S01_AXI_1_ARLOCK; + wire [2:0]S01_AXI_1_ARPROT; + wire [3:0]S01_AXI_1_ARQOS; + wire S01_AXI_1_ARREADY; + wire [2:0]S01_AXI_1_ARSIZE; + wire S01_AXI_1_ARVALID; + wire [31:0]S01_AXI_1_AWADDR; + wire [1:0]S01_AXI_1_AWBURST; + wire [3:0]S01_AXI_1_AWCACHE; + wire [0:0]S01_AXI_1_AWID; + wire [7:0]S01_AXI_1_AWLEN; + wire [0:0]S01_AXI_1_AWLOCK; + wire [2:0]S01_AXI_1_AWPROT; + wire [3:0]S01_AXI_1_AWQOS; + wire S01_AXI_1_AWREADY; + wire [2:0]S01_AXI_1_AWSIZE; + wire S01_AXI_1_AWVALID; + wire [0:0]S01_AXI_1_BID; + wire S01_AXI_1_BREADY; + wire [1:0]S01_AXI_1_BRESP; + wire S01_AXI_1_BVALID; + wire [31:0]S01_AXI_1_RDATA; + wire [0:0]S01_AXI_1_RID; + wire S01_AXI_1_RLAST; + wire S01_AXI_1_RREADY; + wire [1:0]S01_AXI_1_RRESP; + wire S01_AXI_1_RVALID; + wire [31:0]S01_AXI_1_WDATA; + wire S01_AXI_1_WLAST; + wire S01_AXI_1_WREADY; + wire [3:0]S01_AXI_1_WSTRB; + wire S01_AXI_1_WVALID; + wire axi_interconnect_0_ACLK_net; + wire axi_interconnect_0_ARESETN_net; + wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR; + wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST; + wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE; + wire [3:0]axi_interconnect_0_to_s00_couplers_ARID; + wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN; + wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK; + wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT; + wire axi_interconnect_0_to_s00_couplers_ARREADY; + wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE; + wire axi_interconnect_0_to_s00_couplers_ARVALID; + wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR; + wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST; + wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE; + wire [3:0]axi_interconnect_0_to_s00_couplers_AWID; + wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN; + wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK; + wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT; + wire axi_interconnect_0_to_s00_couplers_AWREADY; + wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE; + wire axi_interconnect_0_to_s00_couplers_AWVALID; + wire [3:0]axi_interconnect_0_to_s00_couplers_BID; + wire axi_interconnect_0_to_s00_couplers_BREADY; + wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP; + wire axi_interconnect_0_to_s00_couplers_BVALID; + wire [127:0]axi_interconnect_0_to_s00_couplers_RDATA; + wire [3:0]axi_interconnect_0_to_s00_couplers_RID; + wire axi_interconnect_0_to_s00_couplers_RLAST; + wire axi_interconnect_0_to_s00_couplers_RREADY; + wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP; + wire axi_interconnect_0_to_s00_couplers_RVALID; + wire [127:0]axi_interconnect_0_to_s00_couplers_WDATA; + wire axi_interconnect_0_to_s00_couplers_WLAST; + wire axi_interconnect_0_to_s00_couplers_WREADY; + wire [15:0]axi_interconnect_0_to_s00_couplers_WSTRB; + wire axi_interconnect_0_to_s00_couplers_WVALID; + wire [32:0]m00_couplers_to_axi_interconnect_0_ARADDR; + wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST; + wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE; + wire [0:0]m00_couplers_to_axi_interconnect_0_ARID; + wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN; + wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK; + wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT; + wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS; + wire m00_couplers_to_axi_interconnect_0_ARREADY; + wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE; + wire m00_couplers_to_axi_interconnect_0_ARVALID; + wire [32:0]m00_couplers_to_axi_interconnect_0_AWADDR; + wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST; + wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE; + wire [0:0]m00_couplers_to_axi_interconnect_0_AWID; + wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN; + wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK; + wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT; + wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS; + wire m00_couplers_to_axi_interconnect_0_AWREADY; + wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE; + wire m00_couplers_to_axi_interconnect_0_AWVALID; + wire [0:0]m00_couplers_to_axi_interconnect_0_BID; + wire m00_couplers_to_axi_interconnect_0_BREADY; + wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP; + wire m00_couplers_to_axi_interconnect_0_BVALID; + wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA; + wire [0:0]m00_couplers_to_axi_interconnect_0_RID; + wire m00_couplers_to_axi_interconnect_0_RLAST; + wire m00_couplers_to_axi_interconnect_0_RREADY; + wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP; + wire m00_couplers_to_axi_interconnect_0_RVALID; + wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA; + wire m00_couplers_to_axi_interconnect_0_WLAST; + wire m00_couplers_to_axi_interconnect_0_WREADY; + wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB; + wire m00_couplers_to_axi_interconnect_0_WVALID; + wire [63:0]s00_couplers_to_xbar_ARADDR; + wire [1:0]s00_couplers_to_xbar_ARBURST; + wire [3:0]s00_couplers_to_xbar_ARCACHE; + wire [7:0]s00_couplers_to_xbar_ARLEN; + wire [0:0]s00_couplers_to_xbar_ARLOCK; + wire [2:0]s00_couplers_to_xbar_ARPROT; + wire [3:0]s00_couplers_to_xbar_ARQOS; + wire [0:0]s00_couplers_to_xbar_ARREADY; + wire [2:0]s00_couplers_to_xbar_ARSIZE; + wire s00_couplers_to_xbar_ARVALID; + wire [63:0]s00_couplers_to_xbar_AWADDR; + wire [1:0]s00_couplers_to_xbar_AWBURST; + wire [3:0]s00_couplers_to_xbar_AWCACHE; + wire [7:0]s00_couplers_to_xbar_AWLEN; + wire [0:0]s00_couplers_to_xbar_AWLOCK; + wire [2:0]s00_couplers_to_xbar_AWPROT; + wire [3:0]s00_couplers_to_xbar_AWQOS; + wire [0:0]s00_couplers_to_xbar_AWREADY; + wire [2:0]s00_couplers_to_xbar_AWSIZE; + wire s00_couplers_to_xbar_AWVALID; + wire s00_couplers_to_xbar_BREADY; + wire [1:0]s00_couplers_to_xbar_BRESP; + wire [0:0]s00_couplers_to_xbar_BVALID; + wire [511:0]s00_couplers_to_xbar_RDATA; + wire [0:0]s00_couplers_to_xbar_RLAST; + wire s00_couplers_to_xbar_RREADY; + wire [1:0]s00_couplers_to_xbar_RRESP; + wire [0:0]s00_couplers_to_xbar_RVALID; + wire [511:0]s00_couplers_to_xbar_WDATA; + wire s00_couplers_to_xbar_WLAST; + wire [0:0]s00_couplers_to_xbar_WREADY; + wire [63:0]s00_couplers_to_xbar_WSTRB; + wire s00_couplers_to_xbar_WVALID; + wire [31:0]s01_couplers_to_xbar_ARADDR; + wire [1:0]s01_couplers_to_xbar_ARBURST; + wire [3:0]s01_couplers_to_xbar_ARCACHE; + wire [7:0]s01_couplers_to_xbar_ARLEN; + wire [0:0]s01_couplers_to_xbar_ARLOCK; + wire [2:0]s01_couplers_to_xbar_ARPROT; + wire [3:0]s01_couplers_to_xbar_ARQOS; + wire [1:1]s01_couplers_to_xbar_ARREADY; + wire [2:0]s01_couplers_to_xbar_ARSIZE; + wire s01_couplers_to_xbar_ARVALID; + wire [31:0]s01_couplers_to_xbar_AWADDR; + wire [1:0]s01_couplers_to_xbar_AWBURST; + wire [3:0]s01_couplers_to_xbar_AWCACHE; + wire [7:0]s01_couplers_to_xbar_AWLEN; + wire [0:0]s01_couplers_to_xbar_AWLOCK; + wire [2:0]s01_couplers_to_xbar_AWPROT; + wire [3:0]s01_couplers_to_xbar_AWQOS; + wire [1:1]s01_couplers_to_xbar_AWREADY; + wire [2:0]s01_couplers_to_xbar_AWSIZE; + wire s01_couplers_to_xbar_AWVALID; + wire s01_couplers_to_xbar_BREADY; + wire [3:2]s01_couplers_to_xbar_BRESP; + wire [1:1]s01_couplers_to_xbar_BVALID; + wire [1023:512]s01_couplers_to_xbar_RDATA; + wire [1:1]s01_couplers_to_xbar_RLAST; + wire s01_couplers_to_xbar_RREADY; + wire [3:2]s01_couplers_to_xbar_RRESP; + wire [1:1]s01_couplers_to_xbar_RVALID; + wire [511:0]s01_couplers_to_xbar_WDATA; + wire s01_couplers_to_xbar_WLAST; + wire [1:1]s01_couplers_to_xbar_WREADY; + wire [63:0]s01_couplers_to_xbar_WSTRB; + wire s01_couplers_to_xbar_WVALID; + wire [31:0]s01_mmu_M_AXI_ARADDR; + wire [1:0]s01_mmu_M_AXI_ARBURST; + wire [3:0]s01_mmu_M_AXI_ARCACHE; + wire [0:0]s01_mmu_M_AXI_ARID; + wire [7:0]s01_mmu_M_AXI_ARLEN; + wire [0:0]s01_mmu_M_AXI_ARLOCK; + wire [2:0]s01_mmu_M_AXI_ARPROT; + wire [3:0]s01_mmu_M_AXI_ARQOS; + wire s01_mmu_M_AXI_ARREADY; + wire [2:0]s01_mmu_M_AXI_ARSIZE; + wire s01_mmu_M_AXI_ARVALID; + wire [31:0]s01_mmu_M_AXI_AWADDR; + wire [1:0]s01_mmu_M_AXI_AWBURST; + wire [3:0]s01_mmu_M_AXI_AWCACHE; + wire [0:0]s01_mmu_M_AXI_AWID; + wire [7:0]s01_mmu_M_AXI_AWLEN; + wire [0:0]s01_mmu_M_AXI_AWLOCK; + wire [2:0]s01_mmu_M_AXI_AWPROT; + wire [3:0]s01_mmu_M_AXI_AWQOS; + wire s01_mmu_M_AXI_AWREADY; + wire [2:0]s01_mmu_M_AXI_AWSIZE; + wire s01_mmu_M_AXI_AWVALID; + wire [0:0]s01_mmu_M_AXI_BID; + wire s01_mmu_M_AXI_BREADY; + wire [1:0]s01_mmu_M_AXI_BRESP; + wire s01_mmu_M_AXI_BVALID; + wire [31:0]s01_mmu_M_AXI_RDATA; + wire [0:0]s01_mmu_M_AXI_RID; + wire s01_mmu_M_AXI_RLAST; + wire s01_mmu_M_AXI_RREADY; + wire [1:0]s01_mmu_M_AXI_RRESP; + wire s01_mmu_M_AXI_RVALID; + wire [31:0]s01_mmu_M_AXI_WDATA; + wire s01_mmu_M_AXI_WLAST; + wire s01_mmu_M_AXI_WREADY; + wire [3:0]s01_mmu_M_AXI_WSTRB; + wire s01_mmu_M_AXI_WVALID; + wire [63:0]xbar_to_m00_couplers_ARADDR; + wire [1:0]xbar_to_m00_couplers_ARBURST; + wire [3:0]xbar_to_m00_couplers_ARCACHE; + wire [0:0]xbar_to_m00_couplers_ARID; + wire [7:0]xbar_to_m00_couplers_ARLEN; + wire [0:0]xbar_to_m00_couplers_ARLOCK; + wire [2:0]xbar_to_m00_couplers_ARPROT; + wire [3:0]xbar_to_m00_couplers_ARQOS; + wire xbar_to_m00_couplers_ARREADY; + wire [3:0]xbar_to_m00_couplers_ARREGION; + wire [2:0]xbar_to_m00_couplers_ARSIZE; + wire [0:0]xbar_to_m00_couplers_ARVALID; + wire [63:0]xbar_to_m00_couplers_AWADDR; + wire [1:0]xbar_to_m00_couplers_AWBURST; + wire [3:0]xbar_to_m00_couplers_AWCACHE; + wire [0:0]xbar_to_m00_couplers_AWID; + wire [7:0]xbar_to_m00_couplers_AWLEN; + wire [0:0]xbar_to_m00_couplers_AWLOCK; + wire [2:0]xbar_to_m00_couplers_AWPROT; + wire [3:0]xbar_to_m00_couplers_AWQOS; + wire xbar_to_m00_couplers_AWREADY; + wire [3:0]xbar_to_m00_couplers_AWREGION; + wire [2:0]xbar_to_m00_couplers_AWSIZE; + wire [0:0]xbar_to_m00_couplers_AWVALID; + wire [0:0]xbar_to_m00_couplers_BID; + wire [0:0]xbar_to_m00_couplers_BREADY; + wire [1:0]xbar_to_m00_couplers_BRESP; + wire xbar_to_m00_couplers_BVALID; + wire [511:0]xbar_to_m00_couplers_RDATA; + wire [0:0]xbar_to_m00_couplers_RID; + wire xbar_to_m00_couplers_RLAST; + wire [0:0]xbar_to_m00_couplers_RREADY; + wire [1:0]xbar_to_m00_couplers_RRESP; + wire xbar_to_m00_couplers_RVALID; + wire [511:0]xbar_to_m00_couplers_WDATA; + wire [0:0]xbar_to_m00_couplers_WLAST; + wire xbar_to_m00_couplers_WREADY; + wire [63:0]xbar_to_m00_couplers_WSTRB; + wire [0:0]xbar_to_m00_couplers_WVALID; + + assign M00_ACLK_1 = M00_ACLK; + assign M00_ARESETN_1 = M00_ARESETN; + assign M00_AXI_araddr[32:0] = m00_couplers_to_axi_interconnect_0_ARADDR; + assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST; + assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE; + assign M00_AXI_arid[0] = m00_couplers_to_axi_interconnect_0_ARID; + assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN; + assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK; + assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT; + assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS; + assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE; + assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID; + assign M00_AXI_awaddr[32:0] = m00_couplers_to_axi_interconnect_0_AWADDR; + assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST; + assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE; + assign M00_AXI_awid[0] = m00_couplers_to_axi_interconnect_0_AWID; + assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN; + assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK; + assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT; + assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS; + assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE; + assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID; + assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY; + assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY; + assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA; + assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST; + assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB; + assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID; + assign S00_ACLK_1 = S00_ACLK; + assign S00_ARESETN_1 = S00_ARESETN; + assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY; + assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY; + assign S00_AXI_bid[3:0] = axi_interconnect_0_to_s00_couplers_BID; + assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP; + assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID; + assign S00_AXI_rdata[127:0] = axi_interconnect_0_to_s00_couplers_RDATA; + assign S00_AXI_rid[3:0] = axi_interconnect_0_to_s00_couplers_RID; + assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST; + assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP; + assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID; + assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY; + assign S01_ACLK_1 = S01_ACLK; + assign S01_ARESETN_1 = S01_ARESETN; + assign S01_AXI_1_ARADDR = S01_AXI_araddr[31:0]; + assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0]; + assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0]; + assign S01_AXI_1_ARID = S01_AXI_arid[0]; + assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0]; + assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0]; + assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0]; + assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0]; + assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0]; + assign S01_AXI_1_ARVALID = S01_AXI_arvalid; + assign S01_AXI_1_AWADDR = S01_AXI_awaddr[31:0]; + assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0]; + assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0]; + assign S01_AXI_1_AWID = S01_AXI_awid[0]; + assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0]; + assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0]; + assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0]; + assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0]; + assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0]; + assign S01_AXI_1_AWVALID = S01_AXI_awvalid; + assign S01_AXI_1_BREADY = S01_AXI_bready; + assign S01_AXI_1_RREADY = S01_AXI_rready; + assign S01_AXI_1_WDATA = S01_AXI_wdata[31:0]; + assign S01_AXI_1_WLAST = S01_AXI_wlast; + assign S01_AXI_1_WSTRB = S01_AXI_wstrb[3:0]; + assign S01_AXI_1_WVALID = S01_AXI_wvalid; + assign S01_AXI_arready = S01_AXI_1_ARREADY; + assign S01_AXI_awready = S01_AXI_1_AWREADY; + assign S01_AXI_bid[0] = S01_AXI_1_BID; + assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP; + assign S01_AXI_bvalid = S01_AXI_1_BVALID; + assign S01_AXI_rdata[31:0] = S01_AXI_1_RDATA; + assign S01_AXI_rid[0] = S01_AXI_1_RID; + assign S01_AXI_rlast = S01_AXI_1_RLAST; + assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP; + assign S01_AXI_rvalid = S01_AXI_1_RVALID; + assign S01_AXI_wready = S01_AXI_1_WREADY; + assign axi_interconnect_0_ACLK_net = ACLK; + assign axi_interconnect_0_ARESETN_net = ARESETN; + assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0]; + assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0]; + assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0]; + assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[3:0]; + assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0]; + assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0]; + assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0]; + assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0]; + assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid; + assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0]; + assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0]; + assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0]; + assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[3:0]; + assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0]; + assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0]; + assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0]; + assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0]; + assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid; + assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready; + assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready; + assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[127:0]; + assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast; + assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[15:0]; + assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid; + assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready; + assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready; + assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[0]; + assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0]; + assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid; + assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0]; + assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[0]; + assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast; + assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0]; + assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid; + assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready; + m00_couplers_imp_1FLA7NN m00_couplers + (.M_ACLK(M00_ACLK_1), + .M_ARESETN(M00_ARESETN_1), + .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR), + .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST), + .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE), + .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID), + .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN), + .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK), + .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT), + .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS), + .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY), + .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE), + .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID), + .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR), + .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST), + .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE), + .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID), + .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN), + .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK), + .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT), + .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS), + .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY), + .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE), + .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID), + .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID), + .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY), + .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP), + .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID), + .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA), + .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID), + .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST), + .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY), + .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP), + .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID), + .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA), + .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST), + .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY), + .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB), + .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID), + .S_ACLK(axi_interconnect_0_ACLK_net), + .S_ARESETN(axi_interconnect_0_ARESETN_net), + .S_AXI_araddr(xbar_to_m00_couplers_ARADDR), + .S_AXI_arburst(xbar_to_m00_couplers_ARBURST), + .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE), + .S_AXI_arid(xbar_to_m00_couplers_ARID), + .S_AXI_arlen(xbar_to_m00_couplers_ARLEN), + .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK), + .S_AXI_arprot(xbar_to_m00_couplers_ARPROT), + .S_AXI_arqos(xbar_to_m00_couplers_ARQOS), + .S_AXI_arready(xbar_to_m00_couplers_ARREADY), + .S_AXI_arregion(xbar_to_m00_couplers_ARREGION), + .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE), + .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID), + .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR), + .S_AXI_awburst(xbar_to_m00_couplers_AWBURST), + .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE), + .S_AXI_awid(xbar_to_m00_couplers_AWID), + .S_AXI_awlen(xbar_to_m00_couplers_AWLEN), + .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK), + .S_AXI_awprot(xbar_to_m00_couplers_AWPROT), + .S_AXI_awqos(xbar_to_m00_couplers_AWQOS), + .S_AXI_awready(xbar_to_m00_couplers_AWREADY), + .S_AXI_awregion(xbar_to_m00_couplers_AWREGION), + .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE), + .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID), + .S_AXI_bid(xbar_to_m00_couplers_BID), + .S_AXI_bready(xbar_to_m00_couplers_BREADY), + .S_AXI_bresp(xbar_to_m00_couplers_BRESP), + .S_AXI_bvalid(xbar_to_m00_couplers_BVALID), + .S_AXI_rdata(xbar_to_m00_couplers_RDATA), + .S_AXI_rid(xbar_to_m00_couplers_RID), + .S_AXI_rlast(xbar_to_m00_couplers_RLAST), + .S_AXI_rready(xbar_to_m00_couplers_RREADY), + .S_AXI_rresp(xbar_to_m00_couplers_RRESP), + .S_AXI_rvalid(xbar_to_m00_couplers_RVALID), + .S_AXI_wdata(xbar_to_m00_couplers_WDATA), + .S_AXI_wlast(xbar_to_m00_couplers_WLAST), + .S_AXI_wready(xbar_to_m00_couplers_WREADY), + .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB), + .S_AXI_wvalid(xbar_to_m00_couplers_WVALID)); + s00_couplers_imp_HZCGLD s00_couplers + (.M_ACLK(axi_interconnect_0_ACLK_net), + .M_ARESETN(axi_interconnect_0_ARESETN_net), + .M_AXI_araddr(s00_couplers_to_xbar_ARADDR), + .M_AXI_arburst(s00_couplers_to_xbar_ARBURST), + .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE), + .M_AXI_arlen(s00_couplers_to_xbar_ARLEN), + .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK), + .M_AXI_arprot(s00_couplers_to_xbar_ARPROT), + .M_AXI_arqos(s00_couplers_to_xbar_ARQOS), + .M_AXI_arready(s00_couplers_to_xbar_ARREADY), + .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE), + .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID), + .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR), + .M_AXI_awburst(s00_couplers_to_xbar_AWBURST), + .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE), + .M_AXI_awlen(s00_couplers_to_xbar_AWLEN), + .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK), + .M_AXI_awprot(s00_couplers_to_xbar_AWPROT), + .M_AXI_awqos(s00_couplers_to_xbar_AWQOS), + .M_AXI_awready(s00_couplers_to_xbar_AWREADY), + .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE), + .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID), + .M_AXI_bready(s00_couplers_to_xbar_BREADY), + .M_AXI_bresp(s00_couplers_to_xbar_BRESP), + .M_AXI_bvalid(s00_couplers_to_xbar_BVALID), + .M_AXI_rdata(s00_couplers_to_xbar_RDATA), + .M_AXI_rlast(s00_couplers_to_xbar_RLAST), + .M_AXI_rready(s00_couplers_to_xbar_RREADY), + .M_AXI_rresp(s00_couplers_to_xbar_RRESP), + .M_AXI_rvalid(s00_couplers_to_xbar_RVALID), + .M_AXI_wdata(s00_couplers_to_xbar_WDATA), + .M_AXI_wlast(s00_couplers_to_xbar_WLAST), + .M_AXI_wready(s00_couplers_to_xbar_WREADY), + .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB), + .M_AXI_wvalid(s00_couplers_to_xbar_WVALID), + .S_ACLK(S00_ACLK_1), + .S_ARESETN(S00_ARESETN_1), + .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR), + .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST), + .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE), + .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID), + .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN), + .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK), + .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT), + .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY), + .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE), + .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID), + .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR), + .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST), + .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE), + .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID), + .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN), + .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK), + .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT), + .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY), + .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE), + .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID), + .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID), + .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY), + .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP), + .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID), + .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA), + .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID), + .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST), + .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY), + .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP), + .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID), + .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA), + .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST), + .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY), + .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB), + .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID)); + s01_couplers_imp_1CQ4OV4 s01_couplers + (.M_ACLK(axi_interconnect_0_ACLK_net), + .M_ARESETN(axi_interconnect_0_ARESETN_net), + .M_AXI_araddr(s01_couplers_to_xbar_ARADDR), + .M_AXI_arburst(s01_couplers_to_xbar_ARBURST), + .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE), + .M_AXI_arlen(s01_couplers_to_xbar_ARLEN), + .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK), + .M_AXI_arprot(s01_couplers_to_xbar_ARPROT), + .M_AXI_arqos(s01_couplers_to_xbar_ARQOS), + .M_AXI_arready(s01_couplers_to_xbar_ARREADY), + .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE), + .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID), + .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR), + .M_AXI_awburst(s01_couplers_to_xbar_AWBURST), + .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE), + .M_AXI_awlen(s01_couplers_to_xbar_AWLEN), + .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK), + .M_AXI_awprot(s01_couplers_to_xbar_AWPROT), + .M_AXI_awqos(s01_couplers_to_xbar_AWQOS), + .M_AXI_awready(s01_couplers_to_xbar_AWREADY), + .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE), + .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID), + .M_AXI_bready(s01_couplers_to_xbar_BREADY), + .M_AXI_bresp(s01_couplers_to_xbar_BRESP), + .M_AXI_bvalid(s01_couplers_to_xbar_BVALID), + .M_AXI_rdata(s01_couplers_to_xbar_RDATA), + .M_AXI_rlast(s01_couplers_to_xbar_RLAST), + .M_AXI_rready(s01_couplers_to_xbar_RREADY), + .M_AXI_rresp(s01_couplers_to_xbar_RRESP), + .M_AXI_rvalid(s01_couplers_to_xbar_RVALID), + .M_AXI_wdata(s01_couplers_to_xbar_WDATA), + .M_AXI_wlast(s01_couplers_to_xbar_WLAST), + .M_AXI_wready(s01_couplers_to_xbar_WREADY), + .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB), + .M_AXI_wvalid(s01_couplers_to_xbar_WVALID), + .S_ACLK(S01_ACLK_1), + .S_ARESETN(S01_ARESETN_1), + .S_AXI_araddr(s01_mmu_M_AXI_ARADDR), + .S_AXI_arburst(s01_mmu_M_AXI_ARBURST), + .S_AXI_arcache(s01_mmu_M_AXI_ARCACHE), + .S_AXI_arid(s01_mmu_M_AXI_ARID), + .S_AXI_arlen(s01_mmu_M_AXI_ARLEN), + .S_AXI_arlock(s01_mmu_M_AXI_ARLOCK), + .S_AXI_arprot(s01_mmu_M_AXI_ARPROT), + .S_AXI_arqos(s01_mmu_M_AXI_ARQOS), + .S_AXI_arready(s01_mmu_M_AXI_ARREADY), + .S_AXI_arsize(s01_mmu_M_AXI_ARSIZE), + .S_AXI_arvalid(s01_mmu_M_AXI_ARVALID), + .S_AXI_awaddr(s01_mmu_M_AXI_AWADDR), + .S_AXI_awburst(s01_mmu_M_AXI_AWBURST), + .S_AXI_awcache(s01_mmu_M_AXI_AWCACHE), + .S_AXI_awid(s01_mmu_M_AXI_AWID), + .S_AXI_awlen(s01_mmu_M_AXI_AWLEN), + .S_AXI_awlock(s01_mmu_M_AXI_AWLOCK), + .S_AXI_awprot(s01_mmu_M_AXI_AWPROT), + .S_AXI_awqos(s01_mmu_M_AXI_AWQOS), + .S_AXI_awready(s01_mmu_M_AXI_AWREADY), + .S_AXI_awsize(s01_mmu_M_AXI_AWSIZE), + .S_AXI_awvalid(s01_mmu_M_AXI_AWVALID), + .S_AXI_bid(s01_mmu_M_AXI_BID), + .S_AXI_bready(s01_mmu_M_AXI_BREADY), + .S_AXI_bresp(s01_mmu_M_AXI_BRESP), + .S_AXI_bvalid(s01_mmu_M_AXI_BVALID), + .S_AXI_rdata(s01_mmu_M_AXI_RDATA), + .S_AXI_rid(s01_mmu_M_AXI_RID), + .S_AXI_rlast(s01_mmu_M_AXI_RLAST), + .S_AXI_rready(s01_mmu_M_AXI_RREADY), + .S_AXI_rresp(s01_mmu_M_AXI_RRESP), + .S_AXI_rvalid(s01_mmu_M_AXI_RVALID), + .S_AXI_wdata(s01_mmu_M_AXI_WDATA), + .S_AXI_wlast(s01_mmu_M_AXI_WLAST), + .S_AXI_wready(s01_mmu_M_AXI_WREADY), + .S_AXI_wstrb(s01_mmu_M_AXI_WSTRB), + .S_AXI_wvalid(s01_mmu_M_AXI_WVALID)); + pcie_ddr_s01_mmu_1 s01_mmu + (.aclk(S01_ACLK_1), + .aresetn(S01_ARESETN_1), + .m_axi_araddr(s01_mmu_M_AXI_ARADDR), + .m_axi_arburst(s01_mmu_M_AXI_ARBURST), + .m_axi_arcache(s01_mmu_M_AXI_ARCACHE), + .m_axi_arid(s01_mmu_M_AXI_ARID), + .m_axi_arlen(s01_mmu_M_AXI_ARLEN), + .m_axi_arlock(s01_mmu_M_AXI_ARLOCK), + .m_axi_arprot(s01_mmu_M_AXI_ARPROT), + .m_axi_arqos(s01_mmu_M_AXI_ARQOS), + .m_axi_arready(s01_mmu_M_AXI_ARREADY), + .m_axi_arsize(s01_mmu_M_AXI_ARSIZE), + .m_axi_arvalid(s01_mmu_M_AXI_ARVALID), + .m_axi_awaddr(s01_mmu_M_AXI_AWADDR), + .m_axi_awburst(s01_mmu_M_AXI_AWBURST), + .m_axi_awcache(s01_mmu_M_AXI_AWCACHE), + .m_axi_awid(s01_mmu_M_AXI_AWID), + .m_axi_awlen(s01_mmu_M_AXI_AWLEN), + .m_axi_awlock(s01_mmu_M_AXI_AWLOCK), + .m_axi_awprot(s01_mmu_M_AXI_AWPROT), + .m_axi_awqos(s01_mmu_M_AXI_AWQOS), + .m_axi_awready(s01_mmu_M_AXI_AWREADY), + .m_axi_awsize(s01_mmu_M_AXI_AWSIZE), + .m_axi_awvalid(s01_mmu_M_AXI_AWVALID), + .m_axi_bid(s01_mmu_M_AXI_BID), + .m_axi_bready(s01_mmu_M_AXI_BREADY), + .m_axi_bresp(s01_mmu_M_AXI_BRESP), + .m_axi_bvalid(s01_mmu_M_AXI_BVALID), + .m_axi_rdata(s01_mmu_M_AXI_RDATA), + .m_axi_rid(s01_mmu_M_AXI_RID), + .m_axi_rlast(s01_mmu_M_AXI_RLAST), + .m_axi_rready(s01_mmu_M_AXI_RREADY), + .m_axi_rresp(s01_mmu_M_AXI_RRESP), + .m_axi_rvalid(s01_mmu_M_AXI_RVALID), + .m_axi_wdata(s01_mmu_M_AXI_WDATA), + .m_axi_wlast(s01_mmu_M_AXI_WLAST), + .m_axi_wready(s01_mmu_M_AXI_WREADY), + .m_axi_wstrb(s01_mmu_M_AXI_WSTRB), + .m_axi_wvalid(s01_mmu_M_AXI_WVALID), + .s_axi_araddr(S01_AXI_1_ARADDR), + .s_axi_arburst(S01_AXI_1_ARBURST), + .s_axi_arcache(S01_AXI_1_ARCACHE), + .s_axi_arid(S01_AXI_1_ARID), + .s_axi_arlen(S01_AXI_1_ARLEN), + .s_axi_arlock(S01_AXI_1_ARLOCK), + .s_axi_arprot(S01_AXI_1_ARPROT), + .s_axi_arqos(S01_AXI_1_ARQOS), + .s_axi_arready(S01_AXI_1_ARREADY), + .s_axi_arsize(S01_AXI_1_ARSIZE), + .s_axi_arvalid(S01_AXI_1_ARVALID), + .s_axi_awaddr(S01_AXI_1_AWADDR), + .s_axi_awburst(S01_AXI_1_AWBURST), + .s_axi_awcache(S01_AXI_1_AWCACHE), + .s_axi_awid(S01_AXI_1_AWID), + .s_axi_awlen(S01_AXI_1_AWLEN), + .s_axi_awlock(S01_AXI_1_AWLOCK), + .s_axi_awprot(S01_AXI_1_AWPROT), + .s_axi_awqos(S01_AXI_1_AWQOS), + .s_axi_awready(S01_AXI_1_AWREADY), + .s_axi_awsize(S01_AXI_1_AWSIZE), + .s_axi_awvalid(S01_AXI_1_AWVALID), + .s_axi_bid(S01_AXI_1_BID), + .s_axi_bready(S01_AXI_1_BREADY), + .s_axi_bresp(S01_AXI_1_BRESP), + .s_axi_bvalid(S01_AXI_1_BVALID), + .s_axi_rdata(S01_AXI_1_RDATA), + .s_axi_rid(S01_AXI_1_RID), + .s_axi_rlast(S01_AXI_1_RLAST), + .s_axi_rready(S01_AXI_1_RREADY), + .s_axi_rresp(S01_AXI_1_RRESP), + .s_axi_rvalid(S01_AXI_1_RVALID), + .s_axi_wdata(S01_AXI_1_WDATA), + .s_axi_wlast(S01_AXI_1_WLAST), + .s_axi_wready(S01_AXI_1_WREADY), + .s_axi_wstrb(S01_AXI_1_WSTRB), + .s_axi_wvalid(S01_AXI_1_WVALID)); + pcie_ddr_xbar_1 xbar + (.aclk(axi_interconnect_0_ACLK_net), + .aresetn(axi_interconnect_0_ARESETN_net), + .m_axi_araddr(xbar_to_m00_couplers_ARADDR), + .m_axi_arburst(xbar_to_m00_couplers_ARBURST), + .m_axi_arcache(xbar_to_m00_couplers_ARCACHE), + .m_axi_arid(xbar_to_m00_couplers_ARID), + .m_axi_arlen(xbar_to_m00_couplers_ARLEN), + .m_axi_arlock(xbar_to_m00_couplers_ARLOCK), + .m_axi_arprot(xbar_to_m00_couplers_ARPROT), + .m_axi_arqos(xbar_to_m00_couplers_ARQOS), + .m_axi_arready(xbar_to_m00_couplers_ARREADY), + .m_axi_arregion(xbar_to_m00_couplers_ARREGION), + .m_axi_arsize(xbar_to_m00_couplers_ARSIZE), + .m_axi_arvalid(xbar_to_m00_couplers_ARVALID), + .m_axi_awaddr(xbar_to_m00_couplers_AWADDR), + .m_axi_awburst(xbar_to_m00_couplers_AWBURST), + .m_axi_awcache(xbar_to_m00_couplers_AWCACHE), + .m_axi_awid(xbar_to_m00_couplers_AWID), + .m_axi_awlen(xbar_to_m00_couplers_AWLEN), + .m_axi_awlock(xbar_to_m00_couplers_AWLOCK), + .m_axi_awprot(xbar_to_m00_couplers_AWPROT), + .m_axi_awqos(xbar_to_m00_couplers_AWQOS), + .m_axi_awready(xbar_to_m00_couplers_AWREADY), + .m_axi_awregion(xbar_to_m00_couplers_AWREGION), + .m_axi_awsize(xbar_to_m00_couplers_AWSIZE), + .m_axi_awvalid(xbar_to_m00_couplers_AWVALID), + .m_axi_bid(xbar_to_m00_couplers_BID), + .m_axi_bready(xbar_to_m00_couplers_BREADY), + .m_axi_bresp(xbar_to_m00_couplers_BRESP), + .m_axi_bvalid(xbar_to_m00_couplers_BVALID), + .m_axi_rdata(xbar_to_m00_couplers_RDATA), + .m_axi_rid(xbar_to_m00_couplers_RID), + .m_axi_rlast(xbar_to_m00_couplers_RLAST), + .m_axi_rready(xbar_to_m00_couplers_RREADY), + .m_axi_rresp(xbar_to_m00_couplers_RRESP), + .m_axi_rvalid(xbar_to_m00_couplers_RVALID), + .m_axi_wdata(xbar_to_m00_couplers_WDATA), + .m_axi_wlast(xbar_to_m00_couplers_WLAST), + .m_axi_wready(xbar_to_m00_couplers_WREADY), + .m_axi_wstrb(xbar_to_m00_couplers_WSTRB), + .m_axi_wvalid(xbar_to_m00_couplers_WVALID), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}), + .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}), + .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}), + .s_axi_arid({1'b0,1'b0}), + .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}), + .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}), + .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}), + .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}), + .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}), + .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}), + .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}), + .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}), + .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}), + .s_axi_awid({1'b0,1'b0}), + .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}), + .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}), + .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}), + .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}), + .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}), + .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}), + .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}), + .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}), + .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}), + .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}), + .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}), + .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}), + .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}), + .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}), + .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}), + .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}), + .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}), + .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}), + .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}), + .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID})); +endmodule + +module s00_couplers_imp_HZCGLD + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [63:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [7:0]M_AXI_arlen; + output [0:0]M_AXI_arlock; + output [2:0]M_AXI_arprot; + output [3:0]M_AXI_arqos; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [63:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [7:0]M_AXI_awlen; + output [0:0]M_AXI_awlock; + output [2:0]M_AXI_awprot; + output [3:0]M_AXI_awqos; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [511:0]M_AXI_rdata; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [511:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [63:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [63:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [3:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + output S_AXI_arready; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [63:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [3:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + output S_AXI_awready; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [3:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [127:0]S_AXI_rdata; + output [3:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [127:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [15:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire M_ACLK_1; + wire M_ARESETN_1; + wire S_ACLK_1; + wire S_ARESETN_1; + wire [63:0]auto_cc_to_s00_couplers_ARADDR; + wire [1:0]auto_cc_to_s00_couplers_ARBURST; + wire [3:0]auto_cc_to_s00_couplers_ARCACHE; + wire [7:0]auto_cc_to_s00_couplers_ARLEN; + wire [0:0]auto_cc_to_s00_couplers_ARLOCK; + wire [2:0]auto_cc_to_s00_couplers_ARPROT; + wire [3:0]auto_cc_to_s00_couplers_ARQOS; + wire auto_cc_to_s00_couplers_ARREADY; + wire [2:0]auto_cc_to_s00_couplers_ARSIZE; + wire auto_cc_to_s00_couplers_ARVALID; + wire [63:0]auto_cc_to_s00_couplers_AWADDR; + wire [1:0]auto_cc_to_s00_couplers_AWBURST; + wire [3:0]auto_cc_to_s00_couplers_AWCACHE; + wire [7:0]auto_cc_to_s00_couplers_AWLEN; + wire [0:0]auto_cc_to_s00_couplers_AWLOCK; + wire [2:0]auto_cc_to_s00_couplers_AWPROT; + wire [3:0]auto_cc_to_s00_couplers_AWQOS; + wire auto_cc_to_s00_couplers_AWREADY; + wire [2:0]auto_cc_to_s00_couplers_AWSIZE; + wire auto_cc_to_s00_couplers_AWVALID; + wire auto_cc_to_s00_couplers_BREADY; + wire [1:0]auto_cc_to_s00_couplers_BRESP; + wire auto_cc_to_s00_couplers_BVALID; + wire [511:0]auto_cc_to_s00_couplers_RDATA; + wire auto_cc_to_s00_couplers_RLAST; + wire auto_cc_to_s00_couplers_RREADY; + wire [1:0]auto_cc_to_s00_couplers_RRESP; + wire auto_cc_to_s00_couplers_RVALID; + wire [511:0]auto_cc_to_s00_couplers_WDATA; + wire auto_cc_to_s00_couplers_WLAST; + wire auto_cc_to_s00_couplers_WREADY; + wire [63:0]auto_cc_to_s00_couplers_WSTRB; + wire auto_cc_to_s00_couplers_WVALID; + wire [63:0]auto_us_to_auto_cc_ARADDR; + wire [1:0]auto_us_to_auto_cc_ARBURST; + wire [3:0]auto_us_to_auto_cc_ARCACHE; + wire [7:0]auto_us_to_auto_cc_ARLEN; + wire [0:0]auto_us_to_auto_cc_ARLOCK; + wire [2:0]auto_us_to_auto_cc_ARPROT; + wire [3:0]auto_us_to_auto_cc_ARQOS; + wire auto_us_to_auto_cc_ARREADY; + wire [3:0]auto_us_to_auto_cc_ARREGION; + wire [2:0]auto_us_to_auto_cc_ARSIZE; + wire auto_us_to_auto_cc_ARVALID; + wire [63:0]auto_us_to_auto_cc_AWADDR; + wire [1:0]auto_us_to_auto_cc_AWBURST; + wire [3:0]auto_us_to_auto_cc_AWCACHE; + wire [7:0]auto_us_to_auto_cc_AWLEN; + wire [0:0]auto_us_to_auto_cc_AWLOCK; + wire [2:0]auto_us_to_auto_cc_AWPROT; + wire [3:0]auto_us_to_auto_cc_AWQOS; + wire auto_us_to_auto_cc_AWREADY; + wire [3:0]auto_us_to_auto_cc_AWREGION; + wire [2:0]auto_us_to_auto_cc_AWSIZE; + wire auto_us_to_auto_cc_AWVALID; + wire auto_us_to_auto_cc_BREADY; + wire [1:0]auto_us_to_auto_cc_BRESP; + wire auto_us_to_auto_cc_BVALID; + wire [511:0]auto_us_to_auto_cc_RDATA; + wire auto_us_to_auto_cc_RLAST; + wire auto_us_to_auto_cc_RREADY; + wire [1:0]auto_us_to_auto_cc_RRESP; + wire auto_us_to_auto_cc_RVALID; + wire [511:0]auto_us_to_auto_cc_WDATA; + wire auto_us_to_auto_cc_WLAST; + wire auto_us_to_auto_cc_WREADY; + wire [63:0]auto_us_to_auto_cc_WSTRB; + wire auto_us_to_auto_cc_WVALID; + wire [63:0]s00_couplers_to_auto_us_ARADDR; + wire [1:0]s00_couplers_to_auto_us_ARBURST; + wire [3:0]s00_couplers_to_auto_us_ARCACHE; + wire [3:0]s00_couplers_to_auto_us_ARID; + wire [7:0]s00_couplers_to_auto_us_ARLEN; + wire [0:0]s00_couplers_to_auto_us_ARLOCK; + wire [2:0]s00_couplers_to_auto_us_ARPROT; + wire s00_couplers_to_auto_us_ARREADY; + wire [2:0]s00_couplers_to_auto_us_ARSIZE; + wire s00_couplers_to_auto_us_ARVALID; + wire [63:0]s00_couplers_to_auto_us_AWADDR; + wire [1:0]s00_couplers_to_auto_us_AWBURST; + wire [3:0]s00_couplers_to_auto_us_AWCACHE; + wire [3:0]s00_couplers_to_auto_us_AWID; + wire [7:0]s00_couplers_to_auto_us_AWLEN; + wire [0:0]s00_couplers_to_auto_us_AWLOCK; + wire [2:0]s00_couplers_to_auto_us_AWPROT; + wire s00_couplers_to_auto_us_AWREADY; + wire [2:0]s00_couplers_to_auto_us_AWSIZE; + wire s00_couplers_to_auto_us_AWVALID; + wire [3:0]s00_couplers_to_auto_us_BID; + wire s00_couplers_to_auto_us_BREADY; + wire [1:0]s00_couplers_to_auto_us_BRESP; + wire s00_couplers_to_auto_us_BVALID; + wire [127:0]s00_couplers_to_auto_us_RDATA; + wire [3:0]s00_couplers_to_auto_us_RID; + wire s00_couplers_to_auto_us_RLAST; + wire s00_couplers_to_auto_us_RREADY; + wire [1:0]s00_couplers_to_auto_us_RRESP; + wire s00_couplers_to_auto_us_RVALID; + wire [127:0]s00_couplers_to_auto_us_WDATA; + wire s00_couplers_to_auto_us_WLAST; + wire s00_couplers_to_auto_us_WREADY; + wire [15:0]s00_couplers_to_auto_us_WSTRB; + wire s00_couplers_to_auto_us_WVALID; + + assign M_ACLK_1 = M_ACLK; + assign M_ARESETN_1 = M_ARESETN; + assign M_AXI_araddr[63:0] = auto_cc_to_s00_couplers_ARADDR; + assign M_AXI_arburst[1:0] = auto_cc_to_s00_couplers_ARBURST; + assign M_AXI_arcache[3:0] = auto_cc_to_s00_couplers_ARCACHE; + assign M_AXI_arlen[7:0] = auto_cc_to_s00_couplers_ARLEN; + assign M_AXI_arlock[0] = auto_cc_to_s00_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = auto_cc_to_s00_couplers_ARPROT; + assign M_AXI_arqos[3:0] = auto_cc_to_s00_couplers_ARQOS; + assign M_AXI_arsize[2:0] = auto_cc_to_s00_couplers_ARSIZE; + assign M_AXI_arvalid = auto_cc_to_s00_couplers_ARVALID; + assign M_AXI_awaddr[63:0] = auto_cc_to_s00_couplers_AWADDR; + assign M_AXI_awburst[1:0] = auto_cc_to_s00_couplers_AWBURST; + assign M_AXI_awcache[3:0] = auto_cc_to_s00_couplers_AWCACHE; + assign M_AXI_awlen[7:0] = auto_cc_to_s00_couplers_AWLEN; + assign M_AXI_awlock[0] = auto_cc_to_s00_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = auto_cc_to_s00_couplers_AWPROT; + assign M_AXI_awqos[3:0] = auto_cc_to_s00_couplers_AWQOS; + assign M_AXI_awsize[2:0] = auto_cc_to_s00_couplers_AWSIZE; + assign M_AXI_awvalid = auto_cc_to_s00_couplers_AWVALID; + assign M_AXI_bready = auto_cc_to_s00_couplers_BREADY; + assign M_AXI_rready = auto_cc_to_s00_couplers_RREADY; + assign M_AXI_wdata[511:0] = auto_cc_to_s00_couplers_WDATA; + assign M_AXI_wlast = auto_cc_to_s00_couplers_WLAST; + assign M_AXI_wstrb[63:0] = auto_cc_to_s00_couplers_WSTRB; + assign M_AXI_wvalid = auto_cc_to_s00_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = s00_couplers_to_auto_us_ARREADY; + assign S_AXI_awready = s00_couplers_to_auto_us_AWREADY; + assign S_AXI_bid[3:0] = s00_couplers_to_auto_us_BID; + assign S_AXI_bresp[1:0] = s00_couplers_to_auto_us_BRESP; + assign S_AXI_bvalid = s00_couplers_to_auto_us_BVALID; + assign S_AXI_rdata[127:0] = s00_couplers_to_auto_us_RDATA; + assign S_AXI_rid[3:0] = s00_couplers_to_auto_us_RID; + assign S_AXI_rlast = s00_couplers_to_auto_us_RLAST; + assign S_AXI_rresp[1:0] = s00_couplers_to_auto_us_RRESP; + assign S_AXI_rvalid = s00_couplers_to_auto_us_RVALID; + assign S_AXI_wready = s00_couplers_to_auto_us_WREADY; + assign auto_cc_to_s00_couplers_ARREADY = M_AXI_arready; + assign auto_cc_to_s00_couplers_AWREADY = M_AXI_awready; + assign auto_cc_to_s00_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_cc_to_s00_couplers_BVALID = M_AXI_bvalid; + assign auto_cc_to_s00_couplers_RDATA = M_AXI_rdata[511:0]; + assign auto_cc_to_s00_couplers_RLAST = M_AXI_rlast; + assign auto_cc_to_s00_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_cc_to_s00_couplers_RVALID = M_AXI_rvalid; + assign auto_cc_to_s00_couplers_WREADY = M_AXI_wready; + assign s00_couplers_to_auto_us_ARADDR = S_AXI_araddr[63:0]; + assign s00_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0]; + assign s00_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0]; + assign s00_couplers_to_auto_us_ARID = S_AXI_arid[3:0]; + assign s00_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0]; + assign s00_couplers_to_auto_us_ARLOCK = S_AXI_arlock[0]; + assign s00_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0]; + assign s00_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0]; + assign s00_couplers_to_auto_us_ARVALID = S_AXI_arvalid; + assign s00_couplers_to_auto_us_AWADDR = S_AXI_awaddr[63:0]; + assign s00_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0]; + assign s00_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0]; + assign s00_couplers_to_auto_us_AWID = S_AXI_awid[3:0]; + assign s00_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0]; + assign s00_couplers_to_auto_us_AWLOCK = S_AXI_awlock[0]; + assign s00_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0]; + assign s00_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0]; + assign s00_couplers_to_auto_us_AWVALID = S_AXI_awvalid; + assign s00_couplers_to_auto_us_BREADY = S_AXI_bready; + assign s00_couplers_to_auto_us_RREADY = S_AXI_rready; + assign s00_couplers_to_auto_us_WDATA = S_AXI_wdata[127:0]; + assign s00_couplers_to_auto_us_WLAST = S_AXI_wlast; + assign s00_couplers_to_auto_us_WSTRB = S_AXI_wstrb[15:0]; + assign s00_couplers_to_auto_us_WVALID = S_AXI_wvalid; + pcie_ddr_auto_cc_2 auto_cc + (.m_axi_aclk(M_ACLK_1), + .m_axi_araddr(auto_cc_to_s00_couplers_ARADDR), + .m_axi_arburst(auto_cc_to_s00_couplers_ARBURST), + .m_axi_arcache(auto_cc_to_s00_couplers_ARCACHE), + .m_axi_aresetn(M_ARESETN_1), + .m_axi_arlen(auto_cc_to_s00_couplers_ARLEN), + .m_axi_arlock(auto_cc_to_s00_couplers_ARLOCK), + .m_axi_arprot(auto_cc_to_s00_couplers_ARPROT), + .m_axi_arqos(auto_cc_to_s00_couplers_ARQOS), + .m_axi_arready(auto_cc_to_s00_couplers_ARREADY), + .m_axi_arsize(auto_cc_to_s00_couplers_ARSIZE), + .m_axi_arvalid(auto_cc_to_s00_couplers_ARVALID), + .m_axi_awaddr(auto_cc_to_s00_couplers_AWADDR), + .m_axi_awburst(auto_cc_to_s00_couplers_AWBURST), + .m_axi_awcache(auto_cc_to_s00_couplers_AWCACHE), + .m_axi_awlen(auto_cc_to_s00_couplers_AWLEN), + .m_axi_awlock(auto_cc_to_s00_couplers_AWLOCK), + .m_axi_awprot(auto_cc_to_s00_couplers_AWPROT), + .m_axi_awqos(auto_cc_to_s00_couplers_AWQOS), + .m_axi_awready(auto_cc_to_s00_couplers_AWREADY), + .m_axi_awsize(auto_cc_to_s00_couplers_AWSIZE), + .m_axi_awvalid(auto_cc_to_s00_couplers_AWVALID), + .m_axi_bready(auto_cc_to_s00_couplers_BREADY), + .m_axi_bresp(auto_cc_to_s00_couplers_BRESP), + .m_axi_bvalid(auto_cc_to_s00_couplers_BVALID), + .m_axi_rdata(auto_cc_to_s00_couplers_RDATA), + .m_axi_rlast(auto_cc_to_s00_couplers_RLAST), + .m_axi_rready(auto_cc_to_s00_couplers_RREADY), + .m_axi_rresp(auto_cc_to_s00_couplers_RRESP), + .m_axi_rvalid(auto_cc_to_s00_couplers_RVALID), + .m_axi_wdata(auto_cc_to_s00_couplers_WDATA), + .m_axi_wlast(auto_cc_to_s00_couplers_WLAST), + .m_axi_wready(auto_cc_to_s00_couplers_WREADY), + .m_axi_wstrb(auto_cc_to_s00_couplers_WSTRB), + .m_axi_wvalid(auto_cc_to_s00_couplers_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(auto_us_to_auto_cc_ARADDR), + .s_axi_arburst(auto_us_to_auto_cc_ARBURST), + .s_axi_arcache(auto_us_to_auto_cc_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arlen(auto_us_to_auto_cc_ARLEN), + .s_axi_arlock(auto_us_to_auto_cc_ARLOCK), + .s_axi_arprot(auto_us_to_auto_cc_ARPROT), + .s_axi_arqos(auto_us_to_auto_cc_ARQOS), + .s_axi_arready(auto_us_to_auto_cc_ARREADY), + .s_axi_arregion(auto_us_to_auto_cc_ARREGION), + .s_axi_arsize(auto_us_to_auto_cc_ARSIZE), + .s_axi_arvalid(auto_us_to_auto_cc_ARVALID), + .s_axi_awaddr(auto_us_to_auto_cc_AWADDR), + .s_axi_awburst(auto_us_to_auto_cc_AWBURST), + .s_axi_awcache(auto_us_to_auto_cc_AWCACHE), + .s_axi_awlen(auto_us_to_auto_cc_AWLEN), + .s_axi_awlock(auto_us_to_auto_cc_AWLOCK), + .s_axi_awprot(auto_us_to_auto_cc_AWPROT), + .s_axi_awqos(auto_us_to_auto_cc_AWQOS), + .s_axi_awready(auto_us_to_auto_cc_AWREADY), + .s_axi_awregion(auto_us_to_auto_cc_AWREGION), + .s_axi_awsize(auto_us_to_auto_cc_AWSIZE), + .s_axi_awvalid(auto_us_to_auto_cc_AWVALID), + .s_axi_bready(auto_us_to_auto_cc_BREADY), + .s_axi_bresp(auto_us_to_auto_cc_BRESP), + .s_axi_bvalid(auto_us_to_auto_cc_BVALID), + .s_axi_rdata(auto_us_to_auto_cc_RDATA), + .s_axi_rlast(auto_us_to_auto_cc_RLAST), + .s_axi_rready(auto_us_to_auto_cc_RREADY), + .s_axi_rresp(auto_us_to_auto_cc_RRESP), + .s_axi_rvalid(auto_us_to_auto_cc_RVALID), + .s_axi_wdata(auto_us_to_auto_cc_WDATA), + .s_axi_wlast(auto_us_to_auto_cc_WLAST), + .s_axi_wready(auto_us_to_auto_cc_WREADY), + .s_axi_wstrb(auto_us_to_auto_cc_WSTRB), + .s_axi_wvalid(auto_us_to_auto_cc_WVALID)); + pcie_ddr_auto_us_0 auto_us + (.m_axi_araddr(auto_us_to_auto_cc_ARADDR), + .m_axi_arburst(auto_us_to_auto_cc_ARBURST), + .m_axi_arcache(auto_us_to_auto_cc_ARCACHE), + .m_axi_arlen(auto_us_to_auto_cc_ARLEN), + .m_axi_arlock(auto_us_to_auto_cc_ARLOCK), + .m_axi_arprot(auto_us_to_auto_cc_ARPROT), + .m_axi_arqos(auto_us_to_auto_cc_ARQOS), + .m_axi_arready(auto_us_to_auto_cc_ARREADY), + .m_axi_arregion(auto_us_to_auto_cc_ARREGION), + .m_axi_arsize(auto_us_to_auto_cc_ARSIZE), + .m_axi_arvalid(auto_us_to_auto_cc_ARVALID), + .m_axi_awaddr(auto_us_to_auto_cc_AWADDR), + .m_axi_awburst(auto_us_to_auto_cc_AWBURST), + .m_axi_awcache(auto_us_to_auto_cc_AWCACHE), + .m_axi_awlen(auto_us_to_auto_cc_AWLEN), + .m_axi_awlock(auto_us_to_auto_cc_AWLOCK), + .m_axi_awprot(auto_us_to_auto_cc_AWPROT), + .m_axi_awqos(auto_us_to_auto_cc_AWQOS), + .m_axi_awready(auto_us_to_auto_cc_AWREADY), + .m_axi_awregion(auto_us_to_auto_cc_AWREGION), + .m_axi_awsize(auto_us_to_auto_cc_AWSIZE), + .m_axi_awvalid(auto_us_to_auto_cc_AWVALID), + .m_axi_bready(auto_us_to_auto_cc_BREADY), + .m_axi_bresp(auto_us_to_auto_cc_BRESP), + .m_axi_bvalid(auto_us_to_auto_cc_BVALID), + .m_axi_rdata(auto_us_to_auto_cc_RDATA), + .m_axi_rlast(auto_us_to_auto_cc_RLAST), + .m_axi_rready(auto_us_to_auto_cc_RREADY), + .m_axi_rresp(auto_us_to_auto_cc_RRESP), + .m_axi_rvalid(auto_us_to_auto_cc_RVALID), + .m_axi_wdata(auto_us_to_auto_cc_WDATA), + .m_axi_wlast(auto_us_to_auto_cc_WLAST), + .m_axi_wready(auto_us_to_auto_cc_WREADY), + .m_axi_wstrb(auto_us_to_auto_cc_WSTRB), + .m_axi_wvalid(auto_us_to_auto_cc_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(s00_couplers_to_auto_us_ARADDR), + .s_axi_arburst(s00_couplers_to_auto_us_ARBURST), + .s_axi_arcache(s00_couplers_to_auto_us_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arid(s00_couplers_to_auto_us_ARID), + .s_axi_arlen(s00_couplers_to_auto_us_ARLEN), + .s_axi_arlock(s00_couplers_to_auto_us_ARLOCK), + .s_axi_arprot(s00_couplers_to_auto_us_ARPROT), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(s00_couplers_to_auto_us_ARREADY), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize(s00_couplers_to_auto_us_ARSIZE), + .s_axi_arvalid(s00_couplers_to_auto_us_ARVALID), + .s_axi_awaddr(s00_couplers_to_auto_us_AWADDR), + .s_axi_awburst(s00_couplers_to_auto_us_AWBURST), + .s_axi_awcache(s00_couplers_to_auto_us_AWCACHE), + .s_axi_awid(s00_couplers_to_auto_us_AWID), + .s_axi_awlen(s00_couplers_to_auto_us_AWLEN), + .s_axi_awlock(s00_couplers_to_auto_us_AWLOCK), + .s_axi_awprot(s00_couplers_to_auto_us_AWPROT), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(s00_couplers_to_auto_us_AWREADY), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize(s00_couplers_to_auto_us_AWSIZE), + .s_axi_awvalid(s00_couplers_to_auto_us_AWVALID), + .s_axi_bid(s00_couplers_to_auto_us_BID), + .s_axi_bready(s00_couplers_to_auto_us_BREADY), + .s_axi_bresp(s00_couplers_to_auto_us_BRESP), + .s_axi_bvalid(s00_couplers_to_auto_us_BVALID), + .s_axi_rdata(s00_couplers_to_auto_us_RDATA), + .s_axi_rid(s00_couplers_to_auto_us_RID), + .s_axi_rlast(s00_couplers_to_auto_us_RLAST), + .s_axi_rready(s00_couplers_to_auto_us_RREADY), + .s_axi_rresp(s00_couplers_to_auto_us_RRESP), + .s_axi_rvalid(s00_couplers_to_auto_us_RVALID), + .s_axi_wdata(s00_couplers_to_auto_us_WDATA), + .s_axi_wlast(s00_couplers_to_auto_us_WLAST), + .s_axi_wready(s00_couplers_to_auto_us_WREADY), + .s_axi_wstrb(s00_couplers_to_auto_us_WSTRB), + .s_axi_wvalid(s00_couplers_to_auto_us_WVALID)); +endmodule + +module s01_couplers_imp_1CQ4OV4 + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [31:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [7:0]M_AXI_arlen; + output [0:0]M_AXI_arlock; + output [2:0]M_AXI_arprot; + output [3:0]M_AXI_arqos; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [31:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [7:0]M_AXI_awlen; + output [0:0]M_AXI_awlock; + output [2:0]M_AXI_awprot; + output [3:0]M_AXI_awqos; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [511:0]M_AXI_rdata; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [511:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [63:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [31:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [0:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + input [3:0]S_AXI_arqos; + output S_AXI_arready; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [31:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [0:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + input [3:0]S_AXI_awqos; + output S_AXI_awready; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [0:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [31:0]S_AXI_rdata; + output [0:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [31:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [3:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire M_ACLK_1; + wire M_ARESETN_1; + wire S_ACLK_1; + wire S_ARESETN_1; + wire [31:0]auto_cc_to_s01_couplers_ARADDR; + wire [1:0]auto_cc_to_s01_couplers_ARBURST; + wire [3:0]auto_cc_to_s01_couplers_ARCACHE; + wire [7:0]auto_cc_to_s01_couplers_ARLEN; + wire [0:0]auto_cc_to_s01_couplers_ARLOCK; + wire [2:0]auto_cc_to_s01_couplers_ARPROT; + wire [3:0]auto_cc_to_s01_couplers_ARQOS; + wire auto_cc_to_s01_couplers_ARREADY; + wire [2:0]auto_cc_to_s01_couplers_ARSIZE; + wire auto_cc_to_s01_couplers_ARVALID; + wire [31:0]auto_cc_to_s01_couplers_AWADDR; + wire [1:0]auto_cc_to_s01_couplers_AWBURST; + wire [3:0]auto_cc_to_s01_couplers_AWCACHE; + wire [7:0]auto_cc_to_s01_couplers_AWLEN; + wire [0:0]auto_cc_to_s01_couplers_AWLOCK; + wire [2:0]auto_cc_to_s01_couplers_AWPROT; + wire [3:0]auto_cc_to_s01_couplers_AWQOS; + wire auto_cc_to_s01_couplers_AWREADY; + wire [2:0]auto_cc_to_s01_couplers_AWSIZE; + wire auto_cc_to_s01_couplers_AWVALID; + wire auto_cc_to_s01_couplers_BREADY; + wire [1:0]auto_cc_to_s01_couplers_BRESP; + wire auto_cc_to_s01_couplers_BVALID; + wire [511:0]auto_cc_to_s01_couplers_RDATA; + wire auto_cc_to_s01_couplers_RLAST; + wire auto_cc_to_s01_couplers_RREADY; + wire [1:0]auto_cc_to_s01_couplers_RRESP; + wire auto_cc_to_s01_couplers_RVALID; + wire [511:0]auto_cc_to_s01_couplers_WDATA; + wire auto_cc_to_s01_couplers_WLAST; + wire auto_cc_to_s01_couplers_WREADY; + wire [63:0]auto_cc_to_s01_couplers_WSTRB; + wire auto_cc_to_s01_couplers_WVALID; + wire [31:0]auto_us_to_auto_cc_ARADDR; + wire [1:0]auto_us_to_auto_cc_ARBURST; + wire [3:0]auto_us_to_auto_cc_ARCACHE; + wire [7:0]auto_us_to_auto_cc_ARLEN; + wire [0:0]auto_us_to_auto_cc_ARLOCK; + wire [2:0]auto_us_to_auto_cc_ARPROT; + wire [3:0]auto_us_to_auto_cc_ARQOS; + wire auto_us_to_auto_cc_ARREADY; + wire [3:0]auto_us_to_auto_cc_ARREGION; + wire [2:0]auto_us_to_auto_cc_ARSIZE; + wire auto_us_to_auto_cc_ARVALID; + wire [31:0]auto_us_to_auto_cc_AWADDR; + wire [1:0]auto_us_to_auto_cc_AWBURST; + wire [3:0]auto_us_to_auto_cc_AWCACHE; + wire [7:0]auto_us_to_auto_cc_AWLEN; + wire [0:0]auto_us_to_auto_cc_AWLOCK; + wire [2:0]auto_us_to_auto_cc_AWPROT; + wire [3:0]auto_us_to_auto_cc_AWQOS; + wire auto_us_to_auto_cc_AWREADY; + wire [3:0]auto_us_to_auto_cc_AWREGION; + wire [2:0]auto_us_to_auto_cc_AWSIZE; + wire auto_us_to_auto_cc_AWVALID; + wire auto_us_to_auto_cc_BREADY; + wire [1:0]auto_us_to_auto_cc_BRESP; + wire auto_us_to_auto_cc_BVALID; + wire [511:0]auto_us_to_auto_cc_RDATA; + wire auto_us_to_auto_cc_RLAST; + wire auto_us_to_auto_cc_RREADY; + wire [1:0]auto_us_to_auto_cc_RRESP; + wire auto_us_to_auto_cc_RVALID; + wire [511:0]auto_us_to_auto_cc_WDATA; + wire auto_us_to_auto_cc_WLAST; + wire auto_us_to_auto_cc_WREADY; + wire [63:0]auto_us_to_auto_cc_WSTRB; + wire auto_us_to_auto_cc_WVALID; + wire [31:0]s01_couplers_to_auto_us_ARADDR; + wire [1:0]s01_couplers_to_auto_us_ARBURST; + wire [3:0]s01_couplers_to_auto_us_ARCACHE; + wire [0:0]s01_couplers_to_auto_us_ARID; + wire [7:0]s01_couplers_to_auto_us_ARLEN; + wire [0:0]s01_couplers_to_auto_us_ARLOCK; + wire [2:0]s01_couplers_to_auto_us_ARPROT; + wire [3:0]s01_couplers_to_auto_us_ARQOS; + wire s01_couplers_to_auto_us_ARREADY; + wire [2:0]s01_couplers_to_auto_us_ARSIZE; + wire s01_couplers_to_auto_us_ARVALID; + wire [31:0]s01_couplers_to_auto_us_AWADDR; + wire [1:0]s01_couplers_to_auto_us_AWBURST; + wire [3:0]s01_couplers_to_auto_us_AWCACHE; + wire [0:0]s01_couplers_to_auto_us_AWID; + wire [7:0]s01_couplers_to_auto_us_AWLEN; + wire [0:0]s01_couplers_to_auto_us_AWLOCK; + wire [2:0]s01_couplers_to_auto_us_AWPROT; + wire [3:0]s01_couplers_to_auto_us_AWQOS; + wire s01_couplers_to_auto_us_AWREADY; + wire [2:0]s01_couplers_to_auto_us_AWSIZE; + wire s01_couplers_to_auto_us_AWVALID; + wire [0:0]s01_couplers_to_auto_us_BID; + wire s01_couplers_to_auto_us_BREADY; + wire [1:0]s01_couplers_to_auto_us_BRESP; + wire s01_couplers_to_auto_us_BVALID; + wire [31:0]s01_couplers_to_auto_us_RDATA; + wire [0:0]s01_couplers_to_auto_us_RID; + wire s01_couplers_to_auto_us_RLAST; + wire s01_couplers_to_auto_us_RREADY; + wire [1:0]s01_couplers_to_auto_us_RRESP; + wire s01_couplers_to_auto_us_RVALID; + wire [31:0]s01_couplers_to_auto_us_WDATA; + wire s01_couplers_to_auto_us_WLAST; + wire s01_couplers_to_auto_us_WREADY; + wire [3:0]s01_couplers_to_auto_us_WSTRB; + wire s01_couplers_to_auto_us_WVALID; + + assign M_ACLK_1 = M_ACLK; + assign M_ARESETN_1 = M_ARESETN; + assign M_AXI_araddr[31:0] = auto_cc_to_s01_couplers_ARADDR; + assign M_AXI_arburst[1:0] = auto_cc_to_s01_couplers_ARBURST; + assign M_AXI_arcache[3:0] = auto_cc_to_s01_couplers_ARCACHE; + assign M_AXI_arlen[7:0] = auto_cc_to_s01_couplers_ARLEN; + assign M_AXI_arlock[0] = auto_cc_to_s01_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = auto_cc_to_s01_couplers_ARPROT; + assign M_AXI_arqos[3:0] = auto_cc_to_s01_couplers_ARQOS; + assign M_AXI_arsize[2:0] = auto_cc_to_s01_couplers_ARSIZE; + assign M_AXI_arvalid = auto_cc_to_s01_couplers_ARVALID; + assign M_AXI_awaddr[31:0] = auto_cc_to_s01_couplers_AWADDR; + assign M_AXI_awburst[1:0] = auto_cc_to_s01_couplers_AWBURST; + assign M_AXI_awcache[3:0] = auto_cc_to_s01_couplers_AWCACHE; + assign M_AXI_awlen[7:0] = auto_cc_to_s01_couplers_AWLEN; + assign M_AXI_awlock[0] = auto_cc_to_s01_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = auto_cc_to_s01_couplers_AWPROT; + assign M_AXI_awqos[3:0] = auto_cc_to_s01_couplers_AWQOS; + assign M_AXI_awsize[2:0] = auto_cc_to_s01_couplers_AWSIZE; + assign M_AXI_awvalid = auto_cc_to_s01_couplers_AWVALID; + assign M_AXI_bready = auto_cc_to_s01_couplers_BREADY; + assign M_AXI_rready = auto_cc_to_s01_couplers_RREADY; + assign M_AXI_wdata[511:0] = auto_cc_to_s01_couplers_WDATA; + assign M_AXI_wlast = auto_cc_to_s01_couplers_WLAST; + assign M_AXI_wstrb[63:0] = auto_cc_to_s01_couplers_WSTRB; + assign M_AXI_wvalid = auto_cc_to_s01_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = s01_couplers_to_auto_us_ARREADY; + assign S_AXI_awready = s01_couplers_to_auto_us_AWREADY; + assign S_AXI_bid[0] = s01_couplers_to_auto_us_BID; + assign S_AXI_bresp[1:0] = s01_couplers_to_auto_us_BRESP; + assign S_AXI_bvalid = s01_couplers_to_auto_us_BVALID; + assign S_AXI_rdata[31:0] = s01_couplers_to_auto_us_RDATA; + assign S_AXI_rid[0] = s01_couplers_to_auto_us_RID; + assign S_AXI_rlast = s01_couplers_to_auto_us_RLAST; + assign S_AXI_rresp[1:0] = s01_couplers_to_auto_us_RRESP; + assign S_AXI_rvalid = s01_couplers_to_auto_us_RVALID; + assign S_AXI_wready = s01_couplers_to_auto_us_WREADY; + assign auto_cc_to_s01_couplers_ARREADY = M_AXI_arready; + assign auto_cc_to_s01_couplers_AWREADY = M_AXI_awready; + assign auto_cc_to_s01_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_cc_to_s01_couplers_BVALID = M_AXI_bvalid; + assign auto_cc_to_s01_couplers_RDATA = M_AXI_rdata[511:0]; + assign auto_cc_to_s01_couplers_RLAST = M_AXI_rlast; + assign auto_cc_to_s01_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_cc_to_s01_couplers_RVALID = M_AXI_rvalid; + assign auto_cc_to_s01_couplers_WREADY = M_AXI_wready; + assign s01_couplers_to_auto_us_ARADDR = S_AXI_araddr[31:0]; + assign s01_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0]; + assign s01_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0]; + assign s01_couplers_to_auto_us_ARID = S_AXI_arid[0]; + assign s01_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0]; + assign s01_couplers_to_auto_us_ARLOCK = S_AXI_arlock[0]; + assign s01_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0]; + assign s01_couplers_to_auto_us_ARQOS = S_AXI_arqos[3:0]; + assign s01_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0]; + assign s01_couplers_to_auto_us_ARVALID = S_AXI_arvalid; + assign s01_couplers_to_auto_us_AWADDR = S_AXI_awaddr[31:0]; + assign s01_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0]; + assign s01_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0]; + assign s01_couplers_to_auto_us_AWID = S_AXI_awid[0]; + assign s01_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0]; + assign s01_couplers_to_auto_us_AWLOCK = S_AXI_awlock[0]; + assign s01_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0]; + assign s01_couplers_to_auto_us_AWQOS = S_AXI_awqos[3:0]; + assign s01_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0]; + assign s01_couplers_to_auto_us_AWVALID = S_AXI_awvalid; + assign s01_couplers_to_auto_us_BREADY = S_AXI_bready; + assign s01_couplers_to_auto_us_RREADY = S_AXI_rready; + assign s01_couplers_to_auto_us_WDATA = S_AXI_wdata[31:0]; + assign s01_couplers_to_auto_us_WLAST = S_AXI_wlast; + assign s01_couplers_to_auto_us_WSTRB = S_AXI_wstrb[3:0]; + assign s01_couplers_to_auto_us_WVALID = S_AXI_wvalid; + pcie_ddr_auto_cc_3 auto_cc + (.m_axi_aclk(M_ACLK_1), + .m_axi_araddr(auto_cc_to_s01_couplers_ARADDR), + .m_axi_arburst(auto_cc_to_s01_couplers_ARBURST), + .m_axi_arcache(auto_cc_to_s01_couplers_ARCACHE), + .m_axi_aresetn(M_ARESETN_1), + .m_axi_arlen(auto_cc_to_s01_couplers_ARLEN), + .m_axi_arlock(auto_cc_to_s01_couplers_ARLOCK), + .m_axi_arprot(auto_cc_to_s01_couplers_ARPROT), + .m_axi_arqos(auto_cc_to_s01_couplers_ARQOS), + .m_axi_arready(auto_cc_to_s01_couplers_ARREADY), + .m_axi_arsize(auto_cc_to_s01_couplers_ARSIZE), + .m_axi_arvalid(auto_cc_to_s01_couplers_ARVALID), + .m_axi_awaddr(auto_cc_to_s01_couplers_AWADDR), + .m_axi_awburst(auto_cc_to_s01_couplers_AWBURST), + .m_axi_awcache(auto_cc_to_s01_couplers_AWCACHE), + .m_axi_awlen(auto_cc_to_s01_couplers_AWLEN), + .m_axi_awlock(auto_cc_to_s01_couplers_AWLOCK), + .m_axi_awprot(auto_cc_to_s01_couplers_AWPROT), + .m_axi_awqos(auto_cc_to_s01_couplers_AWQOS), + .m_axi_awready(auto_cc_to_s01_couplers_AWREADY), + .m_axi_awsize(auto_cc_to_s01_couplers_AWSIZE), + .m_axi_awvalid(auto_cc_to_s01_couplers_AWVALID), + .m_axi_bready(auto_cc_to_s01_couplers_BREADY), + .m_axi_bresp(auto_cc_to_s01_couplers_BRESP), + .m_axi_bvalid(auto_cc_to_s01_couplers_BVALID), + .m_axi_rdata(auto_cc_to_s01_couplers_RDATA), + .m_axi_rlast(auto_cc_to_s01_couplers_RLAST), + .m_axi_rready(auto_cc_to_s01_couplers_RREADY), + .m_axi_rresp(auto_cc_to_s01_couplers_RRESP), + .m_axi_rvalid(auto_cc_to_s01_couplers_RVALID), + .m_axi_wdata(auto_cc_to_s01_couplers_WDATA), + .m_axi_wlast(auto_cc_to_s01_couplers_WLAST), + .m_axi_wready(auto_cc_to_s01_couplers_WREADY), + .m_axi_wstrb(auto_cc_to_s01_couplers_WSTRB), + .m_axi_wvalid(auto_cc_to_s01_couplers_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(auto_us_to_auto_cc_ARADDR), + .s_axi_arburst(auto_us_to_auto_cc_ARBURST), + .s_axi_arcache(auto_us_to_auto_cc_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arlen(auto_us_to_auto_cc_ARLEN), + .s_axi_arlock(auto_us_to_auto_cc_ARLOCK), + .s_axi_arprot(auto_us_to_auto_cc_ARPROT), + .s_axi_arqos(auto_us_to_auto_cc_ARQOS), + .s_axi_arready(auto_us_to_auto_cc_ARREADY), + .s_axi_arregion(auto_us_to_auto_cc_ARREGION), + .s_axi_arsize(auto_us_to_auto_cc_ARSIZE), + .s_axi_arvalid(auto_us_to_auto_cc_ARVALID), + .s_axi_awaddr(auto_us_to_auto_cc_AWADDR), + .s_axi_awburst(auto_us_to_auto_cc_AWBURST), + .s_axi_awcache(auto_us_to_auto_cc_AWCACHE), + .s_axi_awlen(auto_us_to_auto_cc_AWLEN), + .s_axi_awlock(auto_us_to_auto_cc_AWLOCK), + .s_axi_awprot(auto_us_to_auto_cc_AWPROT), + .s_axi_awqos(auto_us_to_auto_cc_AWQOS), + .s_axi_awready(auto_us_to_auto_cc_AWREADY), + .s_axi_awregion(auto_us_to_auto_cc_AWREGION), + .s_axi_awsize(auto_us_to_auto_cc_AWSIZE), + .s_axi_awvalid(auto_us_to_auto_cc_AWVALID), + .s_axi_bready(auto_us_to_auto_cc_BREADY), + .s_axi_bresp(auto_us_to_auto_cc_BRESP), + .s_axi_bvalid(auto_us_to_auto_cc_BVALID), + .s_axi_rdata(auto_us_to_auto_cc_RDATA), + .s_axi_rlast(auto_us_to_auto_cc_RLAST), + .s_axi_rready(auto_us_to_auto_cc_RREADY), + .s_axi_rresp(auto_us_to_auto_cc_RRESP), + .s_axi_rvalid(auto_us_to_auto_cc_RVALID), + .s_axi_wdata(auto_us_to_auto_cc_WDATA), + .s_axi_wlast(auto_us_to_auto_cc_WLAST), + .s_axi_wready(auto_us_to_auto_cc_WREADY), + .s_axi_wstrb(auto_us_to_auto_cc_WSTRB), + .s_axi_wvalid(auto_us_to_auto_cc_WVALID)); + pcie_ddr_auto_us_1 auto_us + (.m_axi_araddr(auto_us_to_auto_cc_ARADDR), + .m_axi_arburst(auto_us_to_auto_cc_ARBURST), + .m_axi_arcache(auto_us_to_auto_cc_ARCACHE), + .m_axi_arlen(auto_us_to_auto_cc_ARLEN), + .m_axi_arlock(auto_us_to_auto_cc_ARLOCK), + .m_axi_arprot(auto_us_to_auto_cc_ARPROT), + .m_axi_arqos(auto_us_to_auto_cc_ARQOS), + .m_axi_arready(auto_us_to_auto_cc_ARREADY), + .m_axi_arregion(auto_us_to_auto_cc_ARREGION), + .m_axi_arsize(auto_us_to_auto_cc_ARSIZE), + .m_axi_arvalid(auto_us_to_auto_cc_ARVALID), + .m_axi_awaddr(auto_us_to_auto_cc_AWADDR), + .m_axi_awburst(auto_us_to_auto_cc_AWBURST), + .m_axi_awcache(auto_us_to_auto_cc_AWCACHE), + .m_axi_awlen(auto_us_to_auto_cc_AWLEN), + .m_axi_awlock(auto_us_to_auto_cc_AWLOCK), + .m_axi_awprot(auto_us_to_auto_cc_AWPROT), + .m_axi_awqos(auto_us_to_auto_cc_AWQOS), + .m_axi_awready(auto_us_to_auto_cc_AWREADY), + .m_axi_awregion(auto_us_to_auto_cc_AWREGION), + .m_axi_awsize(auto_us_to_auto_cc_AWSIZE), + .m_axi_awvalid(auto_us_to_auto_cc_AWVALID), + .m_axi_bready(auto_us_to_auto_cc_BREADY), + .m_axi_bresp(auto_us_to_auto_cc_BRESP), + .m_axi_bvalid(auto_us_to_auto_cc_BVALID), + .m_axi_rdata(auto_us_to_auto_cc_RDATA), + .m_axi_rlast(auto_us_to_auto_cc_RLAST), + .m_axi_rready(auto_us_to_auto_cc_RREADY), + .m_axi_rresp(auto_us_to_auto_cc_RRESP), + .m_axi_rvalid(auto_us_to_auto_cc_RVALID), + .m_axi_wdata(auto_us_to_auto_cc_WDATA), + .m_axi_wlast(auto_us_to_auto_cc_WLAST), + .m_axi_wready(auto_us_to_auto_cc_WREADY), + .m_axi_wstrb(auto_us_to_auto_cc_WSTRB), + .m_axi_wvalid(auto_us_to_auto_cc_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(s01_couplers_to_auto_us_ARADDR), + .s_axi_arburst(s01_couplers_to_auto_us_ARBURST), + .s_axi_arcache(s01_couplers_to_auto_us_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arid(s01_couplers_to_auto_us_ARID), + .s_axi_arlen(s01_couplers_to_auto_us_ARLEN), + .s_axi_arlock(s01_couplers_to_auto_us_ARLOCK), + .s_axi_arprot(s01_couplers_to_auto_us_ARPROT), + .s_axi_arqos(s01_couplers_to_auto_us_ARQOS), + .s_axi_arready(s01_couplers_to_auto_us_ARREADY), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize(s01_couplers_to_auto_us_ARSIZE), + .s_axi_arvalid(s01_couplers_to_auto_us_ARVALID), + .s_axi_awaddr(s01_couplers_to_auto_us_AWADDR), + .s_axi_awburst(s01_couplers_to_auto_us_AWBURST), + .s_axi_awcache(s01_couplers_to_auto_us_AWCACHE), + .s_axi_awid(s01_couplers_to_auto_us_AWID), + .s_axi_awlen(s01_couplers_to_auto_us_AWLEN), + .s_axi_awlock(s01_couplers_to_auto_us_AWLOCK), + .s_axi_awprot(s01_couplers_to_auto_us_AWPROT), + .s_axi_awqos(s01_couplers_to_auto_us_AWQOS), + .s_axi_awready(s01_couplers_to_auto_us_AWREADY), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize(s01_couplers_to_auto_us_AWSIZE), + .s_axi_awvalid(s01_couplers_to_auto_us_AWVALID), + .s_axi_bid(s01_couplers_to_auto_us_BID), + .s_axi_bready(s01_couplers_to_auto_us_BREADY), + .s_axi_bresp(s01_couplers_to_auto_us_BRESP), + .s_axi_bvalid(s01_couplers_to_auto_us_BVALID), + .s_axi_rdata(s01_couplers_to_auto_us_RDATA), + .s_axi_rid(s01_couplers_to_auto_us_RID), + .s_axi_rlast(s01_couplers_to_auto_us_RLAST), + .s_axi_rready(s01_couplers_to_auto_us_RREADY), + .s_axi_rresp(s01_couplers_to_auto_us_RRESP), + .s_axi_rvalid(s01_couplers_to_auto_us_RVALID), + .s_axi_wdata(s01_couplers_to_auto_us_WDATA), + .s_axi_wlast(s01_couplers_to_auto_us_WLAST), + .s_axi_wready(s01_couplers_to_auto_us_WREADY), + .s_axi_wstrb(s01_couplers_to_auto_us_WSTRB), + .s_axi_wvalid(s01_couplers_to_auto_us_WVALID)); +endmodule diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/synth/pcie_ddr.v b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/synth/pcie_ddr.v new file mode 100644 index 0000000..f9bc3ac --- /dev/null +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/synth/pcie_ddr.v @@ -0,0 +1,2977 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +//Date : Tue Mar 18 13:48:36 2025 +//Host : BHKLaptop running 64-bit major release (build 9200) +//Command : generate_target pcie_ddr.bd +//Design : pcie_ddr +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module m00_couplers_imp_1FLA7NN + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arid, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awid, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rid, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arregion, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awregion, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [32:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [0:0]M_AXI_arid; + output [7:0]M_AXI_arlen; + output [0:0]M_AXI_arlock; + output [2:0]M_AXI_arprot; + output [3:0]M_AXI_arqos; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [32:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [0:0]M_AXI_awid; + output [7:0]M_AXI_awlen; + output [0:0]M_AXI_awlock; + output [2:0]M_AXI_awprot; + output [3:0]M_AXI_awqos; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + input [0:0]M_AXI_bid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [511:0]M_AXI_rdata; + input [0:0]M_AXI_rid; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [511:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [63:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [63:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [0:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + input [3:0]S_AXI_arqos; + output S_AXI_arready; + input [3:0]S_AXI_arregion; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [63:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [0:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + input [3:0]S_AXI_awqos; + output S_AXI_awready; + input [3:0]S_AXI_awregion; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [0:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [511:0]S_AXI_rdata; + output [0:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [511:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [63:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire M_ACLK_1; + wire M_ARESETN_1; + wire S_ACLK_1; + wire S_ARESETN_1; + wire [32:0]auto_cc_to_m00_couplers_ARADDR; + wire [1:0]auto_cc_to_m00_couplers_ARBURST; + wire [3:0]auto_cc_to_m00_couplers_ARCACHE; + wire [0:0]auto_cc_to_m00_couplers_ARID; + wire [7:0]auto_cc_to_m00_couplers_ARLEN; + wire [0:0]auto_cc_to_m00_couplers_ARLOCK; + wire [2:0]auto_cc_to_m00_couplers_ARPROT; + wire [3:0]auto_cc_to_m00_couplers_ARQOS; + wire auto_cc_to_m00_couplers_ARREADY; + wire [2:0]auto_cc_to_m00_couplers_ARSIZE; + wire auto_cc_to_m00_couplers_ARVALID; + wire [32:0]auto_cc_to_m00_couplers_AWADDR; + wire [1:0]auto_cc_to_m00_couplers_AWBURST; + wire [3:0]auto_cc_to_m00_couplers_AWCACHE; + wire [0:0]auto_cc_to_m00_couplers_AWID; + wire [7:0]auto_cc_to_m00_couplers_AWLEN; + wire [0:0]auto_cc_to_m00_couplers_AWLOCK; + wire [2:0]auto_cc_to_m00_couplers_AWPROT; + wire [3:0]auto_cc_to_m00_couplers_AWQOS; + wire auto_cc_to_m00_couplers_AWREADY; + wire [2:0]auto_cc_to_m00_couplers_AWSIZE; + wire auto_cc_to_m00_couplers_AWVALID; + wire [0:0]auto_cc_to_m00_couplers_BID; + wire auto_cc_to_m00_couplers_BREADY; + wire [1:0]auto_cc_to_m00_couplers_BRESP; + wire auto_cc_to_m00_couplers_BVALID; + wire [511:0]auto_cc_to_m00_couplers_RDATA; + wire [0:0]auto_cc_to_m00_couplers_RID; + wire auto_cc_to_m00_couplers_RLAST; + wire auto_cc_to_m00_couplers_RREADY; + wire [1:0]auto_cc_to_m00_couplers_RRESP; + wire auto_cc_to_m00_couplers_RVALID; + wire [511:0]auto_cc_to_m00_couplers_WDATA; + wire auto_cc_to_m00_couplers_WLAST; + wire auto_cc_to_m00_couplers_WREADY; + wire [63:0]auto_cc_to_m00_couplers_WSTRB; + wire auto_cc_to_m00_couplers_WVALID; + wire [63:0]m00_couplers_to_auto_cc_ARADDR; + wire [1:0]m00_couplers_to_auto_cc_ARBURST; + wire [3:0]m00_couplers_to_auto_cc_ARCACHE; + wire [0:0]m00_couplers_to_auto_cc_ARID; + wire [7:0]m00_couplers_to_auto_cc_ARLEN; + wire [0:0]m00_couplers_to_auto_cc_ARLOCK; + wire [2:0]m00_couplers_to_auto_cc_ARPROT; + wire [3:0]m00_couplers_to_auto_cc_ARQOS; + wire m00_couplers_to_auto_cc_ARREADY; + wire [3:0]m00_couplers_to_auto_cc_ARREGION; + wire [2:0]m00_couplers_to_auto_cc_ARSIZE; + wire m00_couplers_to_auto_cc_ARVALID; + wire [63:0]m00_couplers_to_auto_cc_AWADDR; + wire [1:0]m00_couplers_to_auto_cc_AWBURST; + wire [3:0]m00_couplers_to_auto_cc_AWCACHE; + wire [0:0]m00_couplers_to_auto_cc_AWID; + wire [7:0]m00_couplers_to_auto_cc_AWLEN; + wire [0:0]m00_couplers_to_auto_cc_AWLOCK; + wire [2:0]m00_couplers_to_auto_cc_AWPROT; + wire [3:0]m00_couplers_to_auto_cc_AWQOS; + wire m00_couplers_to_auto_cc_AWREADY; + wire [3:0]m00_couplers_to_auto_cc_AWREGION; + wire [2:0]m00_couplers_to_auto_cc_AWSIZE; + wire m00_couplers_to_auto_cc_AWVALID; + wire [0:0]m00_couplers_to_auto_cc_BID; + wire m00_couplers_to_auto_cc_BREADY; + wire [1:0]m00_couplers_to_auto_cc_BRESP; + wire m00_couplers_to_auto_cc_BVALID; + wire [511:0]m00_couplers_to_auto_cc_RDATA; + wire [0:0]m00_couplers_to_auto_cc_RID; + wire m00_couplers_to_auto_cc_RLAST; + wire m00_couplers_to_auto_cc_RREADY; + wire [1:0]m00_couplers_to_auto_cc_RRESP; + wire m00_couplers_to_auto_cc_RVALID; + wire [511:0]m00_couplers_to_auto_cc_WDATA; + wire m00_couplers_to_auto_cc_WLAST; + wire m00_couplers_to_auto_cc_WREADY; + wire [63:0]m00_couplers_to_auto_cc_WSTRB; + wire m00_couplers_to_auto_cc_WVALID; + + assign M_ACLK_1 = M_ACLK; + assign M_ARESETN_1 = M_ARESETN; + assign M_AXI_araddr[32:0] = auto_cc_to_m00_couplers_ARADDR; + assign M_AXI_arburst[1:0] = auto_cc_to_m00_couplers_ARBURST; + assign M_AXI_arcache[3:0] = auto_cc_to_m00_couplers_ARCACHE; + assign M_AXI_arid[0] = auto_cc_to_m00_couplers_ARID; + assign M_AXI_arlen[7:0] = auto_cc_to_m00_couplers_ARLEN; + assign M_AXI_arlock[0] = auto_cc_to_m00_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = auto_cc_to_m00_couplers_ARPROT; + assign M_AXI_arqos[3:0] = auto_cc_to_m00_couplers_ARQOS; + assign M_AXI_arsize[2:0] = auto_cc_to_m00_couplers_ARSIZE; + assign M_AXI_arvalid = auto_cc_to_m00_couplers_ARVALID; + assign M_AXI_awaddr[32:0] = auto_cc_to_m00_couplers_AWADDR; + assign M_AXI_awburst[1:0] = auto_cc_to_m00_couplers_AWBURST; + assign M_AXI_awcache[3:0] = auto_cc_to_m00_couplers_AWCACHE; + assign M_AXI_awid[0] = auto_cc_to_m00_couplers_AWID; + assign M_AXI_awlen[7:0] = auto_cc_to_m00_couplers_AWLEN; + assign M_AXI_awlock[0] = auto_cc_to_m00_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = auto_cc_to_m00_couplers_AWPROT; + assign M_AXI_awqos[3:0] = auto_cc_to_m00_couplers_AWQOS; + assign M_AXI_awsize[2:0] = auto_cc_to_m00_couplers_AWSIZE; + assign M_AXI_awvalid = auto_cc_to_m00_couplers_AWVALID; + assign M_AXI_bready = auto_cc_to_m00_couplers_BREADY; + assign M_AXI_rready = auto_cc_to_m00_couplers_RREADY; + assign M_AXI_wdata[511:0] = auto_cc_to_m00_couplers_WDATA; + assign M_AXI_wlast = auto_cc_to_m00_couplers_WLAST; + assign M_AXI_wstrb[63:0] = auto_cc_to_m00_couplers_WSTRB; + assign M_AXI_wvalid = auto_cc_to_m00_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = m00_couplers_to_auto_cc_ARREADY; + assign S_AXI_awready = m00_couplers_to_auto_cc_AWREADY; + assign S_AXI_bid[0] = m00_couplers_to_auto_cc_BID; + assign S_AXI_bresp[1:0] = m00_couplers_to_auto_cc_BRESP; + assign S_AXI_bvalid = m00_couplers_to_auto_cc_BVALID; + assign S_AXI_rdata[511:0] = m00_couplers_to_auto_cc_RDATA; + assign S_AXI_rid[0] = m00_couplers_to_auto_cc_RID; + assign S_AXI_rlast = m00_couplers_to_auto_cc_RLAST; + assign S_AXI_rresp[1:0] = m00_couplers_to_auto_cc_RRESP; + assign S_AXI_rvalid = m00_couplers_to_auto_cc_RVALID; + assign S_AXI_wready = m00_couplers_to_auto_cc_WREADY; + assign auto_cc_to_m00_couplers_ARREADY = M_AXI_arready; + assign auto_cc_to_m00_couplers_AWREADY = M_AXI_awready; + assign auto_cc_to_m00_couplers_BID = M_AXI_bid[0]; + assign auto_cc_to_m00_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_cc_to_m00_couplers_BVALID = M_AXI_bvalid; + assign auto_cc_to_m00_couplers_RDATA = M_AXI_rdata[511:0]; + assign auto_cc_to_m00_couplers_RID = M_AXI_rid[0]; + assign auto_cc_to_m00_couplers_RLAST = M_AXI_rlast; + assign auto_cc_to_m00_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_cc_to_m00_couplers_RVALID = M_AXI_rvalid; + assign auto_cc_to_m00_couplers_WREADY = M_AXI_wready; + assign m00_couplers_to_auto_cc_ARADDR = S_AXI_araddr[63:0]; + assign m00_couplers_to_auto_cc_ARBURST = S_AXI_arburst[1:0]; + assign m00_couplers_to_auto_cc_ARCACHE = S_AXI_arcache[3:0]; + assign m00_couplers_to_auto_cc_ARID = S_AXI_arid[0]; + assign m00_couplers_to_auto_cc_ARLEN = S_AXI_arlen[7:0]; + assign m00_couplers_to_auto_cc_ARLOCK = S_AXI_arlock[0]; + assign m00_couplers_to_auto_cc_ARPROT = S_AXI_arprot[2:0]; + assign m00_couplers_to_auto_cc_ARQOS = S_AXI_arqos[3:0]; + assign m00_couplers_to_auto_cc_ARREGION = S_AXI_arregion[3:0]; + assign m00_couplers_to_auto_cc_ARSIZE = S_AXI_arsize[2:0]; + assign m00_couplers_to_auto_cc_ARVALID = S_AXI_arvalid; + assign m00_couplers_to_auto_cc_AWADDR = S_AXI_awaddr[63:0]; + assign m00_couplers_to_auto_cc_AWBURST = S_AXI_awburst[1:0]; + assign m00_couplers_to_auto_cc_AWCACHE = S_AXI_awcache[3:0]; + assign m00_couplers_to_auto_cc_AWID = S_AXI_awid[0]; + assign m00_couplers_to_auto_cc_AWLEN = S_AXI_awlen[7:0]; + assign m00_couplers_to_auto_cc_AWLOCK = S_AXI_awlock[0]; + assign m00_couplers_to_auto_cc_AWPROT = S_AXI_awprot[2:0]; + assign m00_couplers_to_auto_cc_AWQOS = S_AXI_awqos[3:0]; + assign m00_couplers_to_auto_cc_AWREGION = S_AXI_awregion[3:0]; + assign m00_couplers_to_auto_cc_AWSIZE = S_AXI_awsize[2:0]; + assign m00_couplers_to_auto_cc_AWVALID = S_AXI_awvalid; + assign m00_couplers_to_auto_cc_BREADY = S_AXI_bready; + assign m00_couplers_to_auto_cc_RREADY = S_AXI_rready; + assign m00_couplers_to_auto_cc_WDATA = S_AXI_wdata[511:0]; + assign m00_couplers_to_auto_cc_WLAST = S_AXI_wlast; + assign m00_couplers_to_auto_cc_WSTRB = S_AXI_wstrb[63:0]; + assign m00_couplers_to_auto_cc_WVALID = S_AXI_wvalid; + pcie_ddr_auto_cc_1 auto_cc + (.m_axi_aclk(M_ACLK_1), + .m_axi_araddr(auto_cc_to_m00_couplers_ARADDR), + .m_axi_arburst(auto_cc_to_m00_couplers_ARBURST), + .m_axi_arcache(auto_cc_to_m00_couplers_ARCACHE), + .m_axi_aresetn(M_ARESETN_1), + .m_axi_arid(auto_cc_to_m00_couplers_ARID), + .m_axi_arlen(auto_cc_to_m00_couplers_ARLEN), + .m_axi_arlock(auto_cc_to_m00_couplers_ARLOCK), + .m_axi_arprot(auto_cc_to_m00_couplers_ARPROT), + .m_axi_arqos(auto_cc_to_m00_couplers_ARQOS), + .m_axi_arready(auto_cc_to_m00_couplers_ARREADY), + .m_axi_arsize(auto_cc_to_m00_couplers_ARSIZE), + .m_axi_arvalid(auto_cc_to_m00_couplers_ARVALID), + .m_axi_awaddr(auto_cc_to_m00_couplers_AWADDR), + .m_axi_awburst(auto_cc_to_m00_couplers_AWBURST), + .m_axi_awcache(auto_cc_to_m00_couplers_AWCACHE), + .m_axi_awid(auto_cc_to_m00_couplers_AWID), + .m_axi_awlen(auto_cc_to_m00_couplers_AWLEN), + .m_axi_awlock(auto_cc_to_m00_couplers_AWLOCK), + .m_axi_awprot(auto_cc_to_m00_couplers_AWPROT), + .m_axi_awqos(auto_cc_to_m00_couplers_AWQOS), + .m_axi_awready(auto_cc_to_m00_couplers_AWREADY), + .m_axi_awsize(auto_cc_to_m00_couplers_AWSIZE), + .m_axi_awvalid(auto_cc_to_m00_couplers_AWVALID), + .m_axi_bid(auto_cc_to_m00_couplers_BID), + .m_axi_bready(auto_cc_to_m00_couplers_BREADY), + .m_axi_bresp(auto_cc_to_m00_couplers_BRESP), + .m_axi_bvalid(auto_cc_to_m00_couplers_BVALID), + .m_axi_rdata(auto_cc_to_m00_couplers_RDATA), + .m_axi_rid(auto_cc_to_m00_couplers_RID), + .m_axi_rlast(auto_cc_to_m00_couplers_RLAST), + .m_axi_rready(auto_cc_to_m00_couplers_RREADY), + .m_axi_rresp(auto_cc_to_m00_couplers_RRESP), + .m_axi_rvalid(auto_cc_to_m00_couplers_RVALID), + .m_axi_wdata(auto_cc_to_m00_couplers_WDATA), + .m_axi_wlast(auto_cc_to_m00_couplers_WLAST), + .m_axi_wready(auto_cc_to_m00_couplers_WREADY), + .m_axi_wstrb(auto_cc_to_m00_couplers_WSTRB), + .m_axi_wvalid(auto_cc_to_m00_couplers_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(m00_couplers_to_auto_cc_ARADDR[32:0]), + .s_axi_arburst(m00_couplers_to_auto_cc_ARBURST), + .s_axi_arcache(m00_couplers_to_auto_cc_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arid(m00_couplers_to_auto_cc_ARID), + .s_axi_arlen(m00_couplers_to_auto_cc_ARLEN), + .s_axi_arlock(m00_couplers_to_auto_cc_ARLOCK), + .s_axi_arprot(m00_couplers_to_auto_cc_ARPROT), + .s_axi_arqos(m00_couplers_to_auto_cc_ARQOS), + .s_axi_arready(m00_couplers_to_auto_cc_ARREADY), + .s_axi_arregion(m00_couplers_to_auto_cc_ARREGION), + .s_axi_arsize(m00_couplers_to_auto_cc_ARSIZE), + .s_axi_arvalid(m00_couplers_to_auto_cc_ARVALID), + .s_axi_awaddr(m00_couplers_to_auto_cc_AWADDR[32:0]), + .s_axi_awburst(m00_couplers_to_auto_cc_AWBURST), + .s_axi_awcache(m00_couplers_to_auto_cc_AWCACHE), + .s_axi_awid(m00_couplers_to_auto_cc_AWID), + .s_axi_awlen(m00_couplers_to_auto_cc_AWLEN), + .s_axi_awlock(m00_couplers_to_auto_cc_AWLOCK), + .s_axi_awprot(m00_couplers_to_auto_cc_AWPROT), + .s_axi_awqos(m00_couplers_to_auto_cc_AWQOS), + .s_axi_awready(m00_couplers_to_auto_cc_AWREADY), + .s_axi_awregion(m00_couplers_to_auto_cc_AWREGION), + .s_axi_awsize(m00_couplers_to_auto_cc_AWSIZE), + .s_axi_awvalid(m00_couplers_to_auto_cc_AWVALID), + .s_axi_bid(m00_couplers_to_auto_cc_BID), + .s_axi_bready(m00_couplers_to_auto_cc_BREADY), + .s_axi_bresp(m00_couplers_to_auto_cc_BRESP), + .s_axi_bvalid(m00_couplers_to_auto_cc_BVALID), + .s_axi_rdata(m00_couplers_to_auto_cc_RDATA), + .s_axi_rid(m00_couplers_to_auto_cc_RID), + .s_axi_rlast(m00_couplers_to_auto_cc_RLAST), + .s_axi_rready(m00_couplers_to_auto_cc_RREADY), + .s_axi_rresp(m00_couplers_to_auto_cc_RRESP), + .s_axi_rvalid(m00_couplers_to_auto_cc_RVALID), + .s_axi_wdata(m00_couplers_to_auto_cc_WDATA), + .s_axi_wlast(m00_couplers_to_auto_cc_WLAST), + .s_axi_wready(m00_couplers_to_auto_cc_WREADY), + .s_axi_wstrb(m00_couplers_to_auto_cc_WSTRB), + .s_axi_wvalid(m00_couplers_to_auto_cc_WVALID)); +endmodule + +(* CORE_GENERATION_INFO = "pcie_ddr,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=pcie_ddr,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=17,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=5,da_clkrst_cnt=2,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "pcie_ddr.hwdef" *) +module pcie_ddr + (ddr_addr, + ddr_axi_araddr, + ddr_axi_arburst, + ddr_axi_arcache, + ddr_axi_arid, + ddr_axi_arlen, + ddr_axi_arlock, + ddr_axi_arprot, + ddr_axi_arqos, + ddr_axi_arready, + ddr_axi_arsize, + ddr_axi_arvalid, + ddr_axi_awaddr, + ddr_axi_awburst, + ddr_axi_awcache, + ddr_axi_awid, + ddr_axi_awlen, + ddr_axi_awlock, + ddr_axi_awprot, + ddr_axi_awqos, + ddr_axi_awready, + ddr_axi_awsize, + ddr_axi_awvalid, + ddr_axi_bid, + ddr_axi_bready, + ddr_axi_bresp, + ddr_axi_bvalid, + ddr_axi_rdata, + ddr_axi_rid, + ddr_axi_rlast, + ddr_axi_rready, + ddr_axi_rresp, + ddr_axi_rvalid, + ddr_axi_wdata, + ddr_axi_wlast, + ddr_axi_wready, + ddr_axi_wstrb, + ddr_axi_wvalid, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + init_calib_complete, + pcie_clk_clk_n, + pcie_clk_clk_p, + pcie_mgt_rxn, + pcie_mgt_rxp, + pcie_mgt_txn, + pcie_mgt_txp, + pcie_msi_enable, + pcie_user_lnk_up, + pcie_usr_irq_req, + sys_clk, + sys_rst_n_0, + sys_rstn); + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ddr, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [15:0]ddr_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ddr_axi, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pcie_ddr_clk_in1_0, DATA_WIDTH 32, FREQ_HZ 200000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]ddr_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [1:0]ddr_axi_arburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_arcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [0:0]ddr_axi_arid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [7:0]ddr_axi_arlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [0:0]ddr_axi_arlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [2:0]ddr_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_arqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [2:0]ddr_axi_arsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [31:0]ddr_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [1:0]ddr_axi_awburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_awcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [0:0]ddr_axi_awid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [7:0]ddr_axi_awlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [0:0]ddr_axi_awlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [2:0]ddr_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_awqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [2:0]ddr_axi_awsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [0:0]ddr_axi_bid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [1:0]ddr_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [31:0]ddr_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [0:0]ddr_axi_rid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_rlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output [1:0]ddr_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [31:0]ddr_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_wlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) output ddr_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input [3:0]ddr_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 ddr_axi " *) input ddr_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [2:0]ddr_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output ddr_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [7:0]ddr_dm; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) inout [63:0]ddr_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) inout [7:0]ddr_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) inout [7:0]ddr_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output [1:0]ddr_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output ddr_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output ddr_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr " *) output ddr_we_n; + output init_calib_complete; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clk " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME pcie_clk, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]pcie_clk_clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clk " *) input [0:0]pcie_clk_clk_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt " *) input [7:0]pcie_mgt_rxn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt " *) input [7:0]pcie_mgt_rxp; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt " *) output [7:0]pcie_mgt_txn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt " *) output [7:0]pcie_mgt_txp; + output pcie_msi_enable; + output pcie_user_lnk_up; + input [0:0]pcie_usr_irq_req; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYS_CLK, ASSOCIATED_BUSIF ddr_axi, ASSOCIATED_RESET sys_rstn, CLK_DOMAIN pcie_ddr_clk_in1_0, FREQ_HZ 200000000, INSERT_VIP 0, PHASE 0.000" *) input sys_clk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.SYS_RST_N_0 RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.SYS_RST_N_0, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input sys_rst_n_0; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.SYS_RSTN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.SYS_RSTN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input sys_rstn; + + wire [0:0]CLK_IN_D_0_1_CLK_N; + wire [0:0]CLK_IN_D_0_1_CLK_P; + wire [31:0]S01_AXI_0_1_ARADDR; + wire [1:0]S01_AXI_0_1_ARBURST; + wire [3:0]S01_AXI_0_1_ARCACHE; + wire [0:0]S01_AXI_0_1_ARID; + wire [7:0]S01_AXI_0_1_ARLEN; + wire [0:0]S01_AXI_0_1_ARLOCK; + wire [2:0]S01_AXI_0_1_ARPROT; + wire [3:0]S01_AXI_0_1_ARQOS; + wire S01_AXI_0_1_ARREADY; + wire [2:0]S01_AXI_0_1_ARSIZE; + wire S01_AXI_0_1_ARVALID; + wire [31:0]S01_AXI_0_1_AWADDR; + wire [1:0]S01_AXI_0_1_AWBURST; + wire [3:0]S01_AXI_0_1_AWCACHE; + wire [0:0]S01_AXI_0_1_AWID; + wire [7:0]S01_AXI_0_1_AWLEN; + wire [0:0]S01_AXI_0_1_AWLOCK; + wire [2:0]S01_AXI_0_1_AWPROT; + wire [3:0]S01_AXI_0_1_AWQOS; + wire S01_AXI_0_1_AWREADY; + wire [2:0]S01_AXI_0_1_AWSIZE; + wire S01_AXI_0_1_AWVALID; + wire [0:0]S01_AXI_0_1_BID; + wire S01_AXI_0_1_BREADY; + wire [1:0]S01_AXI_0_1_BRESP; + wire S01_AXI_0_1_BVALID; + wire [31:0]S01_AXI_0_1_RDATA; + wire [0:0]S01_AXI_0_1_RID; + wire S01_AXI_0_1_RLAST; + wire S01_AXI_0_1_RREADY; + wire [1:0]S01_AXI_0_1_RRESP; + wire S01_AXI_0_1_RVALID; + wire [31:0]S01_AXI_0_1_WDATA; + wire S01_AXI_0_1_WLAST; + wire S01_AXI_0_1_WREADY; + wire [3:0]S01_AXI_0_1_WSTRB; + wire S01_AXI_0_1_WVALID; + wire [32:0]axi_interconnect_0_M00_AXI_ARADDR; + wire [1:0]axi_interconnect_0_M00_AXI_ARBURST; + wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE; + wire [0:0]axi_interconnect_0_M00_AXI_ARID; + wire [7:0]axi_interconnect_0_M00_AXI_ARLEN; + wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK; + wire [2:0]axi_interconnect_0_M00_AXI_ARPROT; + wire [3:0]axi_interconnect_0_M00_AXI_ARQOS; + wire axi_interconnect_0_M00_AXI_ARREADY; + wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE; + wire axi_interconnect_0_M00_AXI_ARVALID; + wire [32:0]axi_interconnect_0_M00_AXI_AWADDR; + wire [1:0]axi_interconnect_0_M00_AXI_AWBURST; + wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE; + wire [0:0]axi_interconnect_0_M00_AXI_AWID; + wire [7:0]axi_interconnect_0_M00_AXI_AWLEN; + wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK; + wire [2:0]axi_interconnect_0_M00_AXI_AWPROT; + wire [3:0]axi_interconnect_0_M00_AXI_AWQOS; + wire axi_interconnect_0_M00_AXI_AWREADY; + wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE; + wire axi_interconnect_0_M00_AXI_AWVALID; + wire [0:0]axi_interconnect_0_M00_AXI_BID; + wire axi_interconnect_0_M00_AXI_BREADY; + wire [1:0]axi_interconnect_0_M00_AXI_BRESP; + wire axi_interconnect_0_M00_AXI_BVALID; + wire [511:0]axi_interconnect_0_M00_AXI_RDATA; + wire [0:0]axi_interconnect_0_M00_AXI_RID; + wire axi_interconnect_0_M00_AXI_RLAST; + wire axi_interconnect_0_M00_AXI_RREADY; + wire [1:0]axi_interconnect_0_M00_AXI_RRESP; + wire axi_interconnect_0_M00_AXI_RVALID; + wire [511:0]axi_interconnect_0_M00_AXI_WDATA; + wire axi_interconnect_0_M00_AXI_WLAST; + wire axi_interconnect_0_M00_AXI_WREADY; + wire [63:0]axi_interconnect_0_M00_AXI_WSTRB; + wire axi_interconnect_0_M00_AXI_WVALID; + wire clk_in1_0_1; + wire clk_wiz_0_clk_out1; + wire clk_wiz_0_locked; + wire [15:0]mig_7series_0_DDR3_ADDR; + wire [2:0]mig_7series_0_DDR3_BA; + wire mig_7series_0_DDR3_CAS_N; + wire [1:0]mig_7series_0_DDR3_CKE; + wire [1:0]mig_7series_0_DDR3_CK_N; + wire [1:0]mig_7series_0_DDR3_CK_P; + wire [1:0]mig_7series_0_DDR3_CS_N; + wire [7:0]mig_7series_0_DDR3_DM; + wire [63:0]mig_7series_0_DDR3_DQ; + wire [7:0]mig_7series_0_DDR3_DQS_N; + wire [7:0]mig_7series_0_DDR3_DQS_P; + wire [1:0]mig_7series_0_DDR3_ODT; + wire mig_7series_0_DDR3_RAS_N; + wire mig_7series_0_DDR3_RESET_N; + wire mig_7series_0_DDR3_WE_N; + wire mig_7series_0_init_calib_complete; + wire mig_7series_0_mmcm_locked; + wire mig_7series_0_ui_clk; + wire mig_7series_0_ui_clk_sync_rst; + wire resetn_0_1; + wire [0:0]rst_clk_wiz_0_200M_peripheral_aresetn; + wire [0:0]rst_mig_7series_0_100M_peripheral_aresetn; + wire sys_rst_n_0_1; + wire [0:0]usr_irq_req_0_1; + wire [0:0]util_ds_buf_0_IBUF_OUT; + wire [63:0]xdma_0_M_AXI_ARADDR; + wire [1:0]xdma_0_M_AXI_ARBURST; + wire [3:0]xdma_0_M_AXI_ARCACHE; + wire [3:0]xdma_0_M_AXI_ARID; + wire [7:0]xdma_0_M_AXI_ARLEN; + wire xdma_0_M_AXI_ARLOCK; + wire [2:0]xdma_0_M_AXI_ARPROT; + wire xdma_0_M_AXI_ARREADY; + wire [2:0]xdma_0_M_AXI_ARSIZE; + wire xdma_0_M_AXI_ARVALID; + wire [63:0]xdma_0_M_AXI_AWADDR; + wire [1:0]xdma_0_M_AXI_AWBURST; + wire [3:0]xdma_0_M_AXI_AWCACHE; + wire [3:0]xdma_0_M_AXI_AWID; + wire [7:0]xdma_0_M_AXI_AWLEN; + wire xdma_0_M_AXI_AWLOCK; + wire [2:0]xdma_0_M_AXI_AWPROT; + wire xdma_0_M_AXI_AWREADY; + wire [2:0]xdma_0_M_AXI_AWSIZE; + wire xdma_0_M_AXI_AWVALID; + wire [3:0]xdma_0_M_AXI_BID; + wire xdma_0_M_AXI_BREADY; + wire [1:0]xdma_0_M_AXI_BRESP; + wire xdma_0_M_AXI_BVALID; + wire [127:0]xdma_0_M_AXI_RDATA; + wire [3:0]xdma_0_M_AXI_RID; + wire xdma_0_M_AXI_RLAST; + wire xdma_0_M_AXI_RREADY; + wire [1:0]xdma_0_M_AXI_RRESP; + wire xdma_0_M_AXI_RVALID; + wire [127:0]xdma_0_M_AXI_WDATA; + wire xdma_0_M_AXI_WLAST; + wire xdma_0_M_AXI_WREADY; + wire [15:0]xdma_0_M_AXI_WSTRB; + wire xdma_0_M_AXI_WVALID; + wire xdma_0_axi_aclk; + wire xdma_0_axi_aresetn; + wire xdma_0_msi_enable; + wire [7:0]xdma_0_pcie_mgt_rxn; + wire [7:0]xdma_0_pcie_mgt_rxp; + wire [7:0]xdma_0_pcie_mgt_txn; + wire [7:0]xdma_0_pcie_mgt_txp; + wire xdma_0_user_lnk_up; + + assign CLK_IN_D_0_1_CLK_N = pcie_clk_clk_n[0]; + assign CLK_IN_D_0_1_CLK_P = pcie_clk_clk_p[0]; + assign S01_AXI_0_1_ARADDR = ddr_axi_araddr[31:0]; + assign S01_AXI_0_1_ARBURST = ddr_axi_arburst[1:0]; + assign S01_AXI_0_1_ARCACHE = ddr_axi_arcache[3:0]; + assign S01_AXI_0_1_ARID = ddr_axi_arid[0]; + assign S01_AXI_0_1_ARLEN = ddr_axi_arlen[7:0]; + assign S01_AXI_0_1_ARLOCK = ddr_axi_arlock[0]; + assign S01_AXI_0_1_ARPROT = ddr_axi_arprot[2:0]; + assign S01_AXI_0_1_ARQOS = ddr_axi_arqos[3:0]; + assign S01_AXI_0_1_ARSIZE = ddr_axi_arsize[2:0]; + assign S01_AXI_0_1_ARVALID = ddr_axi_arvalid; + assign S01_AXI_0_1_AWADDR = ddr_axi_awaddr[31:0]; + assign S01_AXI_0_1_AWBURST = ddr_axi_awburst[1:0]; + assign S01_AXI_0_1_AWCACHE = ddr_axi_awcache[3:0]; + assign S01_AXI_0_1_AWID = ddr_axi_awid[0]; + assign S01_AXI_0_1_AWLEN = ddr_axi_awlen[7:0]; + assign S01_AXI_0_1_AWLOCK = ddr_axi_awlock[0]; + assign S01_AXI_0_1_AWPROT = ddr_axi_awprot[2:0]; + assign S01_AXI_0_1_AWQOS = ddr_axi_awqos[3:0]; + assign S01_AXI_0_1_AWSIZE = ddr_axi_awsize[2:0]; + assign S01_AXI_0_1_AWVALID = ddr_axi_awvalid; + assign S01_AXI_0_1_BREADY = ddr_axi_bready; + assign S01_AXI_0_1_RREADY = ddr_axi_rready; + assign S01_AXI_0_1_WDATA = ddr_axi_wdata[31:0]; + assign S01_AXI_0_1_WLAST = ddr_axi_wlast; + assign S01_AXI_0_1_WSTRB = ddr_axi_wstrb[3:0]; + assign S01_AXI_0_1_WVALID = ddr_axi_wvalid; + assign clk_in1_0_1 = sys_clk; + assign ddr_addr[15:0] = mig_7series_0_DDR3_ADDR; + assign ddr_axi_arready = S01_AXI_0_1_ARREADY; + assign ddr_axi_awready = S01_AXI_0_1_AWREADY; + assign ddr_axi_bid[0] = S01_AXI_0_1_BID; + assign ddr_axi_bresp[1:0] = S01_AXI_0_1_BRESP; + assign ddr_axi_bvalid = S01_AXI_0_1_BVALID; + assign ddr_axi_rdata[31:0] = S01_AXI_0_1_RDATA; + assign ddr_axi_rid[0] = S01_AXI_0_1_RID; + assign ddr_axi_rlast = S01_AXI_0_1_RLAST; + assign ddr_axi_rresp[1:0] = S01_AXI_0_1_RRESP; + assign ddr_axi_rvalid = S01_AXI_0_1_RVALID; + assign ddr_axi_wready = S01_AXI_0_1_WREADY; + assign ddr_ba[2:0] = mig_7series_0_DDR3_BA; + assign ddr_cas_n = mig_7series_0_DDR3_CAS_N; + assign ddr_ck_n[1:0] = mig_7series_0_DDR3_CK_N; + assign ddr_ck_p[1:0] = mig_7series_0_DDR3_CK_P; + assign ddr_cke[1:0] = mig_7series_0_DDR3_CKE; + assign ddr_cs_n[1:0] = mig_7series_0_DDR3_CS_N; + assign ddr_dm[7:0] = mig_7series_0_DDR3_DM; + assign ddr_odt[1:0] = mig_7series_0_DDR3_ODT; + assign ddr_ras_n = mig_7series_0_DDR3_RAS_N; + assign ddr_reset_n = mig_7series_0_DDR3_RESET_N; + assign ddr_we_n = mig_7series_0_DDR3_WE_N; + assign init_calib_complete = mig_7series_0_init_calib_complete; + assign pcie_mgt_txn[7:0] = xdma_0_pcie_mgt_txn; + assign pcie_mgt_txp[7:0] = xdma_0_pcie_mgt_txp; + assign pcie_msi_enable = xdma_0_msi_enable; + assign pcie_user_lnk_up = xdma_0_user_lnk_up; + assign resetn_0_1 = sys_rstn; + assign sys_rst_n_0_1 = sys_rst_n_0; + assign usr_irq_req_0_1 = pcie_usr_irq_req[0]; + assign xdma_0_pcie_mgt_rxn = pcie_mgt_rxn[7:0]; + assign xdma_0_pcie_mgt_rxp = pcie_mgt_rxp[7:0]; + pcie_ddr_axi_interconnect_0_1 axi_interconnect_0 + (.ACLK(clk_wiz_0_clk_out1), + .ARESETN(rst_clk_wiz_0_200M_peripheral_aresetn), + .M00_ACLK(mig_7series_0_ui_clk), + .M00_ARESETN(rst_mig_7series_0_100M_peripheral_aresetn), + .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR), + .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST), + .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE), + .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID), + .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN), + .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK), + .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT), + .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS), + .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY), + .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE), + .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID), + .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR), + .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST), + .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE), + .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID), + .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN), + .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK), + .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT), + .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS), + .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY), + .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE), + .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID), + .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID), + .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY), + .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP), + .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID), + .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA), + .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID), + .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST), + .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY), + .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP), + .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID), + .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA), + .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST), + .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY), + .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB), + .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID), + .S00_ACLK(xdma_0_axi_aclk), + .S00_ARESETN(xdma_0_axi_aresetn), + .S00_AXI_araddr(xdma_0_M_AXI_ARADDR), + .S00_AXI_arburst(xdma_0_M_AXI_ARBURST), + .S00_AXI_arcache(xdma_0_M_AXI_ARCACHE), + .S00_AXI_arid(xdma_0_M_AXI_ARID), + .S00_AXI_arlen(xdma_0_M_AXI_ARLEN), + .S00_AXI_arlock(xdma_0_M_AXI_ARLOCK), + .S00_AXI_arprot(xdma_0_M_AXI_ARPROT), + .S00_AXI_arready(xdma_0_M_AXI_ARREADY), + .S00_AXI_arsize(xdma_0_M_AXI_ARSIZE), + .S00_AXI_arvalid(xdma_0_M_AXI_ARVALID), + .S00_AXI_awaddr(xdma_0_M_AXI_AWADDR), + .S00_AXI_awburst(xdma_0_M_AXI_AWBURST), + .S00_AXI_awcache(xdma_0_M_AXI_AWCACHE), + .S00_AXI_awid(xdma_0_M_AXI_AWID), + .S00_AXI_awlen(xdma_0_M_AXI_AWLEN), + .S00_AXI_awlock(xdma_0_M_AXI_AWLOCK), + .S00_AXI_awprot(xdma_0_M_AXI_AWPROT), + .S00_AXI_awready(xdma_0_M_AXI_AWREADY), + .S00_AXI_awsize(xdma_0_M_AXI_AWSIZE), + .S00_AXI_awvalid(xdma_0_M_AXI_AWVALID), + .S00_AXI_bid(xdma_0_M_AXI_BID), + .S00_AXI_bready(xdma_0_M_AXI_BREADY), + .S00_AXI_bresp(xdma_0_M_AXI_BRESP), + .S00_AXI_bvalid(xdma_0_M_AXI_BVALID), + .S00_AXI_rdata(xdma_0_M_AXI_RDATA), + .S00_AXI_rid(xdma_0_M_AXI_RID), + .S00_AXI_rlast(xdma_0_M_AXI_RLAST), + .S00_AXI_rready(xdma_0_M_AXI_RREADY), + .S00_AXI_rresp(xdma_0_M_AXI_RRESP), + .S00_AXI_rvalid(xdma_0_M_AXI_RVALID), + .S00_AXI_wdata(xdma_0_M_AXI_WDATA), + .S00_AXI_wlast(xdma_0_M_AXI_WLAST), + .S00_AXI_wready(xdma_0_M_AXI_WREADY), + .S00_AXI_wstrb(xdma_0_M_AXI_WSTRB), + .S00_AXI_wvalid(xdma_0_M_AXI_WVALID), + .S01_ACLK(clk_in1_0_1), + .S01_ARESETN(resetn_0_1), + .S01_AXI_araddr(S01_AXI_0_1_ARADDR), + .S01_AXI_arburst(S01_AXI_0_1_ARBURST), + .S01_AXI_arcache(S01_AXI_0_1_ARCACHE), + .S01_AXI_arid(S01_AXI_0_1_ARID), + .S01_AXI_arlen(S01_AXI_0_1_ARLEN), + .S01_AXI_arlock(S01_AXI_0_1_ARLOCK), + .S01_AXI_arprot(S01_AXI_0_1_ARPROT), + .S01_AXI_arqos(S01_AXI_0_1_ARQOS), + .S01_AXI_arready(S01_AXI_0_1_ARREADY), + .S01_AXI_arsize(S01_AXI_0_1_ARSIZE), + .S01_AXI_arvalid(S01_AXI_0_1_ARVALID), + .S01_AXI_awaddr(S01_AXI_0_1_AWADDR), + .S01_AXI_awburst(S01_AXI_0_1_AWBURST), + .S01_AXI_awcache(S01_AXI_0_1_AWCACHE), + .S01_AXI_awid(S01_AXI_0_1_AWID), + .S01_AXI_awlen(S01_AXI_0_1_AWLEN), + .S01_AXI_awlock(S01_AXI_0_1_AWLOCK), + .S01_AXI_awprot(S01_AXI_0_1_AWPROT), + .S01_AXI_awqos(S01_AXI_0_1_AWQOS), + .S01_AXI_awready(S01_AXI_0_1_AWREADY), + .S01_AXI_awsize(S01_AXI_0_1_AWSIZE), + .S01_AXI_awvalid(S01_AXI_0_1_AWVALID), + .S01_AXI_bid(S01_AXI_0_1_BID), + .S01_AXI_bready(S01_AXI_0_1_BREADY), + .S01_AXI_bresp(S01_AXI_0_1_BRESP), + .S01_AXI_bvalid(S01_AXI_0_1_BVALID), + .S01_AXI_rdata(S01_AXI_0_1_RDATA), + .S01_AXI_rid(S01_AXI_0_1_RID), + .S01_AXI_rlast(S01_AXI_0_1_RLAST), + .S01_AXI_rready(S01_AXI_0_1_RREADY), + .S01_AXI_rresp(S01_AXI_0_1_RRESP), + .S01_AXI_rvalid(S01_AXI_0_1_RVALID), + .S01_AXI_wdata(S01_AXI_0_1_WDATA), + .S01_AXI_wlast(S01_AXI_0_1_WLAST), + .S01_AXI_wready(S01_AXI_0_1_WREADY), + .S01_AXI_wstrb(S01_AXI_0_1_WSTRB), + .S01_AXI_wvalid(S01_AXI_0_1_WVALID)); + pcie_ddr_clk_wiz_0_0 clk_wiz_0 + (.clk_in1(clk_in1_0_1), + .clk_out1(clk_wiz_0_clk_out1), + .locked(clk_wiz_0_locked), + .resetn(resetn_0_1)); + pcie_ddr_mig_7series_0_0 mig_7series_0 + (.aresetn(rst_mig_7series_0_100M_peripheral_aresetn), + .ddr3_addr(mig_7series_0_DDR3_ADDR), + .ddr3_ba(mig_7series_0_DDR3_BA), + .ddr3_cas_n(mig_7series_0_DDR3_CAS_N), + .ddr3_ck_n(mig_7series_0_DDR3_CK_N), + .ddr3_ck_p(mig_7series_0_DDR3_CK_P), + .ddr3_cke(mig_7series_0_DDR3_CKE), + .ddr3_cs_n(mig_7series_0_DDR3_CS_N), + .ddr3_dm(mig_7series_0_DDR3_DM), + .ddr3_dq(ddr_dq[63:0]), + .ddr3_dqs_n(ddr_dqs_n[7:0]), + .ddr3_dqs_p(ddr_dqs_p[7:0]), + .ddr3_odt(mig_7series_0_DDR3_ODT), + .ddr3_ras_n(mig_7series_0_DDR3_RAS_N), + .ddr3_reset_n(mig_7series_0_DDR3_RESET_N), + .ddr3_we_n(mig_7series_0_DDR3_WE_N), + .init_calib_complete(mig_7series_0_init_calib_complete), + .mmcm_locked(mig_7series_0_mmcm_locked), + .s_axi_araddr(axi_interconnect_0_M00_AXI_ARADDR), + .s_axi_arburst(axi_interconnect_0_M00_AXI_ARBURST), + .s_axi_arcache(axi_interconnect_0_M00_AXI_ARCACHE), + .s_axi_arid(axi_interconnect_0_M00_AXI_ARID), + .s_axi_arlen(axi_interconnect_0_M00_AXI_ARLEN), + .s_axi_arlock(axi_interconnect_0_M00_AXI_ARLOCK), + .s_axi_arprot(axi_interconnect_0_M00_AXI_ARPROT), + .s_axi_arqos(axi_interconnect_0_M00_AXI_ARQOS), + .s_axi_arready(axi_interconnect_0_M00_AXI_ARREADY), + .s_axi_arsize(axi_interconnect_0_M00_AXI_ARSIZE), + .s_axi_arvalid(axi_interconnect_0_M00_AXI_ARVALID), + .s_axi_awaddr(axi_interconnect_0_M00_AXI_AWADDR), + .s_axi_awburst(axi_interconnect_0_M00_AXI_AWBURST), + .s_axi_awcache(axi_interconnect_0_M00_AXI_AWCACHE), + .s_axi_awid(axi_interconnect_0_M00_AXI_AWID), + .s_axi_awlen(axi_interconnect_0_M00_AXI_AWLEN), + .s_axi_awlock(axi_interconnect_0_M00_AXI_AWLOCK), + .s_axi_awprot(axi_interconnect_0_M00_AXI_AWPROT), + .s_axi_awqos(axi_interconnect_0_M00_AXI_AWQOS), + .s_axi_awready(axi_interconnect_0_M00_AXI_AWREADY), + .s_axi_awsize(axi_interconnect_0_M00_AXI_AWSIZE), + .s_axi_awvalid(axi_interconnect_0_M00_AXI_AWVALID), + .s_axi_bid(axi_interconnect_0_M00_AXI_BID), + .s_axi_bready(axi_interconnect_0_M00_AXI_BREADY), + .s_axi_bresp(axi_interconnect_0_M00_AXI_BRESP), + .s_axi_bvalid(axi_interconnect_0_M00_AXI_BVALID), + .s_axi_rdata(axi_interconnect_0_M00_AXI_RDATA), + .s_axi_rid(axi_interconnect_0_M00_AXI_RID), + .s_axi_rlast(axi_interconnect_0_M00_AXI_RLAST), + .s_axi_rready(axi_interconnect_0_M00_AXI_RREADY), + .s_axi_rresp(axi_interconnect_0_M00_AXI_RRESP), + .s_axi_rvalid(axi_interconnect_0_M00_AXI_RVALID), + .s_axi_wdata(axi_interconnect_0_M00_AXI_WDATA), + .s_axi_wlast(axi_interconnect_0_M00_AXI_WLAST), + .s_axi_wready(axi_interconnect_0_M00_AXI_WREADY), + .s_axi_wstrb(axi_interconnect_0_M00_AXI_WSTRB), + .s_axi_wvalid(axi_interconnect_0_M00_AXI_WVALID), + .sys_clk_i(clk_wiz_0_clk_out1), + .sys_rst(clk_wiz_0_locked), + .ui_clk(mig_7series_0_ui_clk), + .ui_clk_sync_rst(mig_7series_0_ui_clk_sync_rst)); + pcie_ddr_rst_clk_wiz_0_200M_0 rst_clk_wiz_0_200M + (.aux_reset_in(1'b1), + .dcm_locked(clk_wiz_0_locked), + .ext_reset_in(resetn_0_1), + .mb_debug_sys_rst(1'b0), + .peripheral_aresetn(rst_clk_wiz_0_200M_peripheral_aresetn), + .slowest_sync_clk(clk_wiz_0_clk_out1)); + pcie_ddr_rst_mig_7series_0_100M_4 rst_mig_7series_0_100M + (.aux_reset_in(1'b1), + .dcm_locked(mig_7series_0_mmcm_locked), + .ext_reset_in(mig_7series_0_ui_clk_sync_rst), + .mb_debug_sys_rst(1'b0), + .peripheral_aresetn(rst_mig_7series_0_100M_peripheral_aresetn), + .slowest_sync_clk(mig_7series_0_ui_clk)); + pcie_ddr_util_ds_buf_0_0 util_ds_buf_0 + (.IBUF_DS_N(CLK_IN_D_0_1_CLK_N), + .IBUF_DS_P(CLK_IN_D_0_1_CLK_P), + .IBUF_OUT(util_ds_buf_0_IBUF_OUT)); + pcie_ddr_xdma_0_0 xdma_0 + (.axi_aclk(xdma_0_axi_aclk), + .axi_aresetn(xdma_0_axi_aresetn), + .cfg_mgmt_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .cfg_mgmt_byte_enable({1'b0,1'b0,1'b0,1'b0}), + .cfg_mgmt_read(1'b0), + .cfg_mgmt_type1_cfg_reg_access(1'b0), + .cfg_mgmt_write(1'b0), + .cfg_mgmt_write_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_araddr(xdma_0_M_AXI_ARADDR), + .m_axi_arburst(xdma_0_M_AXI_ARBURST), + .m_axi_arcache(xdma_0_M_AXI_ARCACHE), + .m_axi_arid(xdma_0_M_AXI_ARID), + .m_axi_arlen(xdma_0_M_AXI_ARLEN), + .m_axi_arlock(xdma_0_M_AXI_ARLOCK), + .m_axi_arprot(xdma_0_M_AXI_ARPROT), + .m_axi_arready(xdma_0_M_AXI_ARREADY), + .m_axi_arsize(xdma_0_M_AXI_ARSIZE), + .m_axi_arvalid(xdma_0_M_AXI_ARVALID), + .m_axi_awaddr(xdma_0_M_AXI_AWADDR), + .m_axi_awburst(xdma_0_M_AXI_AWBURST), + .m_axi_awcache(xdma_0_M_AXI_AWCACHE), + .m_axi_awid(xdma_0_M_AXI_AWID), + .m_axi_awlen(xdma_0_M_AXI_AWLEN), + .m_axi_awlock(xdma_0_M_AXI_AWLOCK), + .m_axi_awprot(xdma_0_M_AXI_AWPROT), + .m_axi_awready(xdma_0_M_AXI_AWREADY), + .m_axi_awsize(xdma_0_M_AXI_AWSIZE), + .m_axi_awvalid(xdma_0_M_AXI_AWVALID), + .m_axi_bid(xdma_0_M_AXI_BID), + .m_axi_bready(xdma_0_M_AXI_BREADY), + .m_axi_bresp(xdma_0_M_AXI_BRESP), + .m_axi_bvalid(xdma_0_M_AXI_BVALID), + .m_axi_rdata(xdma_0_M_AXI_RDATA), + .m_axi_rid(xdma_0_M_AXI_RID), + .m_axi_rlast(xdma_0_M_AXI_RLAST), + .m_axi_rready(xdma_0_M_AXI_RREADY), + .m_axi_rresp(xdma_0_M_AXI_RRESP), + .m_axi_rvalid(xdma_0_M_AXI_RVALID), + .m_axi_wdata(xdma_0_M_AXI_WDATA), + .m_axi_wlast(xdma_0_M_AXI_WLAST), + .m_axi_wready(xdma_0_M_AXI_WREADY), + .m_axi_wstrb(xdma_0_M_AXI_WSTRB), + .m_axi_wvalid(xdma_0_M_AXI_WVALID), + .msi_enable(xdma_0_msi_enable), + .pci_exp_rxn(xdma_0_pcie_mgt_rxn), + .pci_exp_rxp(xdma_0_pcie_mgt_rxp), + .pci_exp_txn(xdma_0_pcie_mgt_txn), + .pci_exp_txp(xdma_0_pcie_mgt_txp), + .sys_clk(util_ds_buf_0_IBUF_OUT), + .sys_rst_n(sys_rst_n_0_1), + .user_lnk_up(xdma_0_user_lnk_up), + .usr_irq_req(usr_irq_req_0_1)); +endmodule + +module pcie_ddr_axi_interconnect_0_1 + (ACLK, + ARESETN, + M00_ACLK, + M00_ARESETN, + M00_AXI_araddr, + M00_AXI_arburst, + M00_AXI_arcache, + M00_AXI_arid, + M00_AXI_arlen, + M00_AXI_arlock, + M00_AXI_arprot, + M00_AXI_arqos, + M00_AXI_arready, + M00_AXI_arsize, + M00_AXI_arvalid, + M00_AXI_awaddr, + M00_AXI_awburst, + M00_AXI_awcache, + M00_AXI_awid, + M00_AXI_awlen, + M00_AXI_awlock, + M00_AXI_awprot, + M00_AXI_awqos, + M00_AXI_awready, + M00_AXI_awsize, + M00_AXI_awvalid, + M00_AXI_bid, + M00_AXI_bready, + M00_AXI_bresp, + M00_AXI_bvalid, + M00_AXI_rdata, + M00_AXI_rid, + M00_AXI_rlast, + M00_AXI_rready, + M00_AXI_rresp, + M00_AXI_rvalid, + M00_AXI_wdata, + M00_AXI_wlast, + M00_AXI_wready, + M00_AXI_wstrb, + M00_AXI_wvalid, + S00_ACLK, + S00_ARESETN, + S00_AXI_araddr, + S00_AXI_arburst, + S00_AXI_arcache, + S00_AXI_arid, + S00_AXI_arlen, + S00_AXI_arlock, + S00_AXI_arprot, + S00_AXI_arready, + S00_AXI_arsize, + S00_AXI_arvalid, + S00_AXI_awaddr, + S00_AXI_awburst, + S00_AXI_awcache, + S00_AXI_awid, + S00_AXI_awlen, + S00_AXI_awlock, + S00_AXI_awprot, + S00_AXI_awready, + S00_AXI_awsize, + S00_AXI_awvalid, + S00_AXI_bid, + S00_AXI_bready, + S00_AXI_bresp, + S00_AXI_bvalid, + S00_AXI_rdata, + S00_AXI_rid, + S00_AXI_rlast, + S00_AXI_rready, + S00_AXI_rresp, + S00_AXI_rvalid, + S00_AXI_wdata, + S00_AXI_wlast, + S00_AXI_wready, + S00_AXI_wstrb, + S00_AXI_wvalid, + S01_ACLK, + S01_ARESETN, + S01_AXI_araddr, + S01_AXI_arburst, + S01_AXI_arcache, + S01_AXI_arid, + S01_AXI_arlen, + S01_AXI_arlock, + S01_AXI_arprot, + S01_AXI_arqos, + S01_AXI_arready, + S01_AXI_arsize, + S01_AXI_arvalid, + S01_AXI_awaddr, + S01_AXI_awburst, + S01_AXI_awcache, + S01_AXI_awid, + S01_AXI_awlen, + S01_AXI_awlock, + S01_AXI_awprot, + S01_AXI_awqos, + S01_AXI_awready, + S01_AXI_awsize, + S01_AXI_awvalid, + S01_AXI_bid, + S01_AXI_bready, + S01_AXI_bresp, + S01_AXI_bvalid, + S01_AXI_rdata, + S01_AXI_rid, + S01_AXI_rlast, + S01_AXI_rready, + S01_AXI_rresp, + S01_AXI_rvalid, + S01_AXI_wdata, + S01_AXI_wlast, + S01_AXI_wready, + S01_AXI_wstrb, + S01_AXI_wvalid); + input ACLK; + input ARESETN; + input M00_ACLK; + input M00_ARESETN; + output [32:0]M00_AXI_araddr; + output [1:0]M00_AXI_arburst; + output [3:0]M00_AXI_arcache; + output [0:0]M00_AXI_arid; + output [7:0]M00_AXI_arlen; + output [0:0]M00_AXI_arlock; + output [2:0]M00_AXI_arprot; + output [3:0]M00_AXI_arqos; + input M00_AXI_arready; + output [2:0]M00_AXI_arsize; + output M00_AXI_arvalid; + output [32:0]M00_AXI_awaddr; + output [1:0]M00_AXI_awburst; + output [3:0]M00_AXI_awcache; + output [0:0]M00_AXI_awid; + output [7:0]M00_AXI_awlen; + output [0:0]M00_AXI_awlock; + output [2:0]M00_AXI_awprot; + output [3:0]M00_AXI_awqos; + input M00_AXI_awready; + output [2:0]M00_AXI_awsize; + output M00_AXI_awvalid; + input [0:0]M00_AXI_bid; + output M00_AXI_bready; + input [1:0]M00_AXI_bresp; + input M00_AXI_bvalid; + input [511:0]M00_AXI_rdata; + input [0:0]M00_AXI_rid; + input M00_AXI_rlast; + output M00_AXI_rready; + input [1:0]M00_AXI_rresp; + input M00_AXI_rvalid; + output [511:0]M00_AXI_wdata; + output M00_AXI_wlast; + input M00_AXI_wready; + output [63:0]M00_AXI_wstrb; + output M00_AXI_wvalid; + input S00_ACLK; + input S00_ARESETN; + input [63:0]S00_AXI_araddr; + input [1:0]S00_AXI_arburst; + input [3:0]S00_AXI_arcache; + input [3:0]S00_AXI_arid; + input [7:0]S00_AXI_arlen; + input [0:0]S00_AXI_arlock; + input [2:0]S00_AXI_arprot; + output S00_AXI_arready; + input [2:0]S00_AXI_arsize; + input S00_AXI_arvalid; + input [63:0]S00_AXI_awaddr; + input [1:0]S00_AXI_awburst; + input [3:0]S00_AXI_awcache; + input [3:0]S00_AXI_awid; + input [7:0]S00_AXI_awlen; + input [0:0]S00_AXI_awlock; + input [2:0]S00_AXI_awprot; + output S00_AXI_awready; + input [2:0]S00_AXI_awsize; + input S00_AXI_awvalid; + output [3:0]S00_AXI_bid; + input S00_AXI_bready; + output [1:0]S00_AXI_bresp; + output S00_AXI_bvalid; + output [127:0]S00_AXI_rdata; + output [3:0]S00_AXI_rid; + output S00_AXI_rlast; + input S00_AXI_rready; + output [1:0]S00_AXI_rresp; + output S00_AXI_rvalid; + input [127:0]S00_AXI_wdata; + input S00_AXI_wlast; + output S00_AXI_wready; + input [15:0]S00_AXI_wstrb; + input S00_AXI_wvalid; + input S01_ACLK; + input S01_ARESETN; + input [31:0]S01_AXI_araddr; + input [1:0]S01_AXI_arburst; + input [3:0]S01_AXI_arcache; + input [0:0]S01_AXI_arid; + input [7:0]S01_AXI_arlen; + input [0:0]S01_AXI_arlock; + input [2:0]S01_AXI_arprot; + input [3:0]S01_AXI_arqos; + output S01_AXI_arready; + input [2:0]S01_AXI_arsize; + input S01_AXI_arvalid; + input [31:0]S01_AXI_awaddr; + input [1:0]S01_AXI_awburst; + input [3:0]S01_AXI_awcache; + input [0:0]S01_AXI_awid; + input [7:0]S01_AXI_awlen; + input [0:0]S01_AXI_awlock; + input [2:0]S01_AXI_awprot; + input [3:0]S01_AXI_awqos; + output S01_AXI_awready; + input [2:0]S01_AXI_awsize; + input S01_AXI_awvalid; + output [0:0]S01_AXI_bid; + input S01_AXI_bready; + output [1:0]S01_AXI_bresp; + output S01_AXI_bvalid; + output [31:0]S01_AXI_rdata; + output [0:0]S01_AXI_rid; + output S01_AXI_rlast; + input S01_AXI_rready; + output [1:0]S01_AXI_rresp; + output S01_AXI_rvalid; + input [31:0]S01_AXI_wdata; + input S01_AXI_wlast; + output S01_AXI_wready; + input [3:0]S01_AXI_wstrb; + input S01_AXI_wvalid; + + wire M00_ACLK_1; + wire M00_ARESETN_1; + wire S00_ACLK_1; + wire S00_ARESETN_1; + wire S01_ACLK_1; + wire S01_ARESETN_1; + wire [31:0]S01_AXI_1_ARADDR; + wire [1:0]S01_AXI_1_ARBURST; + wire [3:0]S01_AXI_1_ARCACHE; + wire [0:0]S01_AXI_1_ARID; + wire [7:0]S01_AXI_1_ARLEN; + wire [0:0]S01_AXI_1_ARLOCK; + wire [2:0]S01_AXI_1_ARPROT; + wire [3:0]S01_AXI_1_ARQOS; + wire S01_AXI_1_ARREADY; + wire [2:0]S01_AXI_1_ARSIZE; + wire S01_AXI_1_ARVALID; + wire [31:0]S01_AXI_1_AWADDR; + wire [1:0]S01_AXI_1_AWBURST; + wire [3:0]S01_AXI_1_AWCACHE; + wire [0:0]S01_AXI_1_AWID; + wire [7:0]S01_AXI_1_AWLEN; + wire [0:0]S01_AXI_1_AWLOCK; + wire [2:0]S01_AXI_1_AWPROT; + wire [3:0]S01_AXI_1_AWQOS; + wire S01_AXI_1_AWREADY; + wire [2:0]S01_AXI_1_AWSIZE; + wire S01_AXI_1_AWVALID; + wire [0:0]S01_AXI_1_BID; + wire S01_AXI_1_BREADY; + wire [1:0]S01_AXI_1_BRESP; + wire S01_AXI_1_BVALID; + wire [31:0]S01_AXI_1_RDATA; + wire [0:0]S01_AXI_1_RID; + wire S01_AXI_1_RLAST; + wire S01_AXI_1_RREADY; + wire [1:0]S01_AXI_1_RRESP; + wire S01_AXI_1_RVALID; + wire [31:0]S01_AXI_1_WDATA; + wire S01_AXI_1_WLAST; + wire S01_AXI_1_WREADY; + wire [3:0]S01_AXI_1_WSTRB; + wire S01_AXI_1_WVALID; + wire axi_interconnect_0_ACLK_net; + wire axi_interconnect_0_ARESETN_net; + wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR; + wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST; + wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE; + wire [3:0]axi_interconnect_0_to_s00_couplers_ARID; + wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN; + wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK; + wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT; + wire axi_interconnect_0_to_s00_couplers_ARREADY; + wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE; + wire axi_interconnect_0_to_s00_couplers_ARVALID; + wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR; + wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST; + wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE; + wire [3:0]axi_interconnect_0_to_s00_couplers_AWID; + wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN; + wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK; + wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT; + wire axi_interconnect_0_to_s00_couplers_AWREADY; + wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE; + wire axi_interconnect_0_to_s00_couplers_AWVALID; + wire [3:0]axi_interconnect_0_to_s00_couplers_BID; + wire axi_interconnect_0_to_s00_couplers_BREADY; + wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP; + wire axi_interconnect_0_to_s00_couplers_BVALID; + wire [127:0]axi_interconnect_0_to_s00_couplers_RDATA; + wire [3:0]axi_interconnect_0_to_s00_couplers_RID; + wire axi_interconnect_0_to_s00_couplers_RLAST; + wire axi_interconnect_0_to_s00_couplers_RREADY; + wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP; + wire axi_interconnect_0_to_s00_couplers_RVALID; + wire [127:0]axi_interconnect_0_to_s00_couplers_WDATA; + wire axi_interconnect_0_to_s00_couplers_WLAST; + wire axi_interconnect_0_to_s00_couplers_WREADY; + wire [15:0]axi_interconnect_0_to_s00_couplers_WSTRB; + wire axi_interconnect_0_to_s00_couplers_WVALID; + wire [32:0]m00_couplers_to_axi_interconnect_0_ARADDR; + wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST; + wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE; + wire [0:0]m00_couplers_to_axi_interconnect_0_ARID; + wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN; + wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK; + wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT; + wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS; + wire m00_couplers_to_axi_interconnect_0_ARREADY; + wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE; + wire m00_couplers_to_axi_interconnect_0_ARVALID; + wire [32:0]m00_couplers_to_axi_interconnect_0_AWADDR; + wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST; + wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE; + wire [0:0]m00_couplers_to_axi_interconnect_0_AWID; + wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN; + wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK; + wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT; + wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS; + wire m00_couplers_to_axi_interconnect_0_AWREADY; + wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE; + wire m00_couplers_to_axi_interconnect_0_AWVALID; + wire [0:0]m00_couplers_to_axi_interconnect_0_BID; + wire m00_couplers_to_axi_interconnect_0_BREADY; + wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP; + wire m00_couplers_to_axi_interconnect_0_BVALID; + wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA; + wire [0:0]m00_couplers_to_axi_interconnect_0_RID; + wire m00_couplers_to_axi_interconnect_0_RLAST; + wire m00_couplers_to_axi_interconnect_0_RREADY; + wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP; + wire m00_couplers_to_axi_interconnect_0_RVALID; + wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA; + wire m00_couplers_to_axi_interconnect_0_WLAST; + wire m00_couplers_to_axi_interconnect_0_WREADY; + wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB; + wire m00_couplers_to_axi_interconnect_0_WVALID; + wire [63:0]s00_couplers_to_xbar_ARADDR; + wire [1:0]s00_couplers_to_xbar_ARBURST; + wire [3:0]s00_couplers_to_xbar_ARCACHE; + wire [7:0]s00_couplers_to_xbar_ARLEN; + wire [0:0]s00_couplers_to_xbar_ARLOCK; + wire [2:0]s00_couplers_to_xbar_ARPROT; + wire [3:0]s00_couplers_to_xbar_ARQOS; + wire [0:0]s00_couplers_to_xbar_ARREADY; + wire [2:0]s00_couplers_to_xbar_ARSIZE; + wire s00_couplers_to_xbar_ARVALID; + wire [63:0]s00_couplers_to_xbar_AWADDR; + wire [1:0]s00_couplers_to_xbar_AWBURST; + wire [3:0]s00_couplers_to_xbar_AWCACHE; + wire [7:0]s00_couplers_to_xbar_AWLEN; + wire [0:0]s00_couplers_to_xbar_AWLOCK; + wire [2:0]s00_couplers_to_xbar_AWPROT; + wire [3:0]s00_couplers_to_xbar_AWQOS; + wire [0:0]s00_couplers_to_xbar_AWREADY; + wire [2:0]s00_couplers_to_xbar_AWSIZE; + wire s00_couplers_to_xbar_AWVALID; + wire s00_couplers_to_xbar_BREADY; + wire [1:0]s00_couplers_to_xbar_BRESP; + wire [0:0]s00_couplers_to_xbar_BVALID; + wire [511:0]s00_couplers_to_xbar_RDATA; + wire [0:0]s00_couplers_to_xbar_RLAST; + wire s00_couplers_to_xbar_RREADY; + wire [1:0]s00_couplers_to_xbar_RRESP; + wire [0:0]s00_couplers_to_xbar_RVALID; + wire [511:0]s00_couplers_to_xbar_WDATA; + wire s00_couplers_to_xbar_WLAST; + wire [0:0]s00_couplers_to_xbar_WREADY; + wire [63:0]s00_couplers_to_xbar_WSTRB; + wire s00_couplers_to_xbar_WVALID; + wire [31:0]s01_couplers_to_xbar_ARADDR; + wire [1:0]s01_couplers_to_xbar_ARBURST; + wire [3:0]s01_couplers_to_xbar_ARCACHE; + wire [7:0]s01_couplers_to_xbar_ARLEN; + wire [0:0]s01_couplers_to_xbar_ARLOCK; + wire [2:0]s01_couplers_to_xbar_ARPROT; + wire [3:0]s01_couplers_to_xbar_ARQOS; + wire [1:1]s01_couplers_to_xbar_ARREADY; + wire [2:0]s01_couplers_to_xbar_ARSIZE; + wire s01_couplers_to_xbar_ARVALID; + wire [31:0]s01_couplers_to_xbar_AWADDR; + wire [1:0]s01_couplers_to_xbar_AWBURST; + wire [3:0]s01_couplers_to_xbar_AWCACHE; + wire [7:0]s01_couplers_to_xbar_AWLEN; + wire [0:0]s01_couplers_to_xbar_AWLOCK; + wire [2:0]s01_couplers_to_xbar_AWPROT; + wire [3:0]s01_couplers_to_xbar_AWQOS; + wire [1:1]s01_couplers_to_xbar_AWREADY; + wire [2:0]s01_couplers_to_xbar_AWSIZE; + wire s01_couplers_to_xbar_AWVALID; + wire s01_couplers_to_xbar_BREADY; + wire [3:2]s01_couplers_to_xbar_BRESP; + wire [1:1]s01_couplers_to_xbar_BVALID; + wire [1023:512]s01_couplers_to_xbar_RDATA; + wire [1:1]s01_couplers_to_xbar_RLAST; + wire s01_couplers_to_xbar_RREADY; + wire [3:2]s01_couplers_to_xbar_RRESP; + wire [1:1]s01_couplers_to_xbar_RVALID; + wire [511:0]s01_couplers_to_xbar_WDATA; + wire s01_couplers_to_xbar_WLAST; + wire [1:1]s01_couplers_to_xbar_WREADY; + wire [63:0]s01_couplers_to_xbar_WSTRB; + wire s01_couplers_to_xbar_WVALID; + wire [31:0]s01_mmu_M_AXI_ARADDR; + wire [1:0]s01_mmu_M_AXI_ARBURST; + wire [3:0]s01_mmu_M_AXI_ARCACHE; + wire [0:0]s01_mmu_M_AXI_ARID; + wire [7:0]s01_mmu_M_AXI_ARLEN; + wire [0:0]s01_mmu_M_AXI_ARLOCK; + wire [2:0]s01_mmu_M_AXI_ARPROT; + wire [3:0]s01_mmu_M_AXI_ARQOS; + wire s01_mmu_M_AXI_ARREADY; + wire [2:0]s01_mmu_M_AXI_ARSIZE; + wire s01_mmu_M_AXI_ARVALID; + wire [31:0]s01_mmu_M_AXI_AWADDR; + wire [1:0]s01_mmu_M_AXI_AWBURST; + wire [3:0]s01_mmu_M_AXI_AWCACHE; + wire [0:0]s01_mmu_M_AXI_AWID; + wire [7:0]s01_mmu_M_AXI_AWLEN; + wire [0:0]s01_mmu_M_AXI_AWLOCK; + wire [2:0]s01_mmu_M_AXI_AWPROT; + wire [3:0]s01_mmu_M_AXI_AWQOS; + wire s01_mmu_M_AXI_AWREADY; + wire [2:0]s01_mmu_M_AXI_AWSIZE; + wire s01_mmu_M_AXI_AWVALID; + wire [0:0]s01_mmu_M_AXI_BID; + wire s01_mmu_M_AXI_BREADY; + wire [1:0]s01_mmu_M_AXI_BRESP; + wire s01_mmu_M_AXI_BVALID; + wire [31:0]s01_mmu_M_AXI_RDATA; + wire [0:0]s01_mmu_M_AXI_RID; + wire s01_mmu_M_AXI_RLAST; + wire s01_mmu_M_AXI_RREADY; + wire [1:0]s01_mmu_M_AXI_RRESP; + wire s01_mmu_M_AXI_RVALID; + wire [31:0]s01_mmu_M_AXI_WDATA; + wire s01_mmu_M_AXI_WLAST; + wire s01_mmu_M_AXI_WREADY; + wire [3:0]s01_mmu_M_AXI_WSTRB; + wire s01_mmu_M_AXI_WVALID; + wire [63:0]xbar_to_m00_couplers_ARADDR; + wire [1:0]xbar_to_m00_couplers_ARBURST; + wire [3:0]xbar_to_m00_couplers_ARCACHE; + wire [0:0]xbar_to_m00_couplers_ARID; + wire [7:0]xbar_to_m00_couplers_ARLEN; + wire [0:0]xbar_to_m00_couplers_ARLOCK; + wire [2:0]xbar_to_m00_couplers_ARPROT; + wire [3:0]xbar_to_m00_couplers_ARQOS; + wire xbar_to_m00_couplers_ARREADY; + wire [3:0]xbar_to_m00_couplers_ARREGION; + wire [2:0]xbar_to_m00_couplers_ARSIZE; + wire [0:0]xbar_to_m00_couplers_ARVALID; + wire [63:0]xbar_to_m00_couplers_AWADDR; + wire [1:0]xbar_to_m00_couplers_AWBURST; + wire [3:0]xbar_to_m00_couplers_AWCACHE; + wire [0:0]xbar_to_m00_couplers_AWID; + wire [7:0]xbar_to_m00_couplers_AWLEN; + wire [0:0]xbar_to_m00_couplers_AWLOCK; + wire [2:0]xbar_to_m00_couplers_AWPROT; + wire [3:0]xbar_to_m00_couplers_AWQOS; + wire xbar_to_m00_couplers_AWREADY; + wire [3:0]xbar_to_m00_couplers_AWREGION; + wire [2:0]xbar_to_m00_couplers_AWSIZE; + wire [0:0]xbar_to_m00_couplers_AWVALID; + wire [0:0]xbar_to_m00_couplers_BID; + wire [0:0]xbar_to_m00_couplers_BREADY; + wire [1:0]xbar_to_m00_couplers_BRESP; + wire xbar_to_m00_couplers_BVALID; + wire [511:0]xbar_to_m00_couplers_RDATA; + wire [0:0]xbar_to_m00_couplers_RID; + wire xbar_to_m00_couplers_RLAST; + wire [0:0]xbar_to_m00_couplers_RREADY; + wire [1:0]xbar_to_m00_couplers_RRESP; + wire xbar_to_m00_couplers_RVALID; + wire [511:0]xbar_to_m00_couplers_WDATA; + wire [0:0]xbar_to_m00_couplers_WLAST; + wire xbar_to_m00_couplers_WREADY; + wire [63:0]xbar_to_m00_couplers_WSTRB; + wire [0:0]xbar_to_m00_couplers_WVALID; + + assign M00_ACLK_1 = M00_ACLK; + assign M00_ARESETN_1 = M00_ARESETN; + assign M00_AXI_araddr[32:0] = m00_couplers_to_axi_interconnect_0_ARADDR; + assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST; + assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE; + assign M00_AXI_arid[0] = m00_couplers_to_axi_interconnect_0_ARID; + assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN; + assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK; + assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT; + assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS; + assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE; + assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID; + assign M00_AXI_awaddr[32:0] = m00_couplers_to_axi_interconnect_0_AWADDR; + assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST; + assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE; + assign M00_AXI_awid[0] = m00_couplers_to_axi_interconnect_0_AWID; + assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN; + assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK; + assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT; + assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS; + assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE; + assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID; + assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY; + assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY; + assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA; + assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST; + assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB; + assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID; + assign S00_ACLK_1 = S00_ACLK; + assign S00_ARESETN_1 = S00_ARESETN; + assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY; + assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY; + assign S00_AXI_bid[3:0] = axi_interconnect_0_to_s00_couplers_BID; + assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP; + assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID; + assign S00_AXI_rdata[127:0] = axi_interconnect_0_to_s00_couplers_RDATA; + assign S00_AXI_rid[3:0] = axi_interconnect_0_to_s00_couplers_RID; + assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST; + assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP; + assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID; + assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY; + assign S01_ACLK_1 = S01_ACLK; + assign S01_ARESETN_1 = S01_ARESETN; + assign S01_AXI_1_ARADDR = S01_AXI_araddr[31:0]; + assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0]; + assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0]; + assign S01_AXI_1_ARID = S01_AXI_arid[0]; + assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0]; + assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0]; + assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0]; + assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0]; + assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0]; + assign S01_AXI_1_ARVALID = S01_AXI_arvalid; + assign S01_AXI_1_AWADDR = S01_AXI_awaddr[31:0]; + assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0]; + assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0]; + assign S01_AXI_1_AWID = S01_AXI_awid[0]; + assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0]; + assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0]; + assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0]; + assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0]; + assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0]; + assign S01_AXI_1_AWVALID = S01_AXI_awvalid; + assign S01_AXI_1_BREADY = S01_AXI_bready; + assign S01_AXI_1_RREADY = S01_AXI_rready; + assign S01_AXI_1_WDATA = S01_AXI_wdata[31:0]; + assign S01_AXI_1_WLAST = S01_AXI_wlast; + assign S01_AXI_1_WSTRB = S01_AXI_wstrb[3:0]; + assign S01_AXI_1_WVALID = S01_AXI_wvalid; + assign S01_AXI_arready = S01_AXI_1_ARREADY; + assign S01_AXI_awready = S01_AXI_1_AWREADY; + assign S01_AXI_bid[0] = S01_AXI_1_BID; + assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP; + assign S01_AXI_bvalid = S01_AXI_1_BVALID; + assign S01_AXI_rdata[31:0] = S01_AXI_1_RDATA; + assign S01_AXI_rid[0] = S01_AXI_1_RID; + assign S01_AXI_rlast = S01_AXI_1_RLAST; + assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP; + assign S01_AXI_rvalid = S01_AXI_1_RVALID; + assign S01_AXI_wready = S01_AXI_1_WREADY; + assign axi_interconnect_0_ACLK_net = ACLK; + assign axi_interconnect_0_ARESETN_net = ARESETN; + assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0]; + assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0]; + assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0]; + assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[3:0]; + assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0]; + assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0]; + assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0]; + assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0]; + assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid; + assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0]; + assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0]; + assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0]; + assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[3:0]; + assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0]; + assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0]; + assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0]; + assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0]; + assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid; + assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready; + assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready; + assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[127:0]; + assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast; + assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[15:0]; + assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid; + assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready; + assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready; + assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[0]; + assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0]; + assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid; + assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0]; + assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[0]; + assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast; + assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0]; + assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid; + assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready; + m00_couplers_imp_1FLA7NN m00_couplers + (.M_ACLK(M00_ACLK_1), + .M_ARESETN(M00_ARESETN_1), + .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR), + .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST), + .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE), + .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID), + .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN), + .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK), + .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT), + .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS), + .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY), + .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE), + .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID), + .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR), + .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST), + .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE), + .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID), + .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN), + .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK), + .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT), + .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS), + .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY), + .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE), + .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID), + .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID), + .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY), + .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP), + .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID), + .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA), + .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID), + .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST), + .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY), + .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP), + .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID), + .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA), + .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST), + .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY), + .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB), + .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID), + .S_ACLK(axi_interconnect_0_ACLK_net), + .S_ARESETN(axi_interconnect_0_ARESETN_net), + .S_AXI_araddr(xbar_to_m00_couplers_ARADDR), + .S_AXI_arburst(xbar_to_m00_couplers_ARBURST), + .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE), + .S_AXI_arid(xbar_to_m00_couplers_ARID), + .S_AXI_arlen(xbar_to_m00_couplers_ARLEN), + .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK), + .S_AXI_arprot(xbar_to_m00_couplers_ARPROT), + .S_AXI_arqos(xbar_to_m00_couplers_ARQOS), + .S_AXI_arready(xbar_to_m00_couplers_ARREADY), + .S_AXI_arregion(xbar_to_m00_couplers_ARREGION), + .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE), + .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID), + .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR), + .S_AXI_awburst(xbar_to_m00_couplers_AWBURST), + .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE), + .S_AXI_awid(xbar_to_m00_couplers_AWID), + .S_AXI_awlen(xbar_to_m00_couplers_AWLEN), + .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK), + .S_AXI_awprot(xbar_to_m00_couplers_AWPROT), + .S_AXI_awqos(xbar_to_m00_couplers_AWQOS), + .S_AXI_awready(xbar_to_m00_couplers_AWREADY), + .S_AXI_awregion(xbar_to_m00_couplers_AWREGION), + .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE), + .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID), + .S_AXI_bid(xbar_to_m00_couplers_BID), + .S_AXI_bready(xbar_to_m00_couplers_BREADY), + .S_AXI_bresp(xbar_to_m00_couplers_BRESP), + .S_AXI_bvalid(xbar_to_m00_couplers_BVALID), + .S_AXI_rdata(xbar_to_m00_couplers_RDATA), + .S_AXI_rid(xbar_to_m00_couplers_RID), + .S_AXI_rlast(xbar_to_m00_couplers_RLAST), + .S_AXI_rready(xbar_to_m00_couplers_RREADY), + .S_AXI_rresp(xbar_to_m00_couplers_RRESP), + .S_AXI_rvalid(xbar_to_m00_couplers_RVALID), + .S_AXI_wdata(xbar_to_m00_couplers_WDATA), + .S_AXI_wlast(xbar_to_m00_couplers_WLAST), + .S_AXI_wready(xbar_to_m00_couplers_WREADY), + .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB), + .S_AXI_wvalid(xbar_to_m00_couplers_WVALID)); + s00_couplers_imp_HZCGLD s00_couplers + (.M_ACLK(axi_interconnect_0_ACLK_net), + .M_ARESETN(axi_interconnect_0_ARESETN_net), + .M_AXI_araddr(s00_couplers_to_xbar_ARADDR), + .M_AXI_arburst(s00_couplers_to_xbar_ARBURST), + .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE), + .M_AXI_arlen(s00_couplers_to_xbar_ARLEN), + .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK), + .M_AXI_arprot(s00_couplers_to_xbar_ARPROT), + .M_AXI_arqos(s00_couplers_to_xbar_ARQOS), + .M_AXI_arready(s00_couplers_to_xbar_ARREADY), + .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE), + .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID), + .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR), + .M_AXI_awburst(s00_couplers_to_xbar_AWBURST), + .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE), + .M_AXI_awlen(s00_couplers_to_xbar_AWLEN), + .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK), + .M_AXI_awprot(s00_couplers_to_xbar_AWPROT), + .M_AXI_awqos(s00_couplers_to_xbar_AWQOS), + .M_AXI_awready(s00_couplers_to_xbar_AWREADY), + .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE), + .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID), + .M_AXI_bready(s00_couplers_to_xbar_BREADY), + .M_AXI_bresp(s00_couplers_to_xbar_BRESP), + .M_AXI_bvalid(s00_couplers_to_xbar_BVALID), + .M_AXI_rdata(s00_couplers_to_xbar_RDATA), + .M_AXI_rlast(s00_couplers_to_xbar_RLAST), + .M_AXI_rready(s00_couplers_to_xbar_RREADY), + .M_AXI_rresp(s00_couplers_to_xbar_RRESP), + .M_AXI_rvalid(s00_couplers_to_xbar_RVALID), + .M_AXI_wdata(s00_couplers_to_xbar_WDATA), + .M_AXI_wlast(s00_couplers_to_xbar_WLAST), + .M_AXI_wready(s00_couplers_to_xbar_WREADY), + .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB), + .M_AXI_wvalid(s00_couplers_to_xbar_WVALID), + .S_ACLK(S00_ACLK_1), + .S_ARESETN(S00_ARESETN_1), + .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR), + .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST), + .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE), + .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID), + .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN), + .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK), + .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT), + .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY), + .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE), + .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID), + .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR), + .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST), + .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE), + .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID), + .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN), + .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK), + .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT), + .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY), + .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE), + .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID), + .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID), + .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY), + .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP), + .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID), + .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA), + .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID), + .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST), + .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY), + .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP), + .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID), + .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA), + .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST), + .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY), + .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB), + .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID)); + s01_couplers_imp_1CQ4OV4 s01_couplers + (.M_ACLK(axi_interconnect_0_ACLK_net), + .M_ARESETN(axi_interconnect_0_ARESETN_net), + .M_AXI_araddr(s01_couplers_to_xbar_ARADDR), + .M_AXI_arburst(s01_couplers_to_xbar_ARBURST), + .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE), + .M_AXI_arlen(s01_couplers_to_xbar_ARLEN), + .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK), + .M_AXI_arprot(s01_couplers_to_xbar_ARPROT), + .M_AXI_arqos(s01_couplers_to_xbar_ARQOS), + .M_AXI_arready(s01_couplers_to_xbar_ARREADY), + .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE), + .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID), + .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR), + .M_AXI_awburst(s01_couplers_to_xbar_AWBURST), + .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE), + .M_AXI_awlen(s01_couplers_to_xbar_AWLEN), + .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK), + .M_AXI_awprot(s01_couplers_to_xbar_AWPROT), + .M_AXI_awqos(s01_couplers_to_xbar_AWQOS), + .M_AXI_awready(s01_couplers_to_xbar_AWREADY), + .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE), + .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID), + .M_AXI_bready(s01_couplers_to_xbar_BREADY), + .M_AXI_bresp(s01_couplers_to_xbar_BRESP), + .M_AXI_bvalid(s01_couplers_to_xbar_BVALID), + .M_AXI_rdata(s01_couplers_to_xbar_RDATA), + .M_AXI_rlast(s01_couplers_to_xbar_RLAST), + .M_AXI_rready(s01_couplers_to_xbar_RREADY), + .M_AXI_rresp(s01_couplers_to_xbar_RRESP), + .M_AXI_rvalid(s01_couplers_to_xbar_RVALID), + .M_AXI_wdata(s01_couplers_to_xbar_WDATA), + .M_AXI_wlast(s01_couplers_to_xbar_WLAST), + .M_AXI_wready(s01_couplers_to_xbar_WREADY), + .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB), + .M_AXI_wvalid(s01_couplers_to_xbar_WVALID), + .S_ACLK(S01_ACLK_1), + .S_ARESETN(S01_ARESETN_1), + .S_AXI_araddr(s01_mmu_M_AXI_ARADDR), + .S_AXI_arburst(s01_mmu_M_AXI_ARBURST), + .S_AXI_arcache(s01_mmu_M_AXI_ARCACHE), + .S_AXI_arid(s01_mmu_M_AXI_ARID), + .S_AXI_arlen(s01_mmu_M_AXI_ARLEN), + .S_AXI_arlock(s01_mmu_M_AXI_ARLOCK), + .S_AXI_arprot(s01_mmu_M_AXI_ARPROT), + .S_AXI_arqos(s01_mmu_M_AXI_ARQOS), + .S_AXI_arready(s01_mmu_M_AXI_ARREADY), + .S_AXI_arsize(s01_mmu_M_AXI_ARSIZE), + .S_AXI_arvalid(s01_mmu_M_AXI_ARVALID), + .S_AXI_awaddr(s01_mmu_M_AXI_AWADDR), + .S_AXI_awburst(s01_mmu_M_AXI_AWBURST), + .S_AXI_awcache(s01_mmu_M_AXI_AWCACHE), + .S_AXI_awid(s01_mmu_M_AXI_AWID), + .S_AXI_awlen(s01_mmu_M_AXI_AWLEN), + .S_AXI_awlock(s01_mmu_M_AXI_AWLOCK), + .S_AXI_awprot(s01_mmu_M_AXI_AWPROT), + .S_AXI_awqos(s01_mmu_M_AXI_AWQOS), + .S_AXI_awready(s01_mmu_M_AXI_AWREADY), + .S_AXI_awsize(s01_mmu_M_AXI_AWSIZE), + .S_AXI_awvalid(s01_mmu_M_AXI_AWVALID), + .S_AXI_bid(s01_mmu_M_AXI_BID), + .S_AXI_bready(s01_mmu_M_AXI_BREADY), + .S_AXI_bresp(s01_mmu_M_AXI_BRESP), + .S_AXI_bvalid(s01_mmu_M_AXI_BVALID), + .S_AXI_rdata(s01_mmu_M_AXI_RDATA), + .S_AXI_rid(s01_mmu_M_AXI_RID), + .S_AXI_rlast(s01_mmu_M_AXI_RLAST), + .S_AXI_rready(s01_mmu_M_AXI_RREADY), + .S_AXI_rresp(s01_mmu_M_AXI_RRESP), + .S_AXI_rvalid(s01_mmu_M_AXI_RVALID), + .S_AXI_wdata(s01_mmu_M_AXI_WDATA), + .S_AXI_wlast(s01_mmu_M_AXI_WLAST), + .S_AXI_wready(s01_mmu_M_AXI_WREADY), + .S_AXI_wstrb(s01_mmu_M_AXI_WSTRB), + .S_AXI_wvalid(s01_mmu_M_AXI_WVALID)); + pcie_ddr_s01_mmu_1 s01_mmu + (.aclk(S01_ACLK_1), + .aresetn(S01_ARESETN_1), + .m_axi_araddr(s01_mmu_M_AXI_ARADDR), + .m_axi_arburst(s01_mmu_M_AXI_ARBURST), + .m_axi_arcache(s01_mmu_M_AXI_ARCACHE), + .m_axi_arid(s01_mmu_M_AXI_ARID), + .m_axi_arlen(s01_mmu_M_AXI_ARLEN), + .m_axi_arlock(s01_mmu_M_AXI_ARLOCK), + .m_axi_arprot(s01_mmu_M_AXI_ARPROT), + .m_axi_arqos(s01_mmu_M_AXI_ARQOS), + .m_axi_arready(s01_mmu_M_AXI_ARREADY), + .m_axi_arsize(s01_mmu_M_AXI_ARSIZE), + .m_axi_arvalid(s01_mmu_M_AXI_ARVALID), + .m_axi_awaddr(s01_mmu_M_AXI_AWADDR), + .m_axi_awburst(s01_mmu_M_AXI_AWBURST), + .m_axi_awcache(s01_mmu_M_AXI_AWCACHE), + .m_axi_awid(s01_mmu_M_AXI_AWID), + .m_axi_awlen(s01_mmu_M_AXI_AWLEN), + .m_axi_awlock(s01_mmu_M_AXI_AWLOCK), + .m_axi_awprot(s01_mmu_M_AXI_AWPROT), + .m_axi_awqos(s01_mmu_M_AXI_AWQOS), + .m_axi_awready(s01_mmu_M_AXI_AWREADY), + .m_axi_awsize(s01_mmu_M_AXI_AWSIZE), + .m_axi_awvalid(s01_mmu_M_AXI_AWVALID), + .m_axi_bid(s01_mmu_M_AXI_BID), + .m_axi_bready(s01_mmu_M_AXI_BREADY), + .m_axi_bresp(s01_mmu_M_AXI_BRESP), + .m_axi_bvalid(s01_mmu_M_AXI_BVALID), + .m_axi_rdata(s01_mmu_M_AXI_RDATA), + .m_axi_rid(s01_mmu_M_AXI_RID), + .m_axi_rlast(s01_mmu_M_AXI_RLAST), + .m_axi_rready(s01_mmu_M_AXI_RREADY), + .m_axi_rresp(s01_mmu_M_AXI_RRESP), + .m_axi_rvalid(s01_mmu_M_AXI_RVALID), + .m_axi_wdata(s01_mmu_M_AXI_WDATA), + .m_axi_wlast(s01_mmu_M_AXI_WLAST), + .m_axi_wready(s01_mmu_M_AXI_WREADY), + .m_axi_wstrb(s01_mmu_M_AXI_WSTRB), + .m_axi_wvalid(s01_mmu_M_AXI_WVALID), + .s_axi_araddr(S01_AXI_1_ARADDR), + .s_axi_arburst(S01_AXI_1_ARBURST), + .s_axi_arcache(S01_AXI_1_ARCACHE), + .s_axi_arid(S01_AXI_1_ARID), + .s_axi_arlen(S01_AXI_1_ARLEN), + .s_axi_arlock(S01_AXI_1_ARLOCK), + .s_axi_arprot(S01_AXI_1_ARPROT), + .s_axi_arqos(S01_AXI_1_ARQOS), + .s_axi_arready(S01_AXI_1_ARREADY), + .s_axi_arsize(S01_AXI_1_ARSIZE), + .s_axi_arvalid(S01_AXI_1_ARVALID), + .s_axi_awaddr(S01_AXI_1_AWADDR), + .s_axi_awburst(S01_AXI_1_AWBURST), + .s_axi_awcache(S01_AXI_1_AWCACHE), + .s_axi_awid(S01_AXI_1_AWID), + .s_axi_awlen(S01_AXI_1_AWLEN), + .s_axi_awlock(S01_AXI_1_AWLOCK), + .s_axi_awprot(S01_AXI_1_AWPROT), + .s_axi_awqos(S01_AXI_1_AWQOS), + .s_axi_awready(S01_AXI_1_AWREADY), + .s_axi_awsize(S01_AXI_1_AWSIZE), + .s_axi_awvalid(S01_AXI_1_AWVALID), + .s_axi_bid(S01_AXI_1_BID), + .s_axi_bready(S01_AXI_1_BREADY), + .s_axi_bresp(S01_AXI_1_BRESP), + .s_axi_bvalid(S01_AXI_1_BVALID), + .s_axi_rdata(S01_AXI_1_RDATA), + .s_axi_rid(S01_AXI_1_RID), + .s_axi_rlast(S01_AXI_1_RLAST), + .s_axi_rready(S01_AXI_1_RREADY), + .s_axi_rresp(S01_AXI_1_RRESP), + .s_axi_rvalid(S01_AXI_1_RVALID), + .s_axi_wdata(S01_AXI_1_WDATA), + .s_axi_wlast(S01_AXI_1_WLAST), + .s_axi_wready(S01_AXI_1_WREADY), + .s_axi_wstrb(S01_AXI_1_WSTRB), + .s_axi_wvalid(S01_AXI_1_WVALID)); + pcie_ddr_xbar_1 xbar + (.aclk(axi_interconnect_0_ACLK_net), + .aresetn(axi_interconnect_0_ARESETN_net), + .m_axi_araddr(xbar_to_m00_couplers_ARADDR), + .m_axi_arburst(xbar_to_m00_couplers_ARBURST), + .m_axi_arcache(xbar_to_m00_couplers_ARCACHE), + .m_axi_arid(xbar_to_m00_couplers_ARID), + .m_axi_arlen(xbar_to_m00_couplers_ARLEN), + .m_axi_arlock(xbar_to_m00_couplers_ARLOCK), + .m_axi_arprot(xbar_to_m00_couplers_ARPROT), + .m_axi_arqos(xbar_to_m00_couplers_ARQOS), + .m_axi_arready(xbar_to_m00_couplers_ARREADY), + .m_axi_arregion(xbar_to_m00_couplers_ARREGION), + .m_axi_arsize(xbar_to_m00_couplers_ARSIZE), + .m_axi_arvalid(xbar_to_m00_couplers_ARVALID), + .m_axi_awaddr(xbar_to_m00_couplers_AWADDR), + .m_axi_awburst(xbar_to_m00_couplers_AWBURST), + .m_axi_awcache(xbar_to_m00_couplers_AWCACHE), + .m_axi_awid(xbar_to_m00_couplers_AWID), + .m_axi_awlen(xbar_to_m00_couplers_AWLEN), + .m_axi_awlock(xbar_to_m00_couplers_AWLOCK), + .m_axi_awprot(xbar_to_m00_couplers_AWPROT), + .m_axi_awqos(xbar_to_m00_couplers_AWQOS), + .m_axi_awready(xbar_to_m00_couplers_AWREADY), + .m_axi_awregion(xbar_to_m00_couplers_AWREGION), + .m_axi_awsize(xbar_to_m00_couplers_AWSIZE), + .m_axi_awvalid(xbar_to_m00_couplers_AWVALID), + .m_axi_bid(xbar_to_m00_couplers_BID), + .m_axi_bready(xbar_to_m00_couplers_BREADY), + .m_axi_bresp(xbar_to_m00_couplers_BRESP), + .m_axi_bvalid(xbar_to_m00_couplers_BVALID), + .m_axi_rdata(xbar_to_m00_couplers_RDATA), + .m_axi_rid(xbar_to_m00_couplers_RID), + .m_axi_rlast(xbar_to_m00_couplers_RLAST), + .m_axi_rready(xbar_to_m00_couplers_RREADY), + .m_axi_rresp(xbar_to_m00_couplers_RRESP), + .m_axi_rvalid(xbar_to_m00_couplers_RVALID), + .m_axi_wdata(xbar_to_m00_couplers_WDATA), + .m_axi_wlast(xbar_to_m00_couplers_WLAST), + .m_axi_wready(xbar_to_m00_couplers_WREADY), + .m_axi_wstrb(xbar_to_m00_couplers_WSTRB), + .m_axi_wvalid(xbar_to_m00_couplers_WVALID), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}), + .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}), + .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}), + .s_axi_arid({1'b0,1'b0}), + .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}), + .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}), + .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}), + .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}), + .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}), + .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}), + .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}), + .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}), + .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}), + .s_axi_awid({1'b0,1'b0}), + .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}), + .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}), + .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}), + .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}), + .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}), + .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}), + .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}), + .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}), + .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}), + .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}), + .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}), + .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}), + .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}), + .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}), + .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}), + .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}), + .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}), + .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}), + .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}), + .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID})); +endmodule + +module s00_couplers_imp_HZCGLD + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [63:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [7:0]M_AXI_arlen; + output [0:0]M_AXI_arlock; + output [2:0]M_AXI_arprot; + output [3:0]M_AXI_arqos; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [63:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [7:0]M_AXI_awlen; + output [0:0]M_AXI_awlock; + output [2:0]M_AXI_awprot; + output [3:0]M_AXI_awqos; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [511:0]M_AXI_rdata; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [511:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [63:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [63:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [3:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + output S_AXI_arready; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [63:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [3:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + output S_AXI_awready; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [3:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [127:0]S_AXI_rdata; + output [3:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [127:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [15:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire M_ACLK_1; + wire M_ARESETN_1; + wire S_ACLK_1; + wire S_ARESETN_1; + wire [63:0]auto_cc_to_s00_couplers_ARADDR; + wire [1:0]auto_cc_to_s00_couplers_ARBURST; + wire [3:0]auto_cc_to_s00_couplers_ARCACHE; + wire [7:0]auto_cc_to_s00_couplers_ARLEN; + wire [0:0]auto_cc_to_s00_couplers_ARLOCK; + wire [2:0]auto_cc_to_s00_couplers_ARPROT; + wire [3:0]auto_cc_to_s00_couplers_ARQOS; + wire auto_cc_to_s00_couplers_ARREADY; + wire [2:0]auto_cc_to_s00_couplers_ARSIZE; + wire auto_cc_to_s00_couplers_ARVALID; + wire [63:0]auto_cc_to_s00_couplers_AWADDR; + wire [1:0]auto_cc_to_s00_couplers_AWBURST; + wire [3:0]auto_cc_to_s00_couplers_AWCACHE; + wire [7:0]auto_cc_to_s00_couplers_AWLEN; + wire [0:0]auto_cc_to_s00_couplers_AWLOCK; + wire [2:0]auto_cc_to_s00_couplers_AWPROT; + wire [3:0]auto_cc_to_s00_couplers_AWQOS; + wire auto_cc_to_s00_couplers_AWREADY; + wire [2:0]auto_cc_to_s00_couplers_AWSIZE; + wire auto_cc_to_s00_couplers_AWVALID; + wire auto_cc_to_s00_couplers_BREADY; + wire [1:0]auto_cc_to_s00_couplers_BRESP; + wire auto_cc_to_s00_couplers_BVALID; + wire [511:0]auto_cc_to_s00_couplers_RDATA; + wire auto_cc_to_s00_couplers_RLAST; + wire auto_cc_to_s00_couplers_RREADY; + wire [1:0]auto_cc_to_s00_couplers_RRESP; + wire auto_cc_to_s00_couplers_RVALID; + wire [511:0]auto_cc_to_s00_couplers_WDATA; + wire auto_cc_to_s00_couplers_WLAST; + wire auto_cc_to_s00_couplers_WREADY; + wire [63:0]auto_cc_to_s00_couplers_WSTRB; + wire auto_cc_to_s00_couplers_WVALID; + wire [63:0]auto_us_to_auto_cc_ARADDR; + wire [1:0]auto_us_to_auto_cc_ARBURST; + wire [3:0]auto_us_to_auto_cc_ARCACHE; + wire [7:0]auto_us_to_auto_cc_ARLEN; + wire [0:0]auto_us_to_auto_cc_ARLOCK; + wire [2:0]auto_us_to_auto_cc_ARPROT; + wire [3:0]auto_us_to_auto_cc_ARQOS; + wire auto_us_to_auto_cc_ARREADY; + wire [3:0]auto_us_to_auto_cc_ARREGION; + wire [2:0]auto_us_to_auto_cc_ARSIZE; + wire auto_us_to_auto_cc_ARVALID; + wire [63:0]auto_us_to_auto_cc_AWADDR; + wire [1:0]auto_us_to_auto_cc_AWBURST; + wire [3:0]auto_us_to_auto_cc_AWCACHE; + wire [7:0]auto_us_to_auto_cc_AWLEN; + wire [0:0]auto_us_to_auto_cc_AWLOCK; + wire [2:0]auto_us_to_auto_cc_AWPROT; + wire [3:0]auto_us_to_auto_cc_AWQOS; + wire auto_us_to_auto_cc_AWREADY; + wire [3:0]auto_us_to_auto_cc_AWREGION; + wire [2:0]auto_us_to_auto_cc_AWSIZE; + wire auto_us_to_auto_cc_AWVALID; + wire auto_us_to_auto_cc_BREADY; + wire [1:0]auto_us_to_auto_cc_BRESP; + wire auto_us_to_auto_cc_BVALID; + wire [511:0]auto_us_to_auto_cc_RDATA; + wire auto_us_to_auto_cc_RLAST; + wire auto_us_to_auto_cc_RREADY; + wire [1:0]auto_us_to_auto_cc_RRESP; + wire auto_us_to_auto_cc_RVALID; + wire [511:0]auto_us_to_auto_cc_WDATA; + wire auto_us_to_auto_cc_WLAST; + wire auto_us_to_auto_cc_WREADY; + wire [63:0]auto_us_to_auto_cc_WSTRB; + wire auto_us_to_auto_cc_WVALID; + wire [63:0]s00_couplers_to_auto_us_ARADDR; + wire [1:0]s00_couplers_to_auto_us_ARBURST; + wire [3:0]s00_couplers_to_auto_us_ARCACHE; + wire [3:0]s00_couplers_to_auto_us_ARID; + wire [7:0]s00_couplers_to_auto_us_ARLEN; + wire [0:0]s00_couplers_to_auto_us_ARLOCK; + wire [2:0]s00_couplers_to_auto_us_ARPROT; + wire s00_couplers_to_auto_us_ARREADY; + wire [2:0]s00_couplers_to_auto_us_ARSIZE; + wire s00_couplers_to_auto_us_ARVALID; + wire [63:0]s00_couplers_to_auto_us_AWADDR; + wire [1:0]s00_couplers_to_auto_us_AWBURST; + wire [3:0]s00_couplers_to_auto_us_AWCACHE; + wire [3:0]s00_couplers_to_auto_us_AWID; + wire [7:0]s00_couplers_to_auto_us_AWLEN; + wire [0:0]s00_couplers_to_auto_us_AWLOCK; + wire [2:0]s00_couplers_to_auto_us_AWPROT; + wire s00_couplers_to_auto_us_AWREADY; + wire [2:0]s00_couplers_to_auto_us_AWSIZE; + wire s00_couplers_to_auto_us_AWVALID; + wire [3:0]s00_couplers_to_auto_us_BID; + wire s00_couplers_to_auto_us_BREADY; + wire [1:0]s00_couplers_to_auto_us_BRESP; + wire s00_couplers_to_auto_us_BVALID; + wire [127:0]s00_couplers_to_auto_us_RDATA; + wire [3:0]s00_couplers_to_auto_us_RID; + wire s00_couplers_to_auto_us_RLAST; + wire s00_couplers_to_auto_us_RREADY; + wire [1:0]s00_couplers_to_auto_us_RRESP; + wire s00_couplers_to_auto_us_RVALID; + wire [127:0]s00_couplers_to_auto_us_WDATA; + wire s00_couplers_to_auto_us_WLAST; + wire s00_couplers_to_auto_us_WREADY; + wire [15:0]s00_couplers_to_auto_us_WSTRB; + wire s00_couplers_to_auto_us_WVALID; + + assign M_ACLK_1 = M_ACLK; + assign M_ARESETN_1 = M_ARESETN; + assign M_AXI_araddr[63:0] = auto_cc_to_s00_couplers_ARADDR; + assign M_AXI_arburst[1:0] = auto_cc_to_s00_couplers_ARBURST; + assign M_AXI_arcache[3:0] = auto_cc_to_s00_couplers_ARCACHE; + assign M_AXI_arlen[7:0] = auto_cc_to_s00_couplers_ARLEN; + assign M_AXI_arlock[0] = auto_cc_to_s00_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = auto_cc_to_s00_couplers_ARPROT; + assign M_AXI_arqos[3:0] = auto_cc_to_s00_couplers_ARQOS; + assign M_AXI_arsize[2:0] = auto_cc_to_s00_couplers_ARSIZE; + assign M_AXI_arvalid = auto_cc_to_s00_couplers_ARVALID; + assign M_AXI_awaddr[63:0] = auto_cc_to_s00_couplers_AWADDR; + assign M_AXI_awburst[1:0] = auto_cc_to_s00_couplers_AWBURST; + assign M_AXI_awcache[3:0] = auto_cc_to_s00_couplers_AWCACHE; + assign M_AXI_awlen[7:0] = auto_cc_to_s00_couplers_AWLEN; + assign M_AXI_awlock[0] = auto_cc_to_s00_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = auto_cc_to_s00_couplers_AWPROT; + assign M_AXI_awqos[3:0] = auto_cc_to_s00_couplers_AWQOS; + assign M_AXI_awsize[2:0] = auto_cc_to_s00_couplers_AWSIZE; + assign M_AXI_awvalid = auto_cc_to_s00_couplers_AWVALID; + assign M_AXI_bready = auto_cc_to_s00_couplers_BREADY; + assign M_AXI_rready = auto_cc_to_s00_couplers_RREADY; + assign M_AXI_wdata[511:0] = auto_cc_to_s00_couplers_WDATA; + assign M_AXI_wlast = auto_cc_to_s00_couplers_WLAST; + assign M_AXI_wstrb[63:0] = auto_cc_to_s00_couplers_WSTRB; + assign M_AXI_wvalid = auto_cc_to_s00_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = s00_couplers_to_auto_us_ARREADY; + assign S_AXI_awready = s00_couplers_to_auto_us_AWREADY; + assign S_AXI_bid[3:0] = s00_couplers_to_auto_us_BID; + assign S_AXI_bresp[1:0] = s00_couplers_to_auto_us_BRESP; + assign S_AXI_bvalid = s00_couplers_to_auto_us_BVALID; + assign S_AXI_rdata[127:0] = s00_couplers_to_auto_us_RDATA; + assign S_AXI_rid[3:0] = s00_couplers_to_auto_us_RID; + assign S_AXI_rlast = s00_couplers_to_auto_us_RLAST; + assign S_AXI_rresp[1:0] = s00_couplers_to_auto_us_RRESP; + assign S_AXI_rvalid = s00_couplers_to_auto_us_RVALID; + assign S_AXI_wready = s00_couplers_to_auto_us_WREADY; + assign auto_cc_to_s00_couplers_ARREADY = M_AXI_arready; + assign auto_cc_to_s00_couplers_AWREADY = M_AXI_awready; + assign auto_cc_to_s00_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_cc_to_s00_couplers_BVALID = M_AXI_bvalid; + assign auto_cc_to_s00_couplers_RDATA = M_AXI_rdata[511:0]; + assign auto_cc_to_s00_couplers_RLAST = M_AXI_rlast; + assign auto_cc_to_s00_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_cc_to_s00_couplers_RVALID = M_AXI_rvalid; + assign auto_cc_to_s00_couplers_WREADY = M_AXI_wready; + assign s00_couplers_to_auto_us_ARADDR = S_AXI_araddr[63:0]; + assign s00_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0]; + assign s00_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0]; + assign s00_couplers_to_auto_us_ARID = S_AXI_arid[3:0]; + assign s00_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0]; + assign s00_couplers_to_auto_us_ARLOCK = S_AXI_arlock[0]; + assign s00_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0]; + assign s00_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0]; + assign s00_couplers_to_auto_us_ARVALID = S_AXI_arvalid; + assign s00_couplers_to_auto_us_AWADDR = S_AXI_awaddr[63:0]; + assign s00_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0]; + assign s00_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0]; + assign s00_couplers_to_auto_us_AWID = S_AXI_awid[3:0]; + assign s00_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0]; + assign s00_couplers_to_auto_us_AWLOCK = S_AXI_awlock[0]; + assign s00_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0]; + assign s00_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0]; + assign s00_couplers_to_auto_us_AWVALID = S_AXI_awvalid; + assign s00_couplers_to_auto_us_BREADY = S_AXI_bready; + assign s00_couplers_to_auto_us_RREADY = S_AXI_rready; + assign s00_couplers_to_auto_us_WDATA = S_AXI_wdata[127:0]; + assign s00_couplers_to_auto_us_WLAST = S_AXI_wlast; + assign s00_couplers_to_auto_us_WSTRB = S_AXI_wstrb[15:0]; + assign s00_couplers_to_auto_us_WVALID = S_AXI_wvalid; + pcie_ddr_auto_cc_2 auto_cc + (.m_axi_aclk(M_ACLK_1), + .m_axi_araddr(auto_cc_to_s00_couplers_ARADDR), + .m_axi_arburst(auto_cc_to_s00_couplers_ARBURST), + .m_axi_arcache(auto_cc_to_s00_couplers_ARCACHE), + .m_axi_aresetn(M_ARESETN_1), + .m_axi_arlen(auto_cc_to_s00_couplers_ARLEN), + .m_axi_arlock(auto_cc_to_s00_couplers_ARLOCK), + .m_axi_arprot(auto_cc_to_s00_couplers_ARPROT), + .m_axi_arqos(auto_cc_to_s00_couplers_ARQOS), + .m_axi_arready(auto_cc_to_s00_couplers_ARREADY), + .m_axi_arsize(auto_cc_to_s00_couplers_ARSIZE), + .m_axi_arvalid(auto_cc_to_s00_couplers_ARVALID), + .m_axi_awaddr(auto_cc_to_s00_couplers_AWADDR), + .m_axi_awburst(auto_cc_to_s00_couplers_AWBURST), + .m_axi_awcache(auto_cc_to_s00_couplers_AWCACHE), + .m_axi_awlen(auto_cc_to_s00_couplers_AWLEN), + .m_axi_awlock(auto_cc_to_s00_couplers_AWLOCK), + .m_axi_awprot(auto_cc_to_s00_couplers_AWPROT), + .m_axi_awqos(auto_cc_to_s00_couplers_AWQOS), + .m_axi_awready(auto_cc_to_s00_couplers_AWREADY), + .m_axi_awsize(auto_cc_to_s00_couplers_AWSIZE), + .m_axi_awvalid(auto_cc_to_s00_couplers_AWVALID), + .m_axi_bready(auto_cc_to_s00_couplers_BREADY), + .m_axi_bresp(auto_cc_to_s00_couplers_BRESP), + .m_axi_bvalid(auto_cc_to_s00_couplers_BVALID), + .m_axi_rdata(auto_cc_to_s00_couplers_RDATA), + .m_axi_rlast(auto_cc_to_s00_couplers_RLAST), + .m_axi_rready(auto_cc_to_s00_couplers_RREADY), + .m_axi_rresp(auto_cc_to_s00_couplers_RRESP), + .m_axi_rvalid(auto_cc_to_s00_couplers_RVALID), + .m_axi_wdata(auto_cc_to_s00_couplers_WDATA), + .m_axi_wlast(auto_cc_to_s00_couplers_WLAST), + .m_axi_wready(auto_cc_to_s00_couplers_WREADY), + .m_axi_wstrb(auto_cc_to_s00_couplers_WSTRB), + .m_axi_wvalid(auto_cc_to_s00_couplers_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(auto_us_to_auto_cc_ARADDR), + .s_axi_arburst(auto_us_to_auto_cc_ARBURST), + .s_axi_arcache(auto_us_to_auto_cc_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arlen(auto_us_to_auto_cc_ARLEN), + .s_axi_arlock(auto_us_to_auto_cc_ARLOCK), + .s_axi_arprot(auto_us_to_auto_cc_ARPROT), + .s_axi_arqos(auto_us_to_auto_cc_ARQOS), + .s_axi_arready(auto_us_to_auto_cc_ARREADY), + .s_axi_arregion(auto_us_to_auto_cc_ARREGION), + .s_axi_arsize(auto_us_to_auto_cc_ARSIZE), + .s_axi_arvalid(auto_us_to_auto_cc_ARVALID), + .s_axi_awaddr(auto_us_to_auto_cc_AWADDR), + .s_axi_awburst(auto_us_to_auto_cc_AWBURST), + .s_axi_awcache(auto_us_to_auto_cc_AWCACHE), + .s_axi_awlen(auto_us_to_auto_cc_AWLEN), + .s_axi_awlock(auto_us_to_auto_cc_AWLOCK), + .s_axi_awprot(auto_us_to_auto_cc_AWPROT), + .s_axi_awqos(auto_us_to_auto_cc_AWQOS), + .s_axi_awready(auto_us_to_auto_cc_AWREADY), + .s_axi_awregion(auto_us_to_auto_cc_AWREGION), + .s_axi_awsize(auto_us_to_auto_cc_AWSIZE), + .s_axi_awvalid(auto_us_to_auto_cc_AWVALID), + .s_axi_bready(auto_us_to_auto_cc_BREADY), + .s_axi_bresp(auto_us_to_auto_cc_BRESP), + .s_axi_bvalid(auto_us_to_auto_cc_BVALID), + .s_axi_rdata(auto_us_to_auto_cc_RDATA), + .s_axi_rlast(auto_us_to_auto_cc_RLAST), + .s_axi_rready(auto_us_to_auto_cc_RREADY), + .s_axi_rresp(auto_us_to_auto_cc_RRESP), + .s_axi_rvalid(auto_us_to_auto_cc_RVALID), + .s_axi_wdata(auto_us_to_auto_cc_WDATA), + .s_axi_wlast(auto_us_to_auto_cc_WLAST), + .s_axi_wready(auto_us_to_auto_cc_WREADY), + .s_axi_wstrb(auto_us_to_auto_cc_WSTRB), + .s_axi_wvalid(auto_us_to_auto_cc_WVALID)); + pcie_ddr_auto_us_0 auto_us + (.m_axi_araddr(auto_us_to_auto_cc_ARADDR), + .m_axi_arburst(auto_us_to_auto_cc_ARBURST), + .m_axi_arcache(auto_us_to_auto_cc_ARCACHE), + .m_axi_arlen(auto_us_to_auto_cc_ARLEN), + .m_axi_arlock(auto_us_to_auto_cc_ARLOCK), + .m_axi_arprot(auto_us_to_auto_cc_ARPROT), + .m_axi_arqos(auto_us_to_auto_cc_ARQOS), + .m_axi_arready(auto_us_to_auto_cc_ARREADY), + .m_axi_arregion(auto_us_to_auto_cc_ARREGION), + .m_axi_arsize(auto_us_to_auto_cc_ARSIZE), + .m_axi_arvalid(auto_us_to_auto_cc_ARVALID), + .m_axi_awaddr(auto_us_to_auto_cc_AWADDR), + .m_axi_awburst(auto_us_to_auto_cc_AWBURST), + .m_axi_awcache(auto_us_to_auto_cc_AWCACHE), + .m_axi_awlen(auto_us_to_auto_cc_AWLEN), + .m_axi_awlock(auto_us_to_auto_cc_AWLOCK), + .m_axi_awprot(auto_us_to_auto_cc_AWPROT), + .m_axi_awqos(auto_us_to_auto_cc_AWQOS), + .m_axi_awready(auto_us_to_auto_cc_AWREADY), + .m_axi_awregion(auto_us_to_auto_cc_AWREGION), + .m_axi_awsize(auto_us_to_auto_cc_AWSIZE), + .m_axi_awvalid(auto_us_to_auto_cc_AWVALID), + .m_axi_bready(auto_us_to_auto_cc_BREADY), + .m_axi_bresp(auto_us_to_auto_cc_BRESP), + .m_axi_bvalid(auto_us_to_auto_cc_BVALID), + .m_axi_rdata(auto_us_to_auto_cc_RDATA), + .m_axi_rlast(auto_us_to_auto_cc_RLAST), + .m_axi_rready(auto_us_to_auto_cc_RREADY), + .m_axi_rresp(auto_us_to_auto_cc_RRESP), + .m_axi_rvalid(auto_us_to_auto_cc_RVALID), + .m_axi_wdata(auto_us_to_auto_cc_WDATA), + .m_axi_wlast(auto_us_to_auto_cc_WLAST), + .m_axi_wready(auto_us_to_auto_cc_WREADY), + .m_axi_wstrb(auto_us_to_auto_cc_WSTRB), + .m_axi_wvalid(auto_us_to_auto_cc_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(s00_couplers_to_auto_us_ARADDR), + .s_axi_arburst(s00_couplers_to_auto_us_ARBURST), + .s_axi_arcache(s00_couplers_to_auto_us_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arid(s00_couplers_to_auto_us_ARID), + .s_axi_arlen(s00_couplers_to_auto_us_ARLEN), + .s_axi_arlock(s00_couplers_to_auto_us_ARLOCK), + .s_axi_arprot(s00_couplers_to_auto_us_ARPROT), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(s00_couplers_to_auto_us_ARREADY), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize(s00_couplers_to_auto_us_ARSIZE), + .s_axi_arvalid(s00_couplers_to_auto_us_ARVALID), + .s_axi_awaddr(s00_couplers_to_auto_us_AWADDR), + .s_axi_awburst(s00_couplers_to_auto_us_AWBURST), + .s_axi_awcache(s00_couplers_to_auto_us_AWCACHE), + .s_axi_awid(s00_couplers_to_auto_us_AWID), + .s_axi_awlen(s00_couplers_to_auto_us_AWLEN), + .s_axi_awlock(s00_couplers_to_auto_us_AWLOCK), + .s_axi_awprot(s00_couplers_to_auto_us_AWPROT), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(s00_couplers_to_auto_us_AWREADY), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize(s00_couplers_to_auto_us_AWSIZE), + .s_axi_awvalid(s00_couplers_to_auto_us_AWVALID), + .s_axi_bid(s00_couplers_to_auto_us_BID), + .s_axi_bready(s00_couplers_to_auto_us_BREADY), + .s_axi_bresp(s00_couplers_to_auto_us_BRESP), + .s_axi_bvalid(s00_couplers_to_auto_us_BVALID), + .s_axi_rdata(s00_couplers_to_auto_us_RDATA), + .s_axi_rid(s00_couplers_to_auto_us_RID), + .s_axi_rlast(s00_couplers_to_auto_us_RLAST), + .s_axi_rready(s00_couplers_to_auto_us_RREADY), + .s_axi_rresp(s00_couplers_to_auto_us_RRESP), + .s_axi_rvalid(s00_couplers_to_auto_us_RVALID), + .s_axi_wdata(s00_couplers_to_auto_us_WDATA), + .s_axi_wlast(s00_couplers_to_auto_us_WLAST), + .s_axi_wready(s00_couplers_to_auto_us_WREADY), + .s_axi_wstrb(s00_couplers_to_auto_us_WSTRB), + .s_axi_wvalid(s00_couplers_to_auto_us_WVALID)); +endmodule + +module s01_couplers_imp_1CQ4OV4 + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [31:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [7:0]M_AXI_arlen; + output [0:0]M_AXI_arlock; + output [2:0]M_AXI_arprot; + output [3:0]M_AXI_arqos; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [31:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [7:0]M_AXI_awlen; + output [0:0]M_AXI_awlock; + output [2:0]M_AXI_awprot; + output [3:0]M_AXI_awqos; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [511:0]M_AXI_rdata; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [511:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [63:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [31:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [0:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + input [3:0]S_AXI_arqos; + output S_AXI_arready; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [31:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [0:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + input [3:0]S_AXI_awqos; + output S_AXI_awready; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [0:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [31:0]S_AXI_rdata; + output [0:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [31:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [3:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire M_ACLK_1; + wire M_ARESETN_1; + wire S_ACLK_1; + wire S_ARESETN_1; + wire [31:0]auto_cc_to_s01_couplers_ARADDR; + wire [1:0]auto_cc_to_s01_couplers_ARBURST; + wire [3:0]auto_cc_to_s01_couplers_ARCACHE; + wire [7:0]auto_cc_to_s01_couplers_ARLEN; + wire [0:0]auto_cc_to_s01_couplers_ARLOCK; + wire [2:0]auto_cc_to_s01_couplers_ARPROT; + wire [3:0]auto_cc_to_s01_couplers_ARQOS; + wire auto_cc_to_s01_couplers_ARREADY; + wire [2:0]auto_cc_to_s01_couplers_ARSIZE; + wire auto_cc_to_s01_couplers_ARVALID; + wire [31:0]auto_cc_to_s01_couplers_AWADDR; + wire [1:0]auto_cc_to_s01_couplers_AWBURST; + wire [3:0]auto_cc_to_s01_couplers_AWCACHE; + wire [7:0]auto_cc_to_s01_couplers_AWLEN; + wire [0:0]auto_cc_to_s01_couplers_AWLOCK; + wire [2:0]auto_cc_to_s01_couplers_AWPROT; + wire [3:0]auto_cc_to_s01_couplers_AWQOS; + wire auto_cc_to_s01_couplers_AWREADY; + wire [2:0]auto_cc_to_s01_couplers_AWSIZE; + wire auto_cc_to_s01_couplers_AWVALID; + wire auto_cc_to_s01_couplers_BREADY; + wire [1:0]auto_cc_to_s01_couplers_BRESP; + wire auto_cc_to_s01_couplers_BVALID; + wire [511:0]auto_cc_to_s01_couplers_RDATA; + wire auto_cc_to_s01_couplers_RLAST; + wire auto_cc_to_s01_couplers_RREADY; + wire [1:0]auto_cc_to_s01_couplers_RRESP; + wire auto_cc_to_s01_couplers_RVALID; + wire [511:0]auto_cc_to_s01_couplers_WDATA; + wire auto_cc_to_s01_couplers_WLAST; + wire auto_cc_to_s01_couplers_WREADY; + wire [63:0]auto_cc_to_s01_couplers_WSTRB; + wire auto_cc_to_s01_couplers_WVALID; + wire [31:0]auto_us_to_auto_cc_ARADDR; + wire [1:0]auto_us_to_auto_cc_ARBURST; + wire [3:0]auto_us_to_auto_cc_ARCACHE; + wire [7:0]auto_us_to_auto_cc_ARLEN; + wire [0:0]auto_us_to_auto_cc_ARLOCK; + wire [2:0]auto_us_to_auto_cc_ARPROT; + wire [3:0]auto_us_to_auto_cc_ARQOS; + wire auto_us_to_auto_cc_ARREADY; + wire [3:0]auto_us_to_auto_cc_ARREGION; + wire [2:0]auto_us_to_auto_cc_ARSIZE; + wire auto_us_to_auto_cc_ARVALID; + wire [31:0]auto_us_to_auto_cc_AWADDR; + wire [1:0]auto_us_to_auto_cc_AWBURST; + wire [3:0]auto_us_to_auto_cc_AWCACHE; + wire [7:0]auto_us_to_auto_cc_AWLEN; + wire [0:0]auto_us_to_auto_cc_AWLOCK; + wire [2:0]auto_us_to_auto_cc_AWPROT; + wire [3:0]auto_us_to_auto_cc_AWQOS; + wire auto_us_to_auto_cc_AWREADY; + wire [3:0]auto_us_to_auto_cc_AWREGION; + wire [2:0]auto_us_to_auto_cc_AWSIZE; + wire auto_us_to_auto_cc_AWVALID; + wire auto_us_to_auto_cc_BREADY; + wire [1:0]auto_us_to_auto_cc_BRESP; + wire auto_us_to_auto_cc_BVALID; + wire [511:0]auto_us_to_auto_cc_RDATA; + wire auto_us_to_auto_cc_RLAST; + wire auto_us_to_auto_cc_RREADY; + wire [1:0]auto_us_to_auto_cc_RRESP; + wire auto_us_to_auto_cc_RVALID; + wire [511:0]auto_us_to_auto_cc_WDATA; + wire auto_us_to_auto_cc_WLAST; + wire auto_us_to_auto_cc_WREADY; + wire [63:0]auto_us_to_auto_cc_WSTRB; + wire auto_us_to_auto_cc_WVALID; + wire [31:0]s01_couplers_to_auto_us_ARADDR; + wire [1:0]s01_couplers_to_auto_us_ARBURST; + wire [3:0]s01_couplers_to_auto_us_ARCACHE; + wire [0:0]s01_couplers_to_auto_us_ARID; + wire [7:0]s01_couplers_to_auto_us_ARLEN; + wire [0:0]s01_couplers_to_auto_us_ARLOCK; + wire [2:0]s01_couplers_to_auto_us_ARPROT; + wire [3:0]s01_couplers_to_auto_us_ARQOS; + wire s01_couplers_to_auto_us_ARREADY; + wire [2:0]s01_couplers_to_auto_us_ARSIZE; + wire s01_couplers_to_auto_us_ARVALID; + wire [31:0]s01_couplers_to_auto_us_AWADDR; + wire [1:0]s01_couplers_to_auto_us_AWBURST; + wire [3:0]s01_couplers_to_auto_us_AWCACHE; + wire [0:0]s01_couplers_to_auto_us_AWID; + wire [7:0]s01_couplers_to_auto_us_AWLEN; + wire [0:0]s01_couplers_to_auto_us_AWLOCK; + wire [2:0]s01_couplers_to_auto_us_AWPROT; + wire [3:0]s01_couplers_to_auto_us_AWQOS; + wire s01_couplers_to_auto_us_AWREADY; + wire [2:0]s01_couplers_to_auto_us_AWSIZE; + wire s01_couplers_to_auto_us_AWVALID; + wire [0:0]s01_couplers_to_auto_us_BID; + wire s01_couplers_to_auto_us_BREADY; + wire [1:0]s01_couplers_to_auto_us_BRESP; + wire s01_couplers_to_auto_us_BVALID; + wire [31:0]s01_couplers_to_auto_us_RDATA; + wire [0:0]s01_couplers_to_auto_us_RID; + wire s01_couplers_to_auto_us_RLAST; + wire s01_couplers_to_auto_us_RREADY; + wire [1:0]s01_couplers_to_auto_us_RRESP; + wire s01_couplers_to_auto_us_RVALID; + wire [31:0]s01_couplers_to_auto_us_WDATA; + wire s01_couplers_to_auto_us_WLAST; + wire s01_couplers_to_auto_us_WREADY; + wire [3:0]s01_couplers_to_auto_us_WSTRB; + wire s01_couplers_to_auto_us_WVALID; + + assign M_ACLK_1 = M_ACLK; + assign M_ARESETN_1 = M_ARESETN; + assign M_AXI_araddr[31:0] = auto_cc_to_s01_couplers_ARADDR; + assign M_AXI_arburst[1:0] = auto_cc_to_s01_couplers_ARBURST; + assign M_AXI_arcache[3:0] = auto_cc_to_s01_couplers_ARCACHE; + assign M_AXI_arlen[7:0] = auto_cc_to_s01_couplers_ARLEN; + assign M_AXI_arlock[0] = auto_cc_to_s01_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = auto_cc_to_s01_couplers_ARPROT; + assign M_AXI_arqos[3:0] = auto_cc_to_s01_couplers_ARQOS; + assign M_AXI_arsize[2:0] = auto_cc_to_s01_couplers_ARSIZE; + assign M_AXI_arvalid = auto_cc_to_s01_couplers_ARVALID; + assign M_AXI_awaddr[31:0] = auto_cc_to_s01_couplers_AWADDR; + assign M_AXI_awburst[1:0] = auto_cc_to_s01_couplers_AWBURST; + assign M_AXI_awcache[3:0] = auto_cc_to_s01_couplers_AWCACHE; + assign M_AXI_awlen[7:0] = auto_cc_to_s01_couplers_AWLEN; + assign M_AXI_awlock[0] = auto_cc_to_s01_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = auto_cc_to_s01_couplers_AWPROT; + assign M_AXI_awqos[3:0] = auto_cc_to_s01_couplers_AWQOS; + assign M_AXI_awsize[2:0] = auto_cc_to_s01_couplers_AWSIZE; + assign M_AXI_awvalid = auto_cc_to_s01_couplers_AWVALID; + assign M_AXI_bready = auto_cc_to_s01_couplers_BREADY; + assign M_AXI_rready = auto_cc_to_s01_couplers_RREADY; + assign M_AXI_wdata[511:0] = auto_cc_to_s01_couplers_WDATA; + assign M_AXI_wlast = auto_cc_to_s01_couplers_WLAST; + assign M_AXI_wstrb[63:0] = auto_cc_to_s01_couplers_WSTRB; + assign M_AXI_wvalid = auto_cc_to_s01_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = s01_couplers_to_auto_us_ARREADY; + assign S_AXI_awready = s01_couplers_to_auto_us_AWREADY; + assign S_AXI_bid[0] = s01_couplers_to_auto_us_BID; + assign S_AXI_bresp[1:0] = s01_couplers_to_auto_us_BRESP; + assign S_AXI_bvalid = s01_couplers_to_auto_us_BVALID; + assign S_AXI_rdata[31:0] = s01_couplers_to_auto_us_RDATA; + assign S_AXI_rid[0] = s01_couplers_to_auto_us_RID; + assign S_AXI_rlast = s01_couplers_to_auto_us_RLAST; + assign S_AXI_rresp[1:0] = s01_couplers_to_auto_us_RRESP; + assign S_AXI_rvalid = s01_couplers_to_auto_us_RVALID; + assign S_AXI_wready = s01_couplers_to_auto_us_WREADY; + assign auto_cc_to_s01_couplers_ARREADY = M_AXI_arready; + assign auto_cc_to_s01_couplers_AWREADY = M_AXI_awready; + assign auto_cc_to_s01_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_cc_to_s01_couplers_BVALID = M_AXI_bvalid; + assign auto_cc_to_s01_couplers_RDATA = M_AXI_rdata[511:0]; + assign auto_cc_to_s01_couplers_RLAST = M_AXI_rlast; + assign auto_cc_to_s01_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_cc_to_s01_couplers_RVALID = M_AXI_rvalid; + assign auto_cc_to_s01_couplers_WREADY = M_AXI_wready; + assign s01_couplers_to_auto_us_ARADDR = S_AXI_araddr[31:0]; + assign s01_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0]; + assign s01_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0]; + assign s01_couplers_to_auto_us_ARID = S_AXI_arid[0]; + assign s01_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0]; + assign s01_couplers_to_auto_us_ARLOCK = S_AXI_arlock[0]; + assign s01_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0]; + assign s01_couplers_to_auto_us_ARQOS = S_AXI_arqos[3:0]; + assign s01_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0]; + assign s01_couplers_to_auto_us_ARVALID = S_AXI_arvalid; + assign s01_couplers_to_auto_us_AWADDR = S_AXI_awaddr[31:0]; + assign s01_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0]; + assign s01_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0]; + assign s01_couplers_to_auto_us_AWID = S_AXI_awid[0]; + assign s01_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0]; + assign s01_couplers_to_auto_us_AWLOCK = S_AXI_awlock[0]; + assign s01_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0]; + assign s01_couplers_to_auto_us_AWQOS = S_AXI_awqos[3:0]; + assign s01_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0]; + assign s01_couplers_to_auto_us_AWVALID = S_AXI_awvalid; + assign s01_couplers_to_auto_us_BREADY = S_AXI_bready; + assign s01_couplers_to_auto_us_RREADY = S_AXI_rready; + assign s01_couplers_to_auto_us_WDATA = S_AXI_wdata[31:0]; + assign s01_couplers_to_auto_us_WLAST = S_AXI_wlast; + assign s01_couplers_to_auto_us_WSTRB = S_AXI_wstrb[3:0]; + assign s01_couplers_to_auto_us_WVALID = S_AXI_wvalid; + pcie_ddr_auto_cc_3 auto_cc + (.m_axi_aclk(M_ACLK_1), + .m_axi_araddr(auto_cc_to_s01_couplers_ARADDR), + .m_axi_arburst(auto_cc_to_s01_couplers_ARBURST), + .m_axi_arcache(auto_cc_to_s01_couplers_ARCACHE), + .m_axi_aresetn(M_ARESETN_1), + .m_axi_arlen(auto_cc_to_s01_couplers_ARLEN), + .m_axi_arlock(auto_cc_to_s01_couplers_ARLOCK), + .m_axi_arprot(auto_cc_to_s01_couplers_ARPROT), + .m_axi_arqos(auto_cc_to_s01_couplers_ARQOS), + .m_axi_arready(auto_cc_to_s01_couplers_ARREADY), + .m_axi_arsize(auto_cc_to_s01_couplers_ARSIZE), + .m_axi_arvalid(auto_cc_to_s01_couplers_ARVALID), + .m_axi_awaddr(auto_cc_to_s01_couplers_AWADDR), + .m_axi_awburst(auto_cc_to_s01_couplers_AWBURST), + .m_axi_awcache(auto_cc_to_s01_couplers_AWCACHE), + .m_axi_awlen(auto_cc_to_s01_couplers_AWLEN), + .m_axi_awlock(auto_cc_to_s01_couplers_AWLOCK), + .m_axi_awprot(auto_cc_to_s01_couplers_AWPROT), + .m_axi_awqos(auto_cc_to_s01_couplers_AWQOS), + .m_axi_awready(auto_cc_to_s01_couplers_AWREADY), + .m_axi_awsize(auto_cc_to_s01_couplers_AWSIZE), + .m_axi_awvalid(auto_cc_to_s01_couplers_AWVALID), + .m_axi_bready(auto_cc_to_s01_couplers_BREADY), + .m_axi_bresp(auto_cc_to_s01_couplers_BRESP), + .m_axi_bvalid(auto_cc_to_s01_couplers_BVALID), + .m_axi_rdata(auto_cc_to_s01_couplers_RDATA), + .m_axi_rlast(auto_cc_to_s01_couplers_RLAST), + .m_axi_rready(auto_cc_to_s01_couplers_RREADY), + .m_axi_rresp(auto_cc_to_s01_couplers_RRESP), + .m_axi_rvalid(auto_cc_to_s01_couplers_RVALID), + .m_axi_wdata(auto_cc_to_s01_couplers_WDATA), + .m_axi_wlast(auto_cc_to_s01_couplers_WLAST), + .m_axi_wready(auto_cc_to_s01_couplers_WREADY), + .m_axi_wstrb(auto_cc_to_s01_couplers_WSTRB), + .m_axi_wvalid(auto_cc_to_s01_couplers_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(auto_us_to_auto_cc_ARADDR), + .s_axi_arburst(auto_us_to_auto_cc_ARBURST), + .s_axi_arcache(auto_us_to_auto_cc_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arlen(auto_us_to_auto_cc_ARLEN), + .s_axi_arlock(auto_us_to_auto_cc_ARLOCK), + .s_axi_arprot(auto_us_to_auto_cc_ARPROT), + .s_axi_arqos(auto_us_to_auto_cc_ARQOS), + .s_axi_arready(auto_us_to_auto_cc_ARREADY), + .s_axi_arregion(auto_us_to_auto_cc_ARREGION), + .s_axi_arsize(auto_us_to_auto_cc_ARSIZE), + .s_axi_arvalid(auto_us_to_auto_cc_ARVALID), + .s_axi_awaddr(auto_us_to_auto_cc_AWADDR), + .s_axi_awburst(auto_us_to_auto_cc_AWBURST), + .s_axi_awcache(auto_us_to_auto_cc_AWCACHE), + .s_axi_awlen(auto_us_to_auto_cc_AWLEN), + .s_axi_awlock(auto_us_to_auto_cc_AWLOCK), + .s_axi_awprot(auto_us_to_auto_cc_AWPROT), + .s_axi_awqos(auto_us_to_auto_cc_AWQOS), + .s_axi_awready(auto_us_to_auto_cc_AWREADY), + .s_axi_awregion(auto_us_to_auto_cc_AWREGION), + .s_axi_awsize(auto_us_to_auto_cc_AWSIZE), + .s_axi_awvalid(auto_us_to_auto_cc_AWVALID), + .s_axi_bready(auto_us_to_auto_cc_BREADY), + .s_axi_bresp(auto_us_to_auto_cc_BRESP), + .s_axi_bvalid(auto_us_to_auto_cc_BVALID), + .s_axi_rdata(auto_us_to_auto_cc_RDATA), + .s_axi_rlast(auto_us_to_auto_cc_RLAST), + .s_axi_rready(auto_us_to_auto_cc_RREADY), + .s_axi_rresp(auto_us_to_auto_cc_RRESP), + .s_axi_rvalid(auto_us_to_auto_cc_RVALID), + .s_axi_wdata(auto_us_to_auto_cc_WDATA), + .s_axi_wlast(auto_us_to_auto_cc_WLAST), + .s_axi_wready(auto_us_to_auto_cc_WREADY), + .s_axi_wstrb(auto_us_to_auto_cc_WSTRB), + .s_axi_wvalid(auto_us_to_auto_cc_WVALID)); + pcie_ddr_auto_us_1 auto_us + (.m_axi_araddr(auto_us_to_auto_cc_ARADDR), + .m_axi_arburst(auto_us_to_auto_cc_ARBURST), + .m_axi_arcache(auto_us_to_auto_cc_ARCACHE), + .m_axi_arlen(auto_us_to_auto_cc_ARLEN), + .m_axi_arlock(auto_us_to_auto_cc_ARLOCK), + .m_axi_arprot(auto_us_to_auto_cc_ARPROT), + .m_axi_arqos(auto_us_to_auto_cc_ARQOS), + .m_axi_arready(auto_us_to_auto_cc_ARREADY), + .m_axi_arregion(auto_us_to_auto_cc_ARREGION), + .m_axi_arsize(auto_us_to_auto_cc_ARSIZE), + .m_axi_arvalid(auto_us_to_auto_cc_ARVALID), + .m_axi_awaddr(auto_us_to_auto_cc_AWADDR), + .m_axi_awburst(auto_us_to_auto_cc_AWBURST), + .m_axi_awcache(auto_us_to_auto_cc_AWCACHE), + .m_axi_awlen(auto_us_to_auto_cc_AWLEN), + .m_axi_awlock(auto_us_to_auto_cc_AWLOCK), + .m_axi_awprot(auto_us_to_auto_cc_AWPROT), + .m_axi_awqos(auto_us_to_auto_cc_AWQOS), + .m_axi_awready(auto_us_to_auto_cc_AWREADY), + .m_axi_awregion(auto_us_to_auto_cc_AWREGION), + .m_axi_awsize(auto_us_to_auto_cc_AWSIZE), + .m_axi_awvalid(auto_us_to_auto_cc_AWVALID), + .m_axi_bready(auto_us_to_auto_cc_BREADY), + .m_axi_bresp(auto_us_to_auto_cc_BRESP), + .m_axi_bvalid(auto_us_to_auto_cc_BVALID), + .m_axi_rdata(auto_us_to_auto_cc_RDATA), + .m_axi_rlast(auto_us_to_auto_cc_RLAST), + .m_axi_rready(auto_us_to_auto_cc_RREADY), + .m_axi_rresp(auto_us_to_auto_cc_RRESP), + .m_axi_rvalid(auto_us_to_auto_cc_RVALID), + .m_axi_wdata(auto_us_to_auto_cc_WDATA), + .m_axi_wlast(auto_us_to_auto_cc_WLAST), + .m_axi_wready(auto_us_to_auto_cc_WREADY), + .m_axi_wstrb(auto_us_to_auto_cc_WSTRB), + .m_axi_wvalid(auto_us_to_auto_cc_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(s01_couplers_to_auto_us_ARADDR), + .s_axi_arburst(s01_couplers_to_auto_us_ARBURST), + .s_axi_arcache(s01_couplers_to_auto_us_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arid(s01_couplers_to_auto_us_ARID), + .s_axi_arlen(s01_couplers_to_auto_us_ARLEN), + .s_axi_arlock(s01_couplers_to_auto_us_ARLOCK), + .s_axi_arprot(s01_couplers_to_auto_us_ARPROT), + .s_axi_arqos(s01_couplers_to_auto_us_ARQOS), + .s_axi_arready(s01_couplers_to_auto_us_ARREADY), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize(s01_couplers_to_auto_us_ARSIZE), + .s_axi_arvalid(s01_couplers_to_auto_us_ARVALID), + .s_axi_awaddr(s01_couplers_to_auto_us_AWADDR), + .s_axi_awburst(s01_couplers_to_auto_us_AWBURST), + .s_axi_awcache(s01_couplers_to_auto_us_AWCACHE), + .s_axi_awid(s01_couplers_to_auto_us_AWID), + .s_axi_awlen(s01_couplers_to_auto_us_AWLEN), + .s_axi_awlock(s01_couplers_to_auto_us_AWLOCK), + .s_axi_awprot(s01_couplers_to_auto_us_AWPROT), + .s_axi_awqos(s01_couplers_to_auto_us_AWQOS), + .s_axi_awready(s01_couplers_to_auto_us_AWREADY), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize(s01_couplers_to_auto_us_AWSIZE), + .s_axi_awvalid(s01_couplers_to_auto_us_AWVALID), + .s_axi_bid(s01_couplers_to_auto_us_BID), + .s_axi_bready(s01_couplers_to_auto_us_BREADY), + .s_axi_bresp(s01_couplers_to_auto_us_BRESP), + .s_axi_bvalid(s01_couplers_to_auto_us_BVALID), + .s_axi_rdata(s01_couplers_to_auto_us_RDATA), + .s_axi_rid(s01_couplers_to_auto_us_RID), + .s_axi_rlast(s01_couplers_to_auto_us_RLAST), + .s_axi_rready(s01_couplers_to_auto_us_RREADY), + .s_axi_rresp(s01_couplers_to_auto_us_RRESP), + .s_axi_rvalid(s01_couplers_to_auto_us_RVALID), + .s_axi_wdata(s01_couplers_to_auto_us_WDATA), + .s_axi_wlast(s01_couplers_to_auto_us_WLAST), + .s_axi_wready(s01_couplers_to_auto_us_WREADY), + .s_axi_wstrb(s01_couplers_to_auto_us_WSTRB), + .s_axi_wvalid(s01_couplers_to_auto_us_WVALID)); +endmodule diff --git a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ui/bd_c1e426c2.ui b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ui/bd_c1e426c2.ui index 72e43fe..f33bae0 100644 --- a/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ui/bd_c1e426c2.ui +++ b/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ui/bd_c1e426c2.ui @@ -3,8 +3,8 @@ "Color Coded_ScaleFactor":"0.615572", "Color Coded_TopLeft":"-401,-203", "Default View_Layers":"/S01_ARESETN_0_1:true|/xdma_0_axi_aclk:true|/rst_mig_7series_0_100M_peripheral_aresetn:true|/clk_in1_0_1:true|/xdma_0_axi_aresetn:true|/mig_7series_0_ui_clk:true|/rst_clk_wiz_0_200M_peripheral_aresetn:true|/S01_ACLK_0_1:true|/resetn_0_1:true|/clk_wiz_0_clk_out1:true|/mig_7series_0_ui_clk_sync_rst:true|/util_ds_buf_0_IBUF_OUT:true|/sys_rst_n_0_1:true|", - "Default View_ScaleFactor":"1.0", - "Default View_TopLeft":"-387,41", + "Default View_ScaleFactor":"0.891892", + "Default View_TopLeft":"-184,-77", "Display-PortTypeClock":"true", "Display-PortTypeOthers":"true", "Display-PortTypeReset":"true", @@ -18,54 +18,52 @@ "No Loops_TopLeft":"-220,-10", "guistr":"# # String gsaved with Nlview 7.0.21 2019-05-29 bk=1.5064 VDI=41 GEI=36 GUI=JA:9.0 non-TLS # -string -flagsOSRD -preplace port CLK_IN_D_0 -pg 1 -lvl 0 -x -80 -y 600 -defaultsOSRD -preplace port DDR3_0 -pg 1 -lvl 4 -x 1180 -y 270 -defaultsOSRD -preplace port pcie_mgt_0 -pg 1 -lvl 4 -x 1180 -y 570 -defaultsOSRD -preplace port S01_AXI_0 -pg 1 -lvl 0 -x -80 -y 90 -defaultsOSRD -preplace port clk_in1_0 -pg 1 -lvl 0 -x -80 -y 540 -defaultsOSRD -preplace port resetn_0 -pg 1 -lvl 0 -x -80 -y 520 -defaultsOSRD -preplace port sys_rst_n_0 -pg 1 -lvl 0 -x -80 -y 670 -defaultsOSRD -preplace port init_calib_complete_0 -pg 1 -lvl 4 -x 1180 -y 350 -defaultsOSRD -preplace port user_lnk_up_0 -pg 1 -lvl 4 -x 1180 -y 590 -defaultsOSRD -preplace port msi_enable_0 -pg 1 -lvl 4 -x 1180 -y 670 -defaultsOSRD -preplace port S01_ACLK_0 -pg 1 -lvl 0 -x -80 -y 230 -defaultsOSRD -preplace port S01_ARESETN_0 -pg 1 -lvl 0 -x -80 -y 250 -defaultsOSRD -preplace portBus usr_irq_req_0 -pg 1 -lvl 0 -x -80 -y 690 -defaultsOSRD -preplace inst xdma_0 -pg 1 -lvl 3 -x 980 -y 620 -defaultsOSRD -preplace inst mig_7series_0 -pg 1 -lvl 3 -x 980 -y 310 -defaultsOSRD -preplace inst util_ds_buf_0 -pg 1 -lvl 2 -x 560 -y 600 -swap {0 1 2 4 3} -defaultsOSRD -preplace inst clk_wiz_0 -pg 1 -lvl 1 -x 120 -y 530 -defaultsOSRD -preplace inst axi_interconnect_0 -pg 1 -lvl 2 -x 560 -y 160 -defaultsOSRD -preplace inst rst_mig_7series_0_100M -pg 1 -lvl 1 -x 120 -y 360 -swap {4 0 2 3 1 5 6 7 8 9} -defaultsOSRD -preplace netloc clk_in1_0_1 1 0 1 NJ 540 -preplace netloc resetn_0_1 1 0 1 NJ 520 -preplace netloc clk_wiz_0_clk_out1 1 1 2 290 330 730J -preplace netloc util_ds_buf_0_IBUF_OUT 1 2 1 NJ 610 -preplace netloc sys_rst_n_0_1 1 0 3 NJ 670 NJ 670 710J -preplace netloc clk_wiz_0_locked 1 1 2 320 320 720J -preplace netloc mig_7series_0_init_calib_complete 1 3 1 NJ 350 -preplace netloc xdma_0_user_lnk_up 1 3 1 NJ 590 -preplace netloc xdma_0_msi_enable 1 3 1 NJ 670 -preplace netloc xdma_0_axi_aclk 1 1 3 340 430 NJ 430 1140 -preplace netloc xdma_0_axi_aresetn 1 1 3 350 750 NJ 750 1140 -preplace netloc mig_7series_0_ui_clk 1 0 4 -50 460 300 410 NJ 410 1140 -preplace netloc mig_7series_0_mmcm_locked 1 0 4 -50 260 320J 310 710J 210 1150 -preplace netloc mig_7series_0_ui_clk_sync_rst 1 0 4 -60 10 NJ 10 NJ 10 1160 -preplace netloc rst_mig_7series_0_100M_peripheral_aresetn 1 1 2 310 340 NJ -preplace netloc S01_ACLK_0_1 1 0 2 NJ 230 NJ -preplace netloc S01_ARESETN_0_1 1 0 2 NJ 250 NJ -preplace netloc usr_irq_req_0_1 1 0 3 NJ 690 NJ 690 720J -preplace netloc xdma_0_M_AXI 1 1 3 330 420 NJ 420 1150 -preplace netloc axi_interconnect_0_M00_AXI 1 2 1 720 160n -preplace netloc S01_AXI_0_1 1 0 2 NJ 90 NJ -preplace netloc CLK_IN_D_0_1 1 0 2 NJ 600 NJ -preplace netloc mig_7series_0_DDR3 1 3 1 NJ 270 -preplace netloc xdma_0_pcie_mgt 1 3 1 NJ 570 -levelinfo -pg 1 -80 120 560 980 1180 -pagesize -pg 1 -db -bbox -sgen -250 0 1370 1500 +preplace port pcie_clk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD +preplace port ddr -pg 1 -lvl 5 -x 1310 -y 100 -defaultsOSRD +preplace port pcie_mgt -pg 1 -lvl 5 -x 1310 -y 620 -defaultsOSRD +preplace port ddr_axi -pg 1 -lvl 0 -x 0 -y 460 -defaultsOSRD +preplace port sys_clk -pg 1 -lvl 0 -x 0 -y 340 -defaultsOSRD +preplace port sys_rstn -pg 1 -lvl 0 -x 0 -y 320 -defaultsOSRD +preplace port sys_rst_n_0 -pg 1 -lvl 0 -x 0 -y 680 -defaultsOSRD +preplace port init_calib_complete -pg 1 -lvl 5 -x 1310 -y 180 -defaultsOSRD +preplace port pcie_user_lnk_up -pg 1 -lvl 5 -x 1310 -y 640 -defaultsOSRD +preplace port pcie_msi_enable -pg 1 -lvl 5 -x 1310 -y 720 -defaultsOSRD +preplace portBus pcie_usr_irq_req -pg 1 -lvl 0 -x 0 -y 700 -defaultsOSRD +preplace inst xdma_0 -pg 1 -lvl 4 -x 1110 -y 670 -defaultsOSRD +preplace inst mig_7series_0 -pg 1 -lvl 4 -x 1110 -y 140 -defaultsOSRD +preplace inst util_ds_buf_0 -pg 1 -lvl 3 -x 780 -y 240 -swap {0 1 2 4 3} -defaultsOSRD +preplace inst clk_wiz_0 -pg 1 -lvl 1 -x 120 -y 330 -defaultsOSRD +preplace inst axi_interconnect_0 -pg 1 -lvl 3 -x 780 -y 530 -defaultsOSRD +preplace inst rst_clk_wiz_0_200M -pg 1 -lvl 2 -x 400 -y 360 -defaultsOSRD +preplace inst rst_mig_7series_0_100M -pg 1 -lvl 2 -x 400 -y 130 -defaultsOSRD +preplace netloc clk_in1_0_1 1 0 3 20 600 NJ 600 NJ +preplace netloc resetn_0_1 1 0 3 30 400 230 620 NJ +preplace netloc clk_wiz_0_clk_out1 1 1 3 210 250 610 150 NJ +preplace netloc util_ds_buf_0_IBUF_OUT 1 3 1 930J 250n +preplace netloc sys_rst_n_0_1 1 0 4 NJ 680 NJ 680 NJ 680 NJ +preplace netloc clk_wiz_0_locked 1 1 3 220 260 600J 310 950 +preplace netloc mig_7series_0_init_calib_complete 1 4 1 NJ 180 +preplace netloc xdma_0_user_lnk_up 1 4 1 NJ 640 +preplace netloc xdma_0_msi_enable 1 4 1 NJ 720 +preplace netloc usr_irq_req_0_1 1 0 4 NJ 700 NJ 700 NJ 700 NJ +preplace netloc rst_clk_wiz_0_200M_peripheral_aresetn 1 2 1 570 400n +preplace netloc xdma_0_axi_aclk 1 2 3 630 380 NJ 380 1270 +preplace netloc xdma_0_axi_aresetn 1 2 3 630 800 NJ 800 1270 +preplace netloc mig_7series_0_ui_clk 1 1 4 220 10 580 40 NJ 40 1270 +preplace netloc mig_7series_0_mmcm_locked 1 1 4 210 20 NJ 20 NJ 20 1290 +preplace netloc mig_7series_0_ui_clk_sync_rst 1 1 4 230 30 NJ 30 NJ 30 1280 +preplace netloc rst_mig_7series_0_100M_peripheral_aresetn 1 2 2 590 170 NJ +preplace netloc xdma_0_pcie_mgt 1 4 1 NJ 620 +preplace netloc CLK_IN_D_0_1 1 0 3 NJ 240 NJ 240 NJ +preplace netloc mig_7series_0_DDR3 1 4 1 NJ 100 +preplace netloc xdma_0_M_AXI 1 2 3 620 370 NJ 370 1280 +preplace netloc axi_interconnect_0_M00_AXI 1 3 1 940 110n +preplace netloc S01_AXI_0_1 1 0 3 NJ 460 NJ 460 NJ +levelinfo -pg 1 0 120 400 780 1110 1310 +pagesize -pg 1 -db -bbox -sgen -190 0 1490 810 " } { - "da_axi4_cnt":"3", - "da_clkrst_cnt":"1" + "da_axi4_cnt":"5", + "da_clkrst_cnt":"2" } diff --git a/ddr_general_design.srcs/sources_1/ip/ddr3_mig/ddr3_mig.xci b/ddr_general_design.srcs/sources_1/ip/ddr3_mig/ddr3_mig.xci new file mode 100644 index 0000000..13a5653 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/ip/ddr3_mig/ddr3_mig.xci @@ -0,0 +1,2803 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr3_mig + + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 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Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Synchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k325t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v b/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v new file mode 100644 index 0000000..b42c893 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v @@ -0,0 +1,137 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/18 16:15:52 +// Design Name: +// Module Name: ddr_axi_rd +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr_axi_rd( + input ARESETN, //axi复位 + input ACLK, //axi时钟 + //axi读通道写地址 + output [3:0] M_AXI_ARID , //读地址ID，用来标志一组写信号 + output [31:0] M_AXI_ARADDR , //读地址，给出一次写突发传输的读地址 + output [7:0] M_AXI_ARLEN , //突发长度，给出突发传输的次数 + output [2:0] M_AXI_ARSIZE , //突发大小，给出每次突发传输的字节数 + output [1:0] M_AXI_ARBURST, //突发类型 + output [1:0] M_AXI_ARLOCK , //总线锁信号，可提供操作的原子性 + output [3:0] M_AXI_ARCACHE, //内存类型，表明一次传输是怎样通过系统的 + output [2:0] M_AXI_ARPROT , //保护类型，表明一次传输的特权级及安全等级 + output [3:0] M_AXI_ARQOS , //质量服务QOS + output M_AXI_ARVALID, //有效信号，表明此通道的地址控制信号有效 + input M_AXI_ARREADY, //表明“从”可以接收地址和对应的控制信号 + + //axi读通道读数据 + input [3:0] M_AXI_RID , //读ID tag + input [63:0] M_AXI_RDATA , //读数据 + input [1:0] M_AXI_RRESP , //读响应，表明读传输的状态 + input M_AXI_RLAST , //表明读突发的最后一次传输 + input M_AXI_RVALID, //表明此通道信号有效 + output M_AXI_RREADY, //表明主机能够接收读数据和响应信息 + //用户端fifo接口 + input RD_START , //读突发触发信号 + input [31:0] RD_ADRS , //地址 + input [9:0] RD_LEN , //长度 + output RD_READY , //读空闲 + output RD_FIFO_WE , //连接到读fifo的写使能 + output [63:0] RD_FIFO_DATA, //连接到读fifo的写数据 + output RD_DONE //完成一次突发 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//parameter define +localparam S_RD_IDLE = 3'd0; //读空闲 +localparam S_RA_WAIT = 3'd1; //读地址等待 +localparam S_RA_START = 3'd2; //读地址 +localparam S_RD_WAIT = 3'd3; //读数据等待 +localparam S_RD_PROC = 3'd4; //读数据循环 +localparam S_RD_DONE = 3'd5; //写结束 +//reg define +reg [2:0] rd_state ; //状态寄存器 +reg [31:0] reg_rd_adrs; //地址寄存器 +reg [31:0] reg_rd_len ; //突发长度寄存器 +reg reg_arvalid; //地址有效寄存器 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +assign RD_DONE = (rd_state == S_RD_DONE) ; +assign M_AXI_ARID = 4'b1111;//地址id +assign M_AXI_ARADDR[31:0] = reg_rd_adrs[31:0];//地址 +assign M_AXI_ARLEN[7:0] = RD_LEN-32'd1;//突发长度 +assign M_AXI_ARSIZE[2:0] = 3'b011;//表示AXI总线每个数据宽度是8字节，64位 +assign M_AXI_ARBURST[1:0] = 2'b01;//地址递增方式传输 +assign M_AXI_ARLOCK = 1'b0; +assign M_AXI_ARCACHE[3:0] = 4'b0000; +assign M_AXI_ARPROT[2:0] = 3'b000; +assign M_AXI_ARQOS[3:0] = 4'b0000; +assign M_AXI_ARVALID = reg_arvalid; +assign M_AXI_RREADY = M_AXI_RVALID; +assign RD_READY = (rd_state == S_RD_IDLE)?1'b1:1'b0;//读空闲 +assign RD_FIFO_WE = M_AXI_RVALID;//读fifo的写使能信号 +assign RD_FIFO_DATA[63:0] = M_AXI_RDATA[63:0];//读fifo的写数据信号 + + // 读状态机 + always @(posedge ACLK or negedge ARESETN) begin + if(!ARESETN) begin + rd_state <= S_RD_IDLE; + reg_rd_adrs[31:0] <= 32'd0; + reg_rd_len[31:0] <= 32'd0; + reg_arvalid <= 1'b0; + end else begin + case(rd_state) + S_RD_IDLE: begin//读空闲 + if(RD_START) begin//突发触发信号 + rd_state <= S_RA_WAIT; + reg_rd_adrs[31:0] <= RD_ADRS[31:0]; + reg_rd_len[31:0] <= RD_LEN[9:0] -32'd1; + end + reg_arvalid <= 1'b0; + end + S_RA_WAIT: begin//写地址等待 + rd_state <= S_RA_START; + end + S_RA_START: begin//写地址 + rd_state <= S_RD_WAIT; + reg_arvalid <= 1'b1;//拉高地址有效 + end + S_RD_WAIT: begin //读取数据等待 + if(M_AXI_ARREADY) begin + rd_state <= S_RD_PROC; + reg_arvalid <= 1'b0;//握手成功就拉低 + end + end + S_RD_PROC: begin //接受循环 + if(M_AXI_RVALID) begin //收到数据有效，握手成功 + if(M_AXI_RLAST) begin //收到最后一个数据 + rd_state<= S_RD_DONE; + end + end + end + S_RD_DONE:begin + rd_state <= S_RD_IDLE; + end + endcase + end + end + +endmodule \ No newline at end of file diff --git a/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v b/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v new file mode 100644 index 0000000..90bddf0 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v @@ -0,0 +1,183 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/18 16:15:52 +// Design Name: +// Module Name: ddr_axi_wr +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr_axi_wr( + input ARESETN , //axi复位 + input ACLK , //axi总时钟 +//axi4写通道地址通道 + output [3:0] M_AXI_AWID , //写地址ID，用来标志一组写信号 + output [31:0] M_AXI_AWADDR , //写地址，给出一次写突发传输的写地址 + output [7:0] M_AXI_AWLEN , //突发长度，给出突发传输的次数 + output [2:0] M_AXI_AWSIZE , //突发大小，给出每次突发传输的字节数 + output [1:0] M_AXI_AWBURST, //突发类型 + output M_AXI_AWLOCK , //总线锁信号，可提供操作的原子性 + output [3:0] M_AXI_AWCACHE, //内存类型，表明一次传输是怎样通过系统的 + output [2:0] M_AXI_AWPROT , //保护类型，表明一次传输的特权级及安全等级 + output [3:0] M_AXI_AWQOS , //质量服务QoS + output M_AXI_AWVALID, //有效信号，表明此通道的地址控制信号有效 + input M_AXI_AWREADY, //表明“从”可以接收地址和对应的控制信号 +//axi4写通道数据通道 + output [63:0] M_AXI_WDATA , //写数据 + output [7:0] M_AXI_WSTRB , //写数据有效的字节线 + output M_AXI_WLAST , //表明此次传输是最后一个突发传输 + output M_AXI_WVALID , //写有效，表明此次写有效 + input M_AXI_WREADY , //表明从机可以接收写数据 +//axi4写通道应答通道 + input [3:0] M_AXI_BID , //写响应ID TAG + input [1:0] M_AXI_BRESP , //写响应，表明写传输的状态 + input M_AXI_BVALID , //写响应有效 + output M_AXI_BREADY , //表明主机能够接收写响应 + //用户端信号 + input WR_START , //写突发触发信号 + input [31:0] WR_ADRS , //地址 + input [9:0] WR_LEN , //长度 + output WR_READY , //写空闲 + output WR_FIFO_RE , //连接到写fifo的读使能 + input [63:0] WR_FIFO_DATA , //连接到fifo的读数据 + output WR_DONE //完成一次突发 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +localparam S_WR_IDLE = 3'd0;//写空闲 +localparam S_WA_WAIT = 3'd1;//写地址等待 +localparam S_WA_START = 3'd2;//写地址 +localparam S_WD_WAIT = 3'd3;//写数据等待 +localparam S_WD_PROC = 3'd4;//写数据循环 +localparam S_WR_WAIT = 3'd5;//接受写应答 +localparam S_WR_DONE = 3'd6;//写结束 +//reg define +reg [2:0] wr_state ; //状态寄存器 +reg [31:0] reg_wr_adrs; //地址寄存器 +reg reg_awvalid; //地址有效握手信号 +reg reg_wvalid ; //数据有效握手信号 +reg reg_w_last ; //传输最后一个数据 +reg [7:0] reg_w_len ; //突发长度最大256，实测128最佳 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//写完成信号的写状态完成 +assign WR_DONE = (wr_state == S_WR_DONE); +//写fifo的读使能为axi数据握手成功 +assign WR_FIFO_RE = ((reg_wvalid & M_AXI_WREADY )); +//只有一个主机，可随意设置 +assign M_AXI_AWID = 4'b1111; +//把地址赋予总线 +assign M_AXI_AWADDR[31:0] = reg_wr_adrs[31:0]; +//一次突发传输1长度 +assign M_AXI_AWLEN[7:0] = WR_LEN-'d1; +//表示AXI总线每个数据宽度是8字节，64位 +assign M_AXI_AWSIZE[2:0] = 3'b011; +//01代表地址递增，10代表递减 +assign M_AXI_AWBURST[1:0] = 2'b01; +assign M_AXI_AWLOCK = 1'b0; +assign M_AXI_AWCACHE[3:0] = 4'b0000; +assign M_AXI_AWPROT[2:0] = 3'b000; +assign M_AXI_AWQOS[3:0] = 4'b0000; +//地址握手信号AWVALID +assign M_AXI_AWVALID = reg_awvalid; +//fifo数据赋予总线 +assign M_AXI_WDATA[63:0] = WR_FIFO_DATA[63:0]; +assign M_AXI_WSTRB[7:0] = 8'hFF; +//写到最后一个数据 +assign M_AXI_WLAST =(reg_w_len[7:0] == 8'd0)?'b1:'b0; +//数据握手信号WVALID +assign M_AXI_WVALID = reg_wvalid; +//这个信号是告诉AXI我收到你的应答 +assign M_AXI_BREADY = M_AXI_BVALID; +//axi状态机空闲信号 +assign WR_READY = (wr_state == S_WR_IDLE)?1'b1:1'b0; + +//axi写过程状态机 + always @(posedge ACLK or negedge ARESETN) begin + if(!ARESETN) begin + wr_state <= S_WR_IDLE; + reg_wr_adrs[31:0] <= 32'd0; + reg_awvalid <= 1'b0; + reg_wvalid <= 1'b0; + reg_w_last <= 1'b0; + reg_w_len[7:0] <= 8'd0; + + end else begin + case(wr_state) + S_WR_IDLE: begin //写空闲 + if(WR_START) begin //触发写过程 + wr_state <= S_WA_WAIT; + reg_wr_adrs[31:0] <= WR_ADRS[31:0]; + end + reg_awvalid <= 1'b0; + reg_wvalid <= 1'b0; + reg_w_len[7:0] <= 8'd0; + end + S_WA_WAIT: begin//写地址等待 + wr_state <= S_WA_START;//等待一个周期 + end + S_WA_START: begin + wr_state <= S_WD_WAIT;//写数据等待 + reg_awvalid <= 1'b1; //拉高地址有效信号 + reg_wvalid <= 1'b1;//拉高数据有效信号 + end + S_WD_WAIT: begin + if(M_AXI_AWREADY) begin//等待写地址就绪 + wr_state <= S_WD_PROC; + reg_w_len<=WR_LEN-'d1;//127代表128个长度，0代表1个长度 + reg_awvalid <= 1'b0; + end + end + S_WD_PROC: begin//等待AXI写数据就绪信号 + if(M_AXI_WREADY) begin//拉高了就可以输出fifo使能信号开始读 + + if(reg_w_len[7:0] == 8'd0) begin//完成数据写过程 + wr_state <= S_WR_WAIT; + reg_wvalid <= 1'b0;//此信号拉低，写fifo读使能无效 + reg_w_last<='b1; + //读到最后一个数据，拉高这个标志信号告诉AXI总线这是最后一个 + //如果不拉高传输不会成功 + end + else begin + reg_w_len[7:0] <= reg_w_len[7:0] -8'd1; + end + end + end + S_WR_WAIT: begin//等待写的AXI应答信号 + reg_w_last<='b0; + //M_AXI_BVALID拉高表示写成功，然后状态机完成一次突发传输 + if(M_AXI_BVALID) begin + wr_state <= S_WR_DONE; + end + end + S_WR_DONE: begin //写完成 + wr_state <= S_WR_IDLE; + end + + default: begin + wr_state <= S_WR_IDLE; + end + endcase + end + end + +endmodule diff --git a/ddr_general_design.srcs/sources_1/new/ddr_ctrl.v b/ddr_general_design.srcs/sources_1/new/ddr_ctrl.v new file mode 100644 index 0000000..f6e75df --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/ddr_ctrl.v @@ -0,0 +1,307 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/18 13:49:10 +// Design Name: +// Module Name: ddr_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr_ctrl( + // Inouts + inout [63:0] ddr3_dq, + inout [7:0] ddr3_dqs_n, + inout [7:0] ddr3_dqs_p, + // Outputs + output [15:0] ddr3_addr, + output [2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output ddr3_reset_n, + output [1:0] ddr3_ck_p, + output [1:0] ddr3_ck_n, + output [1:0] ddr3_cke, + output [1:0] ddr3_cs_n, + output [7:0] ddr3_dm, + output [1:0] ddr3_odt, + // Inputs + // Single-ended system clock + input sys_clk_i, + output tg_compare_error, + output init_calib_complete, + // System reset - Default polarity of sys_rst pin is Active Low. + // System reset polarity will change based on the option + // selected in GUI. + input sys_rst + ); + + + //*************************************************************************** + // AXI4 Shim parameters + //*************************************************************************** + localparam C_S_AXI_ID_WIDTH = 4; + // Width of all master and slave ID signals. + // # = >= 1. + localparam C_S_AXI_ADDR_WIDTH = 33; + // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and + // M_AXI_ARADDR for all SI/MI slots. + // # = 32. + localparam C_S_AXI_DATA_WIDTH = 512; + // Width of WDATA and RDATA on SI slot. + // Must be <= APP_DATA_WIDTH. + // # = 32, 64, 128, 256. + localparam C_S_AXI_SUPPORTS_NARROW_BURST = 0; + // Indicates whether to instatiate upsizer + // Range: 0, 1 + + + // Slave Interface Write Address Ports + wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid; + wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr; + wire [7:0] s_axi_awlen; + wire [2:0] s_axi_awsize; + wire [1:0] s_axi_awburst; + wire [0:0] s_axi_awlock; + wire [3:0] s_axi_awcache; + wire [2:0] s_axi_awprot; + wire s_axi_awvalid; + wire s_axi_awready; + // Slave Interface Write Data Ports + wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata; + wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb; + wire s_axi_wlast; + wire s_axi_wvalid; + wire s_axi_wready; + // Slave Interface Write Response Ports + wire s_axi_bready; + wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid; + wire [1:0] s_axi_bresp; + wire s_axi_bvalid; + // Slave Interface Read Address Ports + wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid; + wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr; + wire [7:0] s_axi_arlen; + wire [2:0] s_axi_arsize; + wire [1:0] s_axi_arburst; + wire [0:0] s_axi_arlock; + wire [3:0] s_axi_arcache; + wire [2:0] s_axi_arprot; + wire s_axi_arvalid; + wire s_axi_arready; + // Slave Interface Read Data Ports + wire s_axi_rready; + wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid; + wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata; + wire [1:0] s_axi_rresp; + wire s_axi_rlast; + wire s_axi_rvalid; + + +// output declaration of module ddr_axi_rd +wire [3:0] M_AXI_ARID; +wire [31:0] M_AXI_ARADDR; +wire [7:0] M_AXI_ARLEN; +wire [2:0] M_AXI_ARSIZE; +wire [1:0] M_AXI_ARBURST; +wire [1:0] M_AXI_ARLOCK; +wire [3:0] M_AXI_ARCACHE; +wire [2:0] M_AXI_ARPROT; +wire [3:0] M_AXI_ARQOS; +wire M_AXI_ARVALID; +wire M_AXI_RREADY; +wire RD_READY; +wire RD_FIFO_WE; +wire [63:0] RD_FIFO_DATA; +wire RD_DONE; + +ddr_axi_rd u_ddr_axi_rd( + .ARESETN (ARESETN ), + .ACLK (ACLK ), + .M_AXI_ARID (M_AXI_ARID ), + .M_AXI_ARADDR (M_AXI_ARADDR ), + .M_AXI_ARLEN (M_AXI_ARLEN ), + .M_AXI_ARSIZE (M_AXI_ARSIZE ), + .M_AXI_ARBURST (M_AXI_ARBURST ), + .M_AXI_ARLOCK (M_AXI_ARLOCK ), + .M_AXI_ARCACHE (M_AXI_ARCACHE ), + .M_AXI_ARPROT (M_AXI_ARPROT ), + .M_AXI_ARQOS (M_AXI_ARQOS ), + .M_AXI_ARVALID (M_AXI_ARVALID ), + .M_AXI_ARREADY (M_AXI_ARREADY ), + .M_AXI_RID (M_AXI_RID ), + .M_AXI_RDATA (M_AXI_RDATA ), + .M_AXI_RRESP (M_AXI_RRESP ), + .M_AXI_RLAST (M_AXI_RLAST ), + .M_AXI_RVALID (M_AXI_RVALID ), + .M_AXI_RREADY (M_AXI_RREADY ), + .RD_START (RD_START ), + .RD_ADRS (RD_ADRS ), + .RD_LEN (RD_LEN ), + .RD_READY (RD_READY ), + .RD_FIFO_WE (RD_FIFO_WE ), + .RD_FIFO_DATA (RD_FIFO_DATA ), + .RD_DONE (RD_DONE ) +); + +// output declaration of module ddr_axi_wr +wire [3:0] M_AXI_AWID; +wire [31:0] M_AXI_AWADDR; +wire [7:0] M_AXI_AWLEN; +wire [2:0] M_AXI_AWSIZE; +wire [1:0] M_AXI_AWBURST; +wire M_AXI_AWLOCK; +wire [3:0] M_AXI_AWCACHE; +wire [2:0] M_AXI_AWPROT; +wire [3:0] M_AXI_AWQOS; +wire M_AXI_AWVALID; +wire [63:0] M_AXI_WDATA; +wire [7:0] M_AXI_WSTRB; +wire M_AXI_WLAST; +wire M_AXI_WVALID; +wire M_AXI_BREADY; +wire WR_READY; +wire WR_FIFO_RE; +wire WR_DONE; + +ddr_axi_wr u_ddr_axi_wr( + .ARESETN (ARESETN ), + .ACLK (ACLK ), + .M_AXI_AWID (M_AXI_AWID ), + .M_AXI_AWADDR (M_AXI_AWADDR ), + .M_AXI_AWLEN (M_AXI_AWLEN ), + .M_AXI_AWSIZE (M_AXI_AWSIZE ), + .M_AXI_AWBURST (M_AXI_AWBURST ), + .M_AXI_AWLOCK (M_AXI_AWLOCK ), + .M_AXI_AWCACHE (M_AXI_AWCACHE ), + .M_AXI_AWPROT (M_AXI_AWPROT ), + .M_AXI_AWQOS (M_AXI_AWQOS ), + .M_AXI_AWVALID (M_AXI_AWVALID ), + .M_AXI_AWREADY (M_AXI_AWREADY ), + .M_AXI_WDATA (M_AXI_WDATA ), + .M_AXI_WSTRB (M_AXI_WSTRB ), + .M_AXI_WLAST (M_AXI_WLAST ), + .M_AXI_WVALID (M_AXI_WVALID ), + .M_AXI_WREADY (M_AXI_WREADY ), + .M_AXI_BID (M_AXI_BID ), + .M_AXI_BRESP (M_AXI_BRESP ), + .M_AXI_BVALID (M_AXI_BVALID ), + .M_AXI_BREADY (M_AXI_BREADY ), + .WR_START (WR_START ), + .WR_ADRS (WR_ADRS ), + .WR_LEN (WR_LEN ), + .WR_READY (WR_READY ), + .WR_FIFO_RE (WR_FIFO_RE ), + .WR_FIFO_DATA (WR_FIFO_DATA ), + .WR_DONE (WR_DONE ) +); + + + + + + ddr3_mig u_ddr3_mig( +// Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + + .ddr3_reset_n (ddr3_reset_n), + .init_calib_complete (init_calib_complete), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + +// Application interface ports + .ui_clk (clk), + .ui_clk_sync_rst (rst), + .mmcm_locked (mmcm_locked), + .aresetn (aresetn), + .app_sr_req (1'b0), + .app_ref_req (1'b0), + .app_zq_req (1'b0), + .app_sr_active (app_sr_active), + .app_ref_ack (app_ref_ack), + .app_zq_ack (app_zq_ack), + +// Slave Interface Write Address Ports + .s_axi_awid (s_axi_awid), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awlen (s_axi_awlen), + .s_axi_awsize (s_axi_awsize), + .s_axi_awburst (s_axi_awburst), + .s_axi_awlock (s_axi_awlock), + .s_axi_awcache (s_axi_awcache), + .s_axi_awprot (s_axi_awprot), + .s_axi_awqos (4'h0), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + + +// Slave Interface Write Data Ports + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wlast (s_axi_wlast), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + + +// Slave Interface Write Response Ports + .s_axi_bid (s_axi_bid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + + +// Slave Interface Read Address Ports + .s_axi_arid (s_axi_arid), + .s_axi_araddr (s_axi_araddr), + .s_axi_arlen (s_axi_arlen), + .s_axi_arsize (s_axi_arsize), + .s_axi_arburst (s_axi_arburst), + .s_axi_arlock (s_axi_arlock), + .s_axi_arcache (s_axi_arcache), + .s_axi_arprot (s_axi_arprot), + .s_axi_arqos (4'h0), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + + +// Slave Interface Read Data Ports + .s_axi_rid (s_axi_rid), + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rlast (s_axi_rlast), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + +// System Clock Ports + .sys_clk_i (sys_clk_i), + .device_temp (device_temp), + .sys_rst (sys_rst) + +); + +endmodule diff --git a/ddr_general_design.xpr b/ddr_general_design.xpr index 4438490..8794a46 100644 --- a/ddr_general_design.xpr +++ b/ddr_general_design.xpr @@ -3,7 +3,7 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -86,6 +138,8 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -128,6 +224,40 @@ + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + @@ -145,6 +275,61 @@ + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + 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