FPGALab/ddr3_general_design
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UnbalancedCat cf3f100d53 redo axi construction
2025-03-18 16:56:47 +08:00
ddr_general_design.srcs/sources_1
redo axi construction
2025-03-18 16:56:47 +08:00
others
redo axi construction
2025-03-18 16:56:47 +08:00
.gitignore
fix gitignore
2025-03-18 12:13:58 +08:00
ddr_general_design.xpr
redo axi construction
2025-03-18 16:56:47 +08:00
Description
基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板
59 MiB
Languages
Verilog 100%