`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/03/18 13:49:10
// Design Name: 
// Module Name: ddr_ctrl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ddr_ctrl(
    // Inouts
   inout [63:0]                         ddr3_dq,
   inout [7:0]                          ddr3_dqs_n,
   inout [7:0]                          ddr3_dqs_p,
   // Outputs
   output [15:0]                        ddr3_addr,
   output [2:0]                         ddr3_ba,
   output                               ddr3_cas_n,
   output                               ddr3_ras_n,
   output                               ddr3_we_n,
   output                               ddr3_reset_n,
   output [1:0]                         ddr3_ck_p,
   output [1:0]                         ddr3_ck_n,
   output [1:0]                         ddr3_cke,
   output [1:0]                         ddr3_cs_n,
   output [7:0]                         ddr3_dm,
   output [1:0]                         ddr3_odt,
   // Inputs
   // Single-ended system clock
   input                                sys_clk_i,
   output                               tg_compare_error,
   output                               init_calib_complete,
   // System reset - Default polarity of sys_rst pin is Active Low.
   // System reset polarity will change based on the option 
   // selected in GUI.
   input                                sys_rst
    );

    
   //***************************************************************************
   // AXI4 Shim parameters
   //***************************************************************************
    localparam C_S_AXI_ID_WIDTH              = 4;
                                               // Width of all master and slave ID signals.
                                               // # = >= 1.
    localparam C_S_AXI_ADDR_WIDTH            = 33;
                                               // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
                                               // M_AXI_ARADDR for all SI/MI slots.
                                               // # = 32.
    localparam C_S_AXI_DATA_WIDTH            = 512;
                                               // Width of WDATA and RDATA on SI slot.
                                               // Must be <= APP_DATA_WIDTH.
                                               // # = 32, 64, 128, 256.
    localparam C_S_AXI_SUPPORTS_NARROW_BURST = 0;
                                               // Indicates whether to instatiate upsizer
                                               // Range: 0, 1

    
    // Slave Interface Write Address Ports
    wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_awid;
    wire [C_S_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr;
    wire [7:0]                        s_axi_awlen;
    wire [2:0]                        s_axi_awsize;
    wire [1:0]                        s_axi_awburst;
    wire [0:0]                        s_axi_awlock;
    wire [3:0]                        s_axi_awcache;
    wire [2:0]                        s_axi_awprot;
    wire                              s_axi_awvalid;
    wire                              s_axi_awready;
    // Slave Interface Write Data Ports
    wire [C_S_AXI_DATA_WIDTH-1:0]     s_axi_wdata;
    wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb;
    wire                              s_axi_wlast;
    wire                              s_axi_wvalid;
    wire                              s_axi_wready;
    // Slave Interface Write Response Ports
    wire                              s_axi_bready;
    wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_bid;
    wire [1:0]                        s_axi_bresp;
    wire                              s_axi_bvalid;
    // Slave Interface Read Address Ports
    wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_arid;
    wire [C_S_AXI_ADDR_WIDTH-1:0]     s_axi_araddr;
    wire [7:0]                        s_axi_arlen;
    wire [2:0]                        s_axi_arsize;
    wire [1:0]                        s_axi_arburst;
    wire [0:0]                        s_axi_arlock;
    wire [3:0]                        s_axi_arcache;
    wire [2:0]                        s_axi_arprot;
    wire                              s_axi_arvalid;
    wire                              s_axi_arready;
    // Slave Interface Read Data Ports
    wire                              s_axi_rready;
    wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_rid;
    wire [C_S_AXI_DATA_WIDTH-1:0]     s_axi_rdata;
    wire [1:0]                        s_axi_rresp;
    wire                              s_axi_rlast;
    wire                              s_axi_rvalid;


// output declaration of module ddr_axi_rd
wire [3:0] M_AXI_ARID;
wire [31:0] M_AXI_ARADDR;
wire [7:0] M_AXI_ARLEN;
wire [2:0] M_AXI_ARSIZE;
wire [1:0] M_AXI_ARBURST;
wire [1:0] M_AXI_ARLOCK;
wire [3:0] M_AXI_ARCACHE;
wire [2:0] M_AXI_ARPROT;
wire [3:0] M_AXI_ARQOS;
wire M_AXI_ARVALID;
wire M_AXI_RREADY;
wire RD_READY;
wire RD_FIFO_WE;
wire [63:0] RD_FIFO_DATA;
wire RD_DONE;

ddr_axi_rd u_ddr_axi_rd(
       .ARESETN       	(ARESETN        ),
       .ACLK          	(ACLK           ),
       .M_AXI_ARID    	(M_AXI_ARID     ),
       .M_AXI_ARADDR  	(M_AXI_ARADDR   ),
       .M_AXI_ARLEN   	(M_AXI_ARLEN    ),
       .M_AXI_ARSIZE  	(M_AXI_ARSIZE   ),
       .M_AXI_ARBURST 	(M_AXI_ARBURST  ),
       .M_AXI_ARLOCK  	(M_AXI_ARLOCK   ),
       .M_AXI_ARCACHE 	(M_AXI_ARCACHE  ),
       .M_AXI_ARPROT  	(M_AXI_ARPROT   ),
       .M_AXI_ARQOS   	(M_AXI_ARQOS    ),
       .M_AXI_ARVALID 	(M_AXI_ARVALID  ),
       .M_AXI_ARREADY 	(M_AXI_ARREADY  ),
       .M_AXI_RID     	(M_AXI_RID      ),
       .M_AXI_RDATA   	(M_AXI_RDATA    ),
       .M_AXI_RRESP   	(M_AXI_RRESP    ),
       .M_AXI_RLAST   	(M_AXI_RLAST    ),
       .M_AXI_RVALID  	(M_AXI_RVALID   ),
       .M_AXI_RREADY  	(M_AXI_RREADY   ),
       .RD_START      	(RD_START       ),
       .RD_ADRS       	(RD_ADRS        ),
       .RD_LEN        	(RD_LEN         ),
       .RD_READY      	(RD_READY       ),
       .RD_FIFO_WE    	(RD_FIFO_WE     ),
       .RD_FIFO_DATA  	(RD_FIFO_DATA   ),
       .RD_DONE       	(RD_DONE        )
);

// output declaration of module ddr_axi_wr
wire [3:0] M_AXI_AWID;
wire [31:0] M_AXI_AWADDR;
wire [7:0] M_AXI_AWLEN;
wire [2:0] M_AXI_AWSIZE;
wire [1:0] M_AXI_AWBURST;
wire M_AXI_AWLOCK;
wire [3:0] M_AXI_AWCACHE;
wire [2:0] M_AXI_AWPROT;
wire [3:0] M_AXI_AWQOS;
wire M_AXI_AWVALID;
wire [63:0] M_AXI_WDATA;
wire [7:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire M_AXI_WVALID;
wire M_AXI_BREADY;
wire WR_READY;
wire WR_FIFO_RE;
wire WR_DONE;

ddr_axi_wr u_ddr_axi_wr(
       .ARESETN       	(ARESETN        ),
       .ACLK          	(ACLK           ),
       .M_AXI_AWID    	(M_AXI_AWID     ),
       .M_AXI_AWADDR  	(M_AXI_AWADDR   ),
       .M_AXI_AWLEN   	(M_AXI_AWLEN    ),
       .M_AXI_AWSIZE  	(M_AXI_AWSIZE   ),
       .M_AXI_AWBURST 	(M_AXI_AWBURST  ),
       .M_AXI_AWLOCK  	(M_AXI_AWLOCK   ),
       .M_AXI_AWCACHE 	(M_AXI_AWCACHE  ),
       .M_AXI_AWPROT  	(M_AXI_AWPROT   ),
       .M_AXI_AWQOS   	(M_AXI_AWQOS    ),
       .M_AXI_AWVALID 	(M_AXI_AWVALID  ),
       .M_AXI_AWREADY 	(M_AXI_AWREADY  ),
       .M_AXI_WDATA   	(M_AXI_WDATA    ),
       .M_AXI_WSTRB   	(M_AXI_WSTRB    ),
       .M_AXI_WLAST   	(M_AXI_WLAST    ),
       .M_AXI_WVALID  	(M_AXI_WVALID   ),
       .M_AXI_WREADY  	(M_AXI_WREADY   ),
       .M_AXI_BID     	(M_AXI_BID      ),
       .M_AXI_BRESP   	(M_AXI_BRESP    ),
       .M_AXI_BVALID  	(M_AXI_BVALID   ),
       .M_AXI_BREADY  	(M_AXI_BREADY   ),
       .WR_START      	(WR_START       ),
       .WR_ADRS       	(WR_ADRS        ),
       .WR_LEN        	(WR_LEN         ),
       .WR_READY      	(WR_READY       ),
       .WR_FIFO_RE    	(WR_FIFO_RE     ),
       .WR_FIFO_DATA  	(WR_FIFO_DATA   ),
       .WR_DONE       	(WR_DONE        )
);





  ddr3_mig u_ddr3_mig(
// Memory interface ports
       .ddr3_addr                      (ddr3_addr),
       .ddr3_ba                        (ddr3_ba),
       .ddr3_cas_n                     (ddr3_cas_n),
       .ddr3_ck_n                      (ddr3_ck_n),
       .ddr3_ck_p                      (ddr3_ck_p),
       .ddr3_cke                       (ddr3_cke),
       .ddr3_ras_n                     (ddr3_ras_n),
       .ddr3_we_n                      (ddr3_we_n),
       .ddr3_dq                        (ddr3_dq),
       .ddr3_dqs_n                     (ddr3_dqs_n),
       .ddr3_dqs_p                     (ddr3_dqs_p),

       .ddr3_reset_n                   (ddr3_reset_n),
       .init_calib_complete            (init_calib_complete),
       
       .ddr3_cs_n                      (ddr3_cs_n),
       .ddr3_dm                        (ddr3_dm),
       .ddr3_odt                       (ddr3_odt),

// Application interface ports
       .ui_clk                         (clk),
       .ui_clk_sync_rst                (rst),
       .mmcm_locked                    (mmcm_locked),
       .aresetn                        (aresetn),
       .app_sr_req                     (1'b0),
       .app_ref_req                    (1'b0),
       .app_zq_req                     (1'b0),
       .app_sr_active                  (app_sr_active),
       .app_ref_ack                    (app_ref_ack),
       .app_zq_ack                     (app_zq_ack),

// Slave Interface Write Address Ports
       .s_axi_awid                     (s_axi_awid),
       .s_axi_awaddr                   (s_axi_awaddr),
       .s_axi_awlen                    (s_axi_awlen),
       .s_axi_awsize                   (s_axi_awsize),
       .s_axi_awburst                  (s_axi_awburst),
       .s_axi_awlock                   (s_axi_awlock), 
       .s_axi_awcache                  (s_axi_awcache),
       .s_axi_awprot                   (s_axi_awprot), 
       .s_axi_awqos                    (4'h0),         
       .s_axi_awvalid                  (s_axi_awvalid),
       .s_axi_awready                  (s_axi_awready),


// Slave Interface Write Data Ports
       .s_axi_wdata                    (s_axi_wdata),
       .s_axi_wstrb                    (s_axi_wstrb),
       .s_axi_wlast                    (s_axi_wlast),
       .s_axi_wvalid                   (s_axi_wvalid),
       .s_axi_wready                   (s_axi_wready),


// Slave Interface Write Response Ports
       .s_axi_bid                      (s_axi_bid),
       .s_axi_bresp                    (s_axi_bresp),
       .s_axi_bvalid                   (s_axi_bvalid),
       .s_axi_bready                   (s_axi_bready),


// Slave Interface Read Address Ports
       .s_axi_arid                     (s_axi_arid),
       .s_axi_araddr                   (s_axi_araddr),
       .s_axi_arlen                    (s_axi_arlen),
       .s_axi_arsize                   (s_axi_arsize),
       .s_axi_arburst                  (s_axi_arburst),
       .s_axi_arlock                   (s_axi_arlock),  
       .s_axi_arcache                  (s_axi_arcache), 
       .s_axi_arprot                   (s_axi_arprot),  
       .s_axi_arqos                    (4'h0),          
       .s_axi_arvalid                  (s_axi_arvalid),
       .s_axi_arready                  (s_axi_arready),


// Slave Interface Read Data Ports
       .s_axi_rid                      (s_axi_rid),
       .s_axi_rdata                    (s_axi_rdata),
       .s_axi_rresp                    (s_axi_rresp),
       .s_axi_rlast                    (s_axi_rlast),
       .s_axi_rvalid                   (s_axi_rvalid),
       .s_axi_rready                   (s_axi_rready),

// System Clock Ports
       .sys_clk_i                       (sys_clk_i),
       .device_temp                     (device_temp),
       .sys_rst                         (sys_rst)

);

endmodule
