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redo axi construction

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包焕垲
2025-03-18 16:56:47 +08:00
parent 5dd963dd12
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ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/18 16:15:52
// Design Name:
// Module Name: ddr_axi_rd
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_axi_rd(
input ARESETN, //axi复位
input ACLK, //axi时钟
//axi读通道写地址
output [3:0] M_AXI_ARID , //读地址ID，用来标志一组写信号
output [31:0] M_AXI_ARADDR , //读地址，给出一次写突发传输的读地址
output [7:0] M_AXI_ARLEN , //突发长度，给出突发传输的次数
output [2:0] M_AXI_ARSIZE , //突发大小，给出每次突发传输的字节数
output [1:0] M_AXI_ARBURST, //突发类型
output [1:0] M_AXI_ARLOCK , //总线锁信号，可提供操作的原子性
output [3:0] M_AXI_ARCACHE, //内存类型，表明一次传输是怎样通过系统的
output [2:0] M_AXI_ARPROT , //保护类型，表明一次传输的特权级及安全等级
output [3:0] M_AXI_ARQOS , //质量服务QOS
output M_AXI_ARVALID, //有效信号，表明此通道的地址控制信号有效
input M_AXI_ARREADY, //表明“从”可以接收地址和对应的控制信号
//axi读通道读数据
input [3:0] M_AXI_RID , //读ID tag
input [63:0] M_AXI_RDATA , //读数据
input [1:0] M_AXI_RRESP , //读响应，表明读传输的状态
input M_AXI_RLAST , //表明读突发的最后一次传输
input M_AXI_RVALID, //表明此通道信号有效
output M_AXI_RREADY, //表明主机能够接收读数据和响应信息
//用户端fifo接口
input RD_START , //读突发触发信号
input [31:0] RD_ADRS , //地址
input [9:0] RD_LEN , //长度
output RD_READY , //读空闲
output RD_FIFO_WE , //连接到读fifo的写使能
output [63:0] RD_FIFO_DATA, //连接到读fifo的写数据
output RD_DONE //完成一次突发
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
localparam S_RD_IDLE = 3'd0; //读空闲
localparam S_RA_WAIT = 3'd1; //读地址等待
localparam S_RA_START = 3'd2; //读地址
localparam S_RD_WAIT = 3'd3; //读数据等待
localparam S_RD_PROC = 3'd4; //读数据循环
localparam S_RD_DONE = 3'd5; //写结束
//reg define
reg [2:0] rd_state ; //状态寄存器
reg [31:0] reg_rd_adrs; //地址寄存器
reg [31:0] reg_rd_len ; //突发长度寄存器
reg reg_arvalid; //地址有效寄存器
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
assign RD_DONE = (rd_state == S_RD_DONE) ;
assign M_AXI_ARID = 4'b1111;//地址id
assign M_AXI_ARADDR[31:0] = reg_rd_adrs[31:0];//地址
assign M_AXI_ARLEN[7:0] = RD_LEN-32'd1;//突发长度
assign M_AXI_ARSIZE[2:0] = 3'b011;//表示AXI总线每个数据宽度是8字节，64位
assign M_AXI_ARBURST[1:0] = 2'b01;//地址递增方式传输
assign M_AXI_ARLOCK = 1'b0;
assign M_AXI_ARCACHE[3:0] = 4'b0000;
assign M_AXI_ARPROT[2:0] = 3'b000;
assign M_AXI_ARQOS[3:0] = 4'b0000;
assign M_AXI_ARVALID = reg_arvalid;
assign M_AXI_RREADY = M_AXI_RVALID;
assign RD_READY = (rd_state == S_RD_IDLE)?1'b1:1'b0;//读空闲
assign RD_FIFO_WE = M_AXI_RVALID;//读fifo的写使能信号
assign RD_FIFO_DATA[63:0] = M_AXI_RDATA[63:0];//读fifo的写数据信号
// 读状态机
always @(posedge ACLK or negedge ARESETN) begin
if(!ARESETN) begin
rd_state <= S_RD_IDLE;
reg_rd_adrs[31:0] <= 32'd0;
reg_rd_len[31:0] <= 32'd0;
reg_arvalid <= 1'b0;
end else begin
case(rd_state)
S_RD_IDLE: begin//读空闲
if(RD_START) begin//突发触发信号
rd_state <= S_RA_WAIT;
reg_rd_adrs[31:0] <= RD_ADRS[31:0];
reg_rd_len[31:0] <= RD_LEN[9:0] -32'd1;
end
reg_arvalid <= 1'b0;
end
S_RA_WAIT: begin//写地址等待
rd_state <= S_RA_START;
end
S_RA_START: begin//写地址
rd_state <= S_RD_WAIT;
reg_arvalid <= 1'b1;//拉高地址有效
end
S_RD_WAIT: begin //读取数据等待
if(M_AXI_ARREADY) begin
rd_state <= S_RD_PROC;
reg_arvalid <= 1'b0;//握手成功就拉低
end
end
S_RD_PROC: begin //接受循环
if(M_AXI_RVALID) begin //收到数据有效，握手成功
if(M_AXI_RLAST) begin //收到最后一个数据
rd_state<= S_RD_DONE;
end
end
end
S_RD_DONE:begin
rd_state <= S_RD_IDLE;
end
endcase
end
end
endmodule

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ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/18 16:15:52
// Design Name:
// Module Name: ddr_axi_wr
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_axi_wr(
input ARESETN , //axi复位
input ACLK , //axi总时钟
//axi4写通道地址通道
output [3:0] M_AXI_AWID , //写地址ID，用来标志一组写信号
output [31:0] M_AXI_AWADDR , //写地址，给出一次写突发传输的写地址
output [7:0] M_AXI_AWLEN , //突发长度，给出突发传输的次数
output [2:0] M_AXI_AWSIZE , //突发大小，给出每次突发传输的字节数
output [1:0] M_AXI_AWBURST, //突发类型
output M_AXI_AWLOCK , //总线锁信号，可提供操作的原子性
output [3:0] M_AXI_AWCACHE, //内存类型，表明一次传输是怎样通过系统的
output [2:0] M_AXI_AWPROT , //保护类型，表明一次传输的特权级及安全等级
output [3:0] M_AXI_AWQOS , //质量服务QoS
output M_AXI_AWVALID, //有效信号，表明此通道的地址控制信号有效
input M_AXI_AWREADY, //表明“从”可以接收地址和对应的控制信号
//axi4写通道数据通道
output [63:0] M_AXI_WDATA , //写数据
output [7:0] M_AXI_WSTRB , //写数据有效的字节线
output M_AXI_WLAST , //表明此次传输是最后一个突发传输
output M_AXI_WVALID , //写有效，表明此次写有效
input M_AXI_WREADY , //表明从机可以接收写数据
//axi4写通道应答通道
input [3:0] M_AXI_BID , //写响应ID TAG
input [1:0] M_AXI_BRESP , //写响应，表明写传输的状态
input M_AXI_BVALID , //写响应有效
output M_AXI_BREADY , //表明主机能够接收写响应
//用户端信号
input WR_START , //写突发触发信号
input [31:0] WR_ADRS , //地址
input [9:0] WR_LEN , //长度
output WR_READY , //写空闲
output WR_FIFO_RE , //连接到写fifo的读使能
input [63:0] WR_FIFO_DATA , //连接到fifo的读数据
output WR_DONE //完成一次突发
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
localparam S_WR_IDLE = 3'd0;//写空闲
localparam S_WA_WAIT = 3'd1;//写地址等待
localparam S_WA_START = 3'd2;//写地址
localparam S_WD_WAIT = 3'd3;//写数据等待
localparam S_WD_PROC = 3'd4;//写数据循环
localparam S_WR_WAIT = 3'd5;//接受写应答
localparam S_WR_DONE = 3'd6;//写结束
//reg define
reg [2:0] wr_state ; //状态寄存器
reg [31:0] reg_wr_adrs; //地址寄存器
reg reg_awvalid; //地址有效握手信号
reg reg_wvalid ; //数据有效握手信号
reg reg_w_last ; //传输最后一个数据
reg [7:0] reg_w_len ; //突发长度最大256，实测128最佳
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//写完成信号的写状态完成
assign WR_DONE = (wr_state == S_WR_DONE);
//写fifo的读使能为axi数据握手成功
assign WR_FIFO_RE = ((reg_wvalid & M_AXI_WREADY ));
//只有一个主机，可随意设置
assign M_AXI_AWID = 4'b1111;
//把地址赋予总线
assign M_AXI_AWADDR[31:0] = reg_wr_adrs[31:0];
//一次突发传输1长度
assign M_AXI_AWLEN[7:0] = WR_LEN-'d1;
//表示AXI总线每个数据宽度是8字节，64位
assign M_AXI_AWSIZE[2:0] = 3'b011;
//01代表地址递增，10代表递减
assign M_AXI_AWBURST[1:0] = 2'b01;
assign M_AXI_AWLOCK = 1'b0;
assign M_AXI_AWCACHE[3:0] = 4'b0000;
assign M_AXI_AWPROT[2:0] = 3'b000;
assign M_AXI_AWQOS[3:0] = 4'b0000;
//地址握手信号AWVALID
assign M_AXI_AWVALID = reg_awvalid;
//fifo数据赋予总线
assign M_AXI_WDATA[63:0] = WR_FIFO_DATA[63:0];
assign M_AXI_WSTRB[7:0] = 8'hFF;
//写到最后一个数据
assign M_AXI_WLAST =(reg_w_len[7:0] == 8'd0)?'b1:'b0;
//数据握手信号WVALID
assign M_AXI_WVALID = reg_wvalid;
//这个信号是告诉AXI我收到你的应答
assign M_AXI_BREADY = M_AXI_BVALID;
//axi状态机空闲信号
assign WR_READY = (wr_state == S_WR_IDLE)?1'b1:1'b0;
//axi写过程状态机
always @(posedge ACLK or negedge ARESETN) begin
if(!ARESETN) begin
wr_state <= S_WR_IDLE;
reg_wr_adrs[31:0] <= 32'd0;
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b0;
reg_w_last <= 1'b0;
reg_w_len[7:0] <= 8'd0;
end else begin
case(wr_state)
S_WR_IDLE: begin //写空闲
if(WR_START) begin //触发写过程
wr_state <= S_WA_WAIT;
reg_wr_adrs[31:0] <= WR_ADRS[31:0];
end
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b0;
reg_w_len[7:0] <= 8'd0;
end
S_WA_WAIT: begin//写地址等待
wr_state <= S_WA_START;//等待一个周期
end
S_WA_START: begin
wr_state <= S_WD_WAIT;//写数据等待
reg_awvalid <= 1'b1; //拉高地址有效信号
reg_wvalid <= 1'b1;//拉高数据有效信号
end
S_WD_WAIT: begin
if(M_AXI_AWREADY) begin//等待写地址就绪
wr_state <= S_WD_PROC;
reg_w_len<=WR_LEN-'d1;//127代表128个长度，0代表1个长度
reg_awvalid <= 1'b0;
end
end
S_WD_PROC: begin//等待AXI写数据就绪信号
if(M_AXI_WREADY) begin//拉高了就可以输出fifo使能信号开始读
if(reg_w_len[7:0] == 8'd0) begin//完成数据写过程
wr_state <= S_WR_WAIT;
reg_wvalid <= 1'b0;//此信号拉低，写fifo读使能无效
reg_w_last<='b1;
//读到最后一个数据，拉高这个标志信号告诉AXI总线这是最后一个
//如果不拉高传输不会成功
end
else begin
reg_w_len[7:0] <= reg_w_len[7:0] -8'd1;
end
end
end
S_WR_WAIT: begin//等待写的AXI应答信号
reg_w_last<='b0;
//M_AXI_BVALID拉高表示写成功，然后状态机完成一次突发传输
if(M_AXI_BVALID) begin
wr_state <= S_WR_DONE;
end
end
S_WR_DONE: begin //写完成
wr_state <= S_WR_IDLE;
end
default: begin
wr_state <= S_WR_IDLE;
end
endcase
end
end
endmodule

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ddr_general_design.srcs/sources_1/new/ddr_ctrl.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/18 13:49:10
// Design Name:
// Module Name: ddr_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_ctrl(
// Inouts
inout [63:0] ddr3_dq,
inout [7:0] ddr3_dqs_n,
inout [7:0] ddr3_dqs_p,
// Outputs
output [15:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_cas_n,
output ddr3_ras_n,
output ddr3_we_n,
output ddr3_reset_n,
output [1:0] ddr3_ck_p,
output [1:0] ddr3_ck_n,
output [1:0] ddr3_cke,
output [1:0] ddr3_cs_n,
output [7:0] ddr3_dm,
output [1:0] ddr3_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
output tg_compare_error,
output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
localparam C_S_AXI_ID_WIDTH = 4;
// Width of all master and slave ID signals.
// # = >= 1.
localparam C_S_AXI_ADDR_WIDTH = 33;
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
localparam C_S_AXI_DATA_WIDTH = 512;
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
localparam C_S_AXI_SUPPORTS_NARROW_BURST = 0;
// Indicates whether to instatiate upsizer
// Range: 0, 1
// Slave Interface Write Address Ports
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid;
wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr;
wire [7:0] s_axi_awlen;
wire [2:0] s_axi_awsize;
wire [1:0] s_axi_awburst;
wire [0:0] s_axi_awlock;
wire [3:0] s_axi_awcache;
wire [2:0] s_axi_awprot;
wire s_axi_awvalid;
wire s_axi_awready;
// Slave Interface Write Data Ports
wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb;
wire s_axi_wlast;
wire s_axi_wvalid;
wire s_axi_wready;
// Slave Interface Write Response Ports
wire s_axi_bready;
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
// Slave Interface Read Address Ports
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid;
wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr;
wire [7:0] s_axi_arlen;
wire [2:0] s_axi_arsize;
wire [1:0] s_axi_arburst;
wire [0:0] s_axi_arlock;
wire [3:0] s_axi_arcache;
wire [2:0] s_axi_arprot;
wire s_axi_arvalid;
wire s_axi_arready;
// Slave Interface Read Data Ports
wire s_axi_rready;
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid;
wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rlast;
wire s_axi_rvalid;
// output declaration of module ddr_axi_rd
wire [3:0] M_AXI_ARID;
wire [31:0] M_AXI_ARADDR;
wire [7:0] M_AXI_ARLEN;
wire [2:0] M_AXI_ARSIZE;
wire [1:0] M_AXI_ARBURST;
wire [1:0] M_AXI_ARLOCK;
wire [3:0] M_AXI_ARCACHE;
wire [2:0] M_AXI_ARPROT;
wire [3:0] M_AXI_ARQOS;
wire M_AXI_ARVALID;
wire M_AXI_RREADY;
wire RD_READY;
wire RD_FIFO_WE;
wire [63:0] RD_FIFO_DATA;
wire RD_DONE;
ddr_axi_rd u_ddr_axi_rd(
.ARESETN (ARESETN ),
.ACLK (ACLK ),
.M_AXI_ARID (M_AXI_ARID ),
.M_AXI_ARADDR (M_AXI_ARADDR ),
.M_AXI_ARLEN (M_AXI_ARLEN ),
.M_AXI_ARSIZE (M_AXI_ARSIZE ),
.M_AXI_ARBURST (M_AXI_ARBURST ),
.M_AXI_ARLOCK (M_AXI_ARLOCK ),
.M_AXI_ARCACHE (M_AXI_ARCACHE ),
.M_AXI_ARPROT (M_AXI_ARPROT ),
.M_AXI_ARQOS (M_AXI_ARQOS ),
.M_AXI_ARVALID (M_AXI_ARVALID ),
.M_AXI_ARREADY (M_AXI_ARREADY ),
.M_AXI_RID (M_AXI_RID ),
.M_AXI_RDATA (M_AXI_RDATA ),
.M_AXI_RRESP (M_AXI_RRESP ),
.M_AXI_RLAST (M_AXI_RLAST ),
.M_AXI_RVALID (M_AXI_RVALID ),
.M_AXI_RREADY (M_AXI_RREADY ),
.RD_START (RD_START ),
.RD_ADRS (RD_ADRS ),
.RD_LEN (RD_LEN ),
.RD_READY (RD_READY ),
.RD_FIFO_WE (RD_FIFO_WE ),
.RD_FIFO_DATA (RD_FIFO_DATA ),
.RD_DONE (RD_DONE )
);
// output declaration of module ddr_axi_wr
wire [3:0] M_AXI_AWID;
wire [31:0] M_AXI_AWADDR;
wire [7:0] M_AXI_AWLEN;
wire [2:0] M_AXI_AWSIZE;
wire [1:0] M_AXI_AWBURST;
wire M_AXI_AWLOCK;
wire [3:0] M_AXI_AWCACHE;
wire [2:0] M_AXI_AWPROT;
wire [3:0] M_AXI_AWQOS;
wire M_AXI_AWVALID;
wire [63:0] M_AXI_WDATA;
wire [7:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire M_AXI_WVALID;
wire M_AXI_BREADY;
wire WR_READY;
wire WR_FIFO_RE;
wire WR_DONE;
ddr_axi_wr u_ddr_axi_wr(
.ARESETN (ARESETN ),
.ACLK (ACLK ),
.M_AXI_AWID (M_AXI_AWID ),
.M_AXI_AWADDR (M_AXI_AWADDR ),
.M_AXI_AWLEN (M_AXI_AWLEN ),
.M_AXI_AWSIZE (M_AXI_AWSIZE ),
.M_AXI_AWBURST (M_AXI_AWBURST ),
.M_AXI_AWLOCK (M_AXI_AWLOCK ),
.M_AXI_AWCACHE (M_AXI_AWCACHE ),
.M_AXI_AWPROT (M_AXI_AWPROT ),
.M_AXI_AWQOS (M_AXI_AWQOS ),
.M_AXI_AWVALID (M_AXI_AWVALID ),
.M_AXI_AWREADY (M_AXI_AWREADY ),
.M_AXI_WDATA (M_AXI_WDATA ),
.M_AXI_WSTRB (M_AXI_WSTRB ),
.M_AXI_WLAST (M_AXI_WLAST ),
.M_AXI_WVALID (M_AXI_WVALID ),
.M_AXI_WREADY (M_AXI_WREADY ),
.M_AXI_BID (M_AXI_BID ),
.M_AXI_BRESP (M_AXI_BRESP ),
.M_AXI_BVALID (M_AXI_BVALID ),
.M_AXI_BREADY (M_AXI_BREADY ),
.WR_START (WR_START ),
.WR_ADRS (WR_ADRS ),
.WR_LEN (WR_LEN ),
.WR_READY (WR_READY ),
.WR_FIFO_RE (WR_FIFO_RE ),
.WR_FIFO_DATA (WR_FIFO_DATA ),
.WR_DONE (WR_DONE )
);
ddr3_mig u_ddr3_mig(
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_reset_n (ddr3_reset_n),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.ui_clk (clk),
.ui_clk_sync_rst (rst),
.mmcm_locked (mmcm_locked),
.aresetn (aresetn),
.app_sr_req (1'b0),
.app_ref_req (1'b0),
.app_zq_req (1'b0),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (4'h0),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (4'h0),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// System Clock Ports
.sys_clk_i (sys_clk_i),
.device_temp (device_temp),
.sys_rst (sys_rst)
);
endmodule