sync
This commit is contained in:
@@ -36,13 +36,13 @@
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="13"/>
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<Option Name="WTModelSimExportSim" Val="13"/>
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<Option Name="WTQuestaExportSim" Val="13"/>
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<Option Name="WTIesExportSim" Val="13"/>
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<Option Name="WTVcsExportSim" Val="13"/>
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<Option Name="WTRivieraExportSim" Val="13"/>
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<Option Name="WTActivehdlExportSim" Val="13"/>
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<Option Name="WTXSimExportSim" Val="22"/>
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<Option Name="WTModelSimExportSim" Val="22"/>
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<Option Name="WTQuestaExportSim" Val="22"/>
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<Option Name="WTIesExportSim" Val="22"/>
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<Option Name="WTVcsExportSim" Val="22"/>
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<Option Name="WTRivieraExportSim" Val="22"/>
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<Option Name="WTActivehdlExportSim" Val="22"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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@@ -58,8 +58,30 @@
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/new/axi_m_rd.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/axi_m_wr.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/axi_ddr_top.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/pcie_ddr/pcie_ddr.bd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@@ -67,6 +89,7 @@
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</File>
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<File Path="$PSRCDIR/sources_1/bd/pcie_ddr/hdl/pcie_ddr_wrapper.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@@ -84,64 +107,23 @@
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<Attr Name="ScopedToCell" Val="pcie_ddr_mig_7series_0_0"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ddr_axi_wr.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ddr_axi_rd.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/fifo2axi_convert.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/fifo_axi_ctrl.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/axi2fifo_convert.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ddr_ctrl_top.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/ip/ddr_ctrl/mig_a.prj">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="ScopedToCell" Val="ddr_ctrl"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/axi_fifo_ctrl.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="pcie_ddr_wrapper"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TopModule" Val="axi_ddr_top"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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@@ -172,7 +154,6 @@
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<FileSet Name="fifo_ddr_info" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_info">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@@ -186,7 +167,6 @@
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<FileSet Name="fifo_ddr_data" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_data">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@@ -200,7 +180,6 @@
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<FileSet Name="ddr_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ddr_ctrl">
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<File Path="$PSRCDIR/sources_1/ip/ddr_ctrl/ddr_ctrl.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@@ -214,7 +193,6 @@
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<FileSet Name="fifo_ddr_addr" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_addr">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@@ -225,6 +203,32 @@
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="fifo_ddr_len" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_len">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_len/fifo_ddr_len.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="fifo_ddr_len"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="fifo_ddr_mask" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_mask">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_mask/fifo_ddr_mask.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="fifo_ddr_mask"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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@@ -264,16 +268,37 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_data_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_data" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_data" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true">
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<Run Id="fifo_ddr_data_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_data" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_data" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_data_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="ddr_ctrl_synth_1" Type="Ft3:Synth" SrcSet="ddr_ctrl" Part="xc7k325tffg900-2" ConstrsSet="ddr_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ddr_ctrl_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_addr_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_addr" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_addr" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_addr_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_len_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_len" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_len" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_len_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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@@ -285,7 +310,7 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_addr_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_addr" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_addr" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_addr_synth_1" IncludeInArchive="true">
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<Run Id="fifo_ddr_mask_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_mask" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_mask" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_mask_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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@@ -349,6 +374,40 @@
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<RQSFiles/>
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</Run>
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<Run Id="ddr_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="ddr_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ddr_ctrl_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_addr_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_addr" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_addr_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_len_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_len" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_len_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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||||
<Desc>Default settings for Implementation.</Desc>
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@@ -367,7 +426,7 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_addr_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_addr" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_addr_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Run Id="fifo_ddr_mask_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_mask" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_mask_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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||||
<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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||||
<Desc>Default settings for Implementation.</Desc>
|
||||
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||||
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