diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci index b1b9838..5f5f095 100644 --- a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci @@ -150,7 +150,7 @@ 1 1 1 - 1 + 0 0 6 BlankString @@ -165,7 +165,7 @@ 33 0 1 - 0 + 1 0 0 0 @@ -174,9 +174,9 @@ 0 0 kintex7 - 0 + 1 0 - 0 + 1 1 0 0 @@ -213,15 +213,15 @@ 0 0 0 - 0 + 1 0 - 1 + 0 0 1 1 0 0 - 0 + 2 1 1 1 @@ -260,14 +260,14 @@ 0 0 0 - 62 + 61 1023 1023 1023 1023 1023 1023 - 61 + 60 0 0 0 @@ -332,7 +332,7 @@ 0 false false - false + true 0 0 Slave_Interface_Clock_Enable @@ -369,7 +369,7 @@ false false true - false + true false true Data_FIFO @@ -384,16 +384,16 @@ Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM - Common_Clock_Block_RAM - 0 - 62 + Independent_Clocks_Block_RAM + 1 + 61 1023 1023 1023 1023 1023 1023 - 61 + 60 false false false @@ -457,7 +457,7 @@ Fully_Registered Fully_Registered true - Synchronous_Reset + Asynchronous_Reset false 1 0 @@ -548,7 +548,11 @@ + + + + @@ -556,6 +560,7 @@ + diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci index 4dcf84b..38ddcdd 100644 --- a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci @@ -150,7 +150,7 @@ 1 1 1 - 1 + 0 0 6 BlankString @@ -165,7 +165,7 @@ 512 0 1 - 0 + 1 0 0 0 @@ -174,9 +174,9 @@ 0 0 kintex7 - 0 + 1 0 - 0 + 1 1 0 0 @@ -213,15 +213,15 @@ 0 0 0 - 0 + 1 0 - 1 + 0 0 1 - 1 + 0 0 0 - 0 + 2 1 1 1 @@ -260,14 +260,14 @@ 0 0 0 - 62 + 61 1023 1023 1023 1023 1023 1023 - 61 + 60 0 0 0 @@ -332,7 +332,7 @@ 0 false false - false + true 0 0 Slave_Interface_Clock_Enable @@ -369,7 +369,7 @@ false false true - false + true false true Data_FIFO @@ -384,16 +384,16 @@ Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM - Common_Clock_Block_RAM - 0 - 62 + Independent_Clocks_Block_RAM + 1 + 61 1023 1023 1023 1023 1023 1023 - 61 + 60 false false false @@ -457,7 +457,7 @@ Fully_Registered Fully_Registered true - Synchronous_Reset + Asynchronous_Reset false 1 0 @@ -476,7 +476,7 @@ true Active_High 0 - true + false Active_High 1 false @@ -548,7 +548,11 @@ + + + + @@ -556,6 +560,7 @@ + diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci index 2e9ddff..c620683 100644 --- a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci @@ -154,7 +154,7 @@ 0 6 BlankString - 5 + 10 1 32 64 @@ -162,7 +162,7 @@ 64 2 0 - 5 + 10 0 1 0 @@ -217,8 +217,8 @@ 0 1 0 - 1 - 1 + 0 + 0 0 0 0 @@ -413,7 +413,7 @@ false false false - 5 + 10 64 1024 16 @@ -422,7 +422,7 @@ 1024 16 false - 5 + 10 64 Embedded_Reg false @@ -473,10 +473,10 @@ false false false - true + false Active_High 0 - true + false Active_High 1 false @@ -556,6 +556,7 @@ + diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_len/fifo_ddr_len.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_len/fifo_ddr_len.xci new file mode 100644 index 0000000..b0d8f2b --- /dev/null +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_len/fifo_ddr_len.xci @@ -0,0 +1,571 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_ddr_len + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 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No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k325t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_mask/fifo_ddr_mask.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_mask/fifo_ddr_mask.xci new file mode 100644 index 0000000..14fae81 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_mask/fifo_ddr_mask.xci @@ -0,0 +1,569 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_ddr_mask + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 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No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k325t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/new/axi_ddr_top.v b/ddr_general_design.srcs/sources_1/new/axi_ddr_top.v new file mode 100644 index 0000000..c81b2e5 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/axi_ddr_top.v @@ -0,0 +1,349 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/20 14:38:30 +// Design Name: +// Module Name: axi_ddr_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module axi_ddr_top( + // Inouts + inout [63:0] ddr3_dq, + inout [7:0] ddr3_dqs_n, + inout [7:0] ddr3_dqs_p, + // Outputs + output [15:0] ddr3_addr, + output [2:0] ddr3_ba, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output ddr3_reset_n, + output [1:0] ddr3_ck_p, + output [1:0] ddr3_ck_n, + output [1:0] ddr3_cke, + output [1:0] ddr3_cs_n, + output [7:0] ddr3_dm, + output [1:0] ddr3_odt, + // Inputs + // Single-ended system clock + input sys_clk_i, + input sys_rst_i, + output init_calib_complete + ); + + // Wire declarations + wire ui_clk; + wire ui_rst; + + + // Slave Interface Write Address Ports + wire [3:0] s_axi_awid; + wire [32:0] s_axi_awaddr; + wire [7:0] s_axi_awlen; + wire [2:0] s_axi_awsize; + wire [1:0] s_axi_awburst; + wire [0:0] s_axi_awlock; + wire [3:0] s_axi_awcache; + wire [2:0] s_axi_awprot; + wire s_axi_awvalid; + wire s_axi_awready; + // Slave Interface Write Data Ports + wire [512:0] s_axi_wdata; + wire [63:0] s_axi_wstrb; + wire s_axi_wlast; + wire s_axi_wvalid; + wire s_axi_wready; + // Slave Interface Write Response Ports + wire s_axi_bready; + wire [3:0] s_axi_bid; + wire [1:0] s_axi_bresp; + wire s_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] s_axi_arid; + wire [32:0] s_axi_araddr; + wire [7:0] s_axi_arlen; + wire [2:0] s_axi_arsize; + wire [1:0] s_axi_arburst; + wire [0:0] s_axi_arlock; + wire [3:0] s_axi_arcache; + wire [2:0] s_axi_arprot; + wire s_axi_arvalid; + wire s_axi_arready; + // Slave Interface Read Data Ports + wire s_axi_rready; + wire [3:0] s_axi_rid; + wire [32:0] s_axi_rdata; + wire [1:0] s_axi_rresp; + wire s_axi_rlast; + wire s_axi_rvalid; + + wire rd_fifo_re; + wire [ 7:0] rd_fifo_len; + wire [32:0] rd_fifo_addr; + wire rd_fifo_len_empty; + wire rd_fifo_addr_empty; + wire [511:0] rd_fifo_data; + wire rd_fifo_we; + wire rd_fifo_almost_full; + wire wr_fifo_re; + wire [32:0] wr_fifo_addr; + wire [511:0] wr_fifo_data; + wire [63:0] wr_fifo_mask; + wire wr_fifo_addr_empty; + wire wr_fifo_data_empty; + wire wr_fifo_mask_empty; + + +ddr_ctrl u_ddr_ctrl( +// Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_reset_n (ddr3_reset_n), + .init_calib_complete (init_calib_complete), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + + +// Application interface ports + .ui_clk (ui_clk), // 100 Mhz + .ui_clk_sync_rst (ui_rst), + .mmcm_locked (), + .aresetn (), + .app_sr_req (1'b0), + .app_ref_req (1'b0), + .app_zq_req (1'b0), + .app_sr_active (), + .app_ref_ack (), + .app_zq_ack (), + +// Slave Interface Write Address Ports + .s_axi_awid (s_axi_awid), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awlen (s_axi_awlen), + .s_axi_awsize (s_axi_awsize), + .s_axi_awburst (s_axi_awburst), + .s_axi_awlock (s_axi_awlock), + .s_axi_awcache (s_axi_awcache), + .s_axi_awprot (s_axi_awprot), + .s_axi_awqos (4'h0), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + + +// Slave Interface Write Data Ports + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wlast (s_axi_wlast), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + + +// Slave Interface Write Response Ports + .s_axi_bid (s_axi_bid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + +// Slave Interface Read Address Ports + .s_axi_arid (s_axi_arid), + .s_axi_araddr (s_axi_araddr), + .s_axi_arlen (s_axi_arlen), + .s_axi_arsize (s_axi_arsize), + .s_axi_arburst (s_axi_arburst), + .s_axi_arlock (s_axi_arlock), + .s_axi_arcache (s_axi_arcache), + .s_axi_arprot (s_axi_arprot), + .s_axi_arqos (4'h0), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), +// Slave Interface Read Data Ports + .s_axi_rid (s_axi_rid), + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rlast (s_axi_rlast), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), +// System Clock Ports + .sys_clk_i (sys_clk_i), // 200 Mhz + .sys_rst (sys_rst_i) + ); + +// Instance of axi_m_rd +axi_m_rd u_axi_m_rd ( + .ui_clk_i(ui_clk), + .ui_rst_i(ui_rst), + + // Connect m_axi to s_axi + .m_axi_arid_o(s_axi_arid), + .m_axi_araddr_o(s_axi_araddr), + .m_axi_arlen_o(s_axi_arlen), + .m_axi_arsize_o(s_axi_arsize), + .m_axi_arburst_o(s_axi_arburst), + .m_axi_arlock_o(s_axi_arlock), + .m_axi_arcache_o(s_axi_arcache), + .m_axi_arprot_o(s_axi_arprot), + .m_axi_arvalid_o(s_axi_arvalid), + .m_axi_arready_i(s_axi_arready), + .m_axi_rready_o(s_axi_rready), + .m_axi_rid_i(s_axi_rid), + .m_axi_rdata_i(s_axi_rdata), + .m_axi_rresp_i(s_axi_rresp), + .m_axi_rlast_i(s_axi_rlast), + .m_axi_rvalid_i(s_axi_rvalid), + + // Remaining ports + .rd_fifo_empty_i(rd_fifo_addr_empty & rd_fifo_len_empty), + .rd_fifo_re_o(rd_fifo_re), + .rd_fifo_addr_i(rd_fifo_addr), + .rd_fifo_len_i(rd_fifo_len), + .rd_fifo_almost_full_i(rd_fifo_almost_full), + .rd_fifo_we_o(rd_fifo_we), + .rd_fifo_din_o(rd_fifo_data) +); + + + +fifo_ddr_addr fifo_rd_addr_inst( + .rst(sys_rst_i), + .wr_clk(sys_clk_i), + .wr_en(), + .din(), + .full(), + .rd_clk(ui_clk), + .rd_en(rd_fifo_re), + .dout(rd_fifo_addr), + .empty(rd_fifo_addr_empty) +); + +fifo_ddr_len fifo_rd_len_inst( + .rst(sys_rst_i), + .wr_clk(sys_clk_i), + .wr_en(), + .din(), + .full(), + .rd_clk(ui_clk), + .rd_en(rd_fifo_re), + .dout(rd_fifo_len), + .empty(rd_fifo_len_empty) +); + +fifo_ddr_data fifo_rd_data_inst( + .rst(ui_rst), + .wr_clk(ui_clk), + .wr_en(rd_fifo_we), + .din(rd_fifo_data), + .almost_full(rd_fifo_almost_full), + .full(), + .rd_clk(sys_clk_i), + .rd_en(), + .dout(), + .empty() +); + +fifo_ddr_info fifo_rd_info_inst( + .srst(sys_rst_i), + .clk(sys_clk_i), + .wr_en(), + .din(), + .full(), + .rd_en(), + .dout(), + .empty() +); + +// Instance of axi_m_wr +axi_m_wr u_axi_m_wr ( + .ui_clk_i(ui_clk), + .ui_rst_i(ui_rst), + + // Connect m_axi to s_axi + .m_axi_awid_o(s_axi_awid), + .m_axi_awaddr_o(s_axi_awaddr), + .m_axi_awlen_o(s_axi_awlen), + .m_axi_awsize_o(s_axi_awsize), + .m_axi_awburst_o(s_axi_awburst), + .m_axi_awlock_o(s_axi_awlock), + .m_axi_awcache_o(s_axi_awcache), + .m_axi_awprot_o(s_axi_awprot), + .m_axi_awvalid_o(s_axi_awvalid), + .m_axi_awready_i(s_axi_awready), + .m_axi_wdata_o(s_axi_wdata), + .m_axi_wstrb_o(s_axi_wstrb), + .m_axi_wlast_o(s_axi_wlast), + .m_axi_wvalid_o(s_axi_wvalid), + .m_axi_wready_i(s_axi_wready), + .m_axi_bready_o(s_axi_bready), + .m_axi_bid_i(s_axi_bid), + .m_axi_bresp_i(s_axi_bresp), + .m_axi_bvalid_i(s_axi_bvalid), + + // Remaining ports + .wr_fifo_empty_i(wr_fifo_addr_empty && wr_fifo_data_empty && wr_fifo_mask_empty), + .wr_fifo_re_o(wr_fifo_re), + .wr_fifo_addr_i(wr_fifo_addr), + .wr_fifo_len_i(1'b1), + .wr_fifo_data_i(wr_fifo_data), + .wr_fifo_mask_i(wr_fifo_mask) + ); + +fifo_ddr_addr fifo_wr_addr_inst( + .rst(sys_rst_i), + .wr_clk(sys_clk_i), + .wr_en(), + .din(), + .full(), + .rd_clk(ui_clk), + .rd_en(wr_fifo_re), + .dout(wr_fifo_addr), + .empty(wr_fifo_addr_empty) +); + +fifo_ddr_data fifo_wr_data_inst( + .rst(sys_rst_i), + .wr_clk(sys_clk_i), + .wr_en(), + .din(), + .full(), + .rd_clk(ui_clk), + .rd_en(wr_fifo_re), + .dout(wr_fifo_data), + .empty(wr_fifo_data_empty) +); + +fifo_ddr_mask fifo_wr_mask_inst( + .rst(sys_rst_i), + .wr_clk(sys_clk_i), + .wr_en(), + .din(), + .full(), + .rd_clk(ui_clk), + .rd_en(wr_fifo_re), + .dout(wr_fifo_mask), + .empty(wr_fifo_mask_empty) +); + +endmodule diff --git a/ddr_general_design.srcs/sources_1/new/axi_fifo_ctrl.v b/ddr_general_design.srcs/sources_1/new/axi_fifo_ctrl.v new file mode 100644 index 0000000..62f881a --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/axi_fifo_ctrl.v @@ -0,0 +1,204 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/20 20:49:32 +// Design Name: +// Module Name: axi_fifo_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module axi_fifo_ctrl( + input sys_clk_i, + input sys_rst_i, + + input [1:0] rw_req_i, + input [32:0] rw_addr_i, + input [4:0] rd_len_i, + input [511:0] wr_data_i, + input [63:0] wr_mask_i, + input [4:0] rw_info_i, + + output rw_ack_o, + output [4:0] rw_info_o, + + output [511:0] rd_data_o, + output rd_data_v_o, + output [4:0] rd_info_o, + + input wr_fifo_almost_full_i, + input wr_fifo_full_i, + output wr_fifo_we_o, + output [32:0] wr_fifo_addr_o, + output [511:0] wr_fifo_data_o, + output [63:0] wr_fifo_mask_o, + + input rd_fifo_almost_full_i, + input rd_fifo_full_i, + output [32:0] rd_fifo_addr_o, + output [7:0] rd_fifo_len_o, + output [4:0] rd_fifo_info_o, + output rd_fifo_we_o, + input rd_fifo_empty_i, + output rd_fifo_re_o, + input [511:0] rd_fifo_data_o, + input rd_fifo_data_v_o, + input [4:0] rd_fifo_info_i, + + output [1:0] rw_fifo_busy_o + ); + + localparam + S_IDLE = 3'b000, + S_WR_START = 3'b001, + S_WR_RESP = 3'b010, + S_RD_START = 3'b011, + S_RD_RESP = 3'b100; + + + reg [2:0] c_state; + reg [2:0] n_state; + + reg rd_req; + reg wr_req; + reg rw_ack; + reg [4:0] rd_info; + reg [511:0] rd_data; + reg rd_data_v; + reg [4:0] rw_info; + + reg wr_fifo_we; + reg [32:0] wr_fifo_addr; + reg [511:0] wr_fifo_data; + reg [63:0] wr_fifo_mask; + reg [32:0] rd_fifo_addr; + reg [7:0] rd_fifo_len; + reg rd_fifo_we; + reg rd_fifo_re; + + assign rw_ack_o = rw_ack; + assign rd_info_o = rd_info; + assign rd_data_o = rd_data; + assign rd_data_v_o = rd_data_v; + assign rw_info_o = rw_info; + assign wr_fifo_we_o = wr_fifo_we; + assign wr_fifo_addr_o = wr_fifo_addr; + assign wr_fifo_data_o = wr_fifo_data; + assign wr_fifo_mask_o = wr_fifo_mask; + assign rd_fifo_addr_o = rd_fifo_addr; + assign rd_fifo_len_o = rd_fifo_len; + assign rd_fifo_we_o = rd_fifo_we; + assign rd_fifo_re_o = rd_fifo_re; + assign rd_fifo_info_o = rw_info; + assign rw_fifo_busy_o = 2'b11; // ! + + always @(posedge sys_clk_i or posedge sys_rst_i) begin + if (sys_rst_i) begin + c_state <= S_IDLE; + end else begin + c_state <= n_state; + end + end + + always @(*) begin + rd_req = 1'b0; + wr_req = 1'b0; + rw_ack = 1'b0; + rw_info = 5'b0; + wr_fifo_we = 1'b0; + wr_fifo_addr = 33'b0; + wr_fifo_data = 512'b0; + wr_fifo_mask = 64'b0; + rd_fifo_addr = 33'b0; + rd_fifo_len = 8'b0; + rd_fifo_we = 1'b0; + rd_fifo_re = 1'b0; + n_state = S_IDLE; + case (c_state) + S_IDLE: begin + rw_info = rw_info_i; + if(rw_req_i == 2'b01) begin + rd_fifo_addr = rw_addr_i; + rd_fifo_len = rd_len_i; + rd_req = 1'b1; + n_state = S_WR_START; + end else if(rw_req_i == 2'b10) begin + wr_fifo_addr = rw_addr_i; + wr_fifo_data = wr_data_i; + wr_fifo_mask = wr_mask_i; + wr_req = 1'b1; + n_state = S_RD_START; + end + else begin + n_state = S_IDLE; + end + end + S_RD_START: begin + rw_info = rw_info; + rd_fifo_addr = rd_fifo_addr; + rd_fifo_len = rd_fifo_len; + rd_req = rd_req; + if(rd_fifo_full_i == 1'b0) begin + rd_fifo_we = 1'b1; + n_state = S_RD_RESP; + end + else begin + n_state = S_RD_START; + end + end + S_RD_RESP: begin + rw_info = rw_info; + rw_ack = 1'b1; + n_state = S_IDLE; + end + S_WR_START: begin + rw_info = rw_info; + wr_fifo_addr = wr_fifo_addr; + wr_fifo_data = wr_fifo_data; + wr_fifo_mask = wr_fifo_mask; + wr_req = wr_req; + if(wr_fifo_full_i == 1'b0) begin + wr_fifo_we = 1'b1; + n_state = S_WR_RESP; + end + else begin + n_state = S_WR_START; + end + end + S_WR_RESP: begin + rw_info = rw_info; + rw_ack = 1'b1; + n_state = S_IDLE; + end + default: begin + n_state = S_IDLE; + end + endcase + end + + always @(posedge sys_clk_i or posedge sys_rst_i) begin + if (sys_rst_i) begin + rd_data <= 512'b0; + rd_data_v <= 1'b0; + rd_info <= 5'b0; + end + else begin + if () begin + + end + end + end + +endmodule diff --git a/ddr_general_design.srcs/sources_1/new/axi_m_rd.v b/ddr_general_design.srcs/sources_1/new/axi_m_rd.v new file mode 100644 index 0000000..545f9cc --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/axi_m_rd.v @@ -0,0 +1,158 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/20 14:56:39 +// Design Name: +// Module Name: axi_m_rd +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module axi_m_rd( + input ui_clk_i, + input ui_rst_i, + + // Master Interface Read Address Ports + output [3:0] m_axi_arid_o, + output [32:0] m_axi_araddr_o, + output [7:0] m_axi_arlen_o, + output [2:0] m_axi_arsize_o, + output [1:0] m_axi_arburst_o, + output [0:0] m_axi_arlock_o, + output [3:0] m_axi_arcache_o, + output [2:0] m_axi_arprot_o, + output m_axi_arvalid_o, + input m_axi_arready_i, + // Master Interface Read Data Ports + output m_axi_rready_o, + input [3:0] m_axi_rid_i, + input [32:0] m_axi_rdata_i, + input [1:0] m_axi_rresp_i, + input m_axi_rlast_i, + input m_axi_rvalid_i, + + input rd_fifo_empty_i, + output rd_fifo_re_o, + input [32:0] rd_fifo_addr_i, + input [7:0] rd_fifo_len_i, + + input rd_fifo_almost_full_i, + output rd_fifo_we_o, + output [511:0] rd_fifo_din_o + ); + + localparam + S_RD_IDLE = 5'b00001, + S_RD_ADDR_START = 5'b00010, + S_RD_ADDR_WAIT = 5'b00100, + S_RD_DATA = 5'b01000, + S_RD_DONE = 5'b10000; + + reg [ 4:0] c_state; + reg [ 4:0] n_state; + + reg rd_fifo_re; + + reg [32:0] rd_addr; + reg rd_addr_v; + reg [ 7:0] rd_len; + + reg m_axi_rready; + + assign m_axi_arid_o = 4'h0; + assign m_axi_araddr_o = rd_addr; + assign m_axi_arlen_o = rd_len - 8'b1; + assign m_axi_arsize_o = 3'b110; // 512 bit + assign m_axi_arburst_o = 2'b01; // inc mode + assign m_axi_arlock_o = 1'b0; + assign m_axi_arcache_o = 4'b0000; + assign m_axi_arprot_o = 3'b000; + assign m_axi_arvalid_o = rd_addr_v; + assign m_axi_rready_o = m_axi_rready; + + assign rd_fifo_re_o = rd_fifo_re; + + assign rd_fifo_we_o = m_axi_rvalid_i; + assign rd_fifo_din_o = m_axi_rdata_i; + + always @(posedge ui_clk_i or posedge ui_rst_i) begin + if(ui_rst_i) begin + c_state <= S_RD_IDLE; + end + else begin + c_state <= n_state; + end + end + + always @(*) begin + n_state = S_RD_IDLE; + rd_fifo_re = 1'b0; + rd_addr = 33'b0; + rd_len = 8'b0; + rd_addr_v = 1'b0; + m_axi_rready = 1'b0; + + case(c_state) + S_RD_IDLE: begin + if(!rd_fifo_empty_i) begin + rd_fifo_re = 1'b1; + n_state = S_RD_ADDR_START; + end + else begin + n_state = S_RD_IDLE; + end + end + S_RD_ADDR_START: begin + rd_addr = rd_fifo_addr_i; + rd_len = rd_fifo_len_i; + rd_addr_v = 1'b1; + n_state = S_RD_ADDR_WAIT; + end + S_RD_ADDR_WAIT: begin + if(m_axi_arready_i) begin + n_state = S_RD_DATA; + end + else begin + rd_addr = rd_addr ; + rd_len = rd_len ; + rd_addr_v = rd_addr_v; + m_axi_rready = 1'b1; + n_state = S_RD_ADDR_WAIT; + end + end + S_RD_DATA: begin + m_axi_rready = 1'b1; + casex({m_axi_rvalid_i, m_axi_rlast_i, rd_fifo_almost_full_i}) + 3'b0xx: begin + n_state = S_RD_DATA; + end + 3'b11x: begin // last in full + n_state = S_RD_DONE; + end + 3'b100: begin + n_state = S_RD_DATA; + end + 3'b101: begin // overflow + n_state = S_RD_DATA; + end + endcase + end + S_RD_DONE: begin + n_state = S_RD_IDLE; + end + endcase + end + +endmodule diff --git a/ddr_general_design.srcs/sources_1/new/axi_m_wr.v b/ddr_general_design.srcs/sources_1/new/axi_m_wr.v new file mode 100644 index 0000000..80fdeeb --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/axi_m_wr.v @@ -0,0 +1,172 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/20 16:05:32 +// Design Name: +// Module Name: axi_m_wr +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module axi_m_wr( + input ui_clk_i, + input ui_rst_i, + + // Master Interface Write Address Ports + output [3:0] m_axi_awid_o, + output [32:0] m_axi_awaddr_o, + output [7:0] m_axi_awlen_o, + output [2:0] m_axi_awsize_o, + output [1:0] m_axi_awburst_o, + output [0:0] m_axi_awlock_o, + output [3:0] m_axi_awcache_o, + output [2:0] m_axi_awprot_o, + output m_axi_awvalid_o, + input m_axi_awready_i, + // Master Interface Write Data Ports + output [512:0] m_axi_wdata_o, + output [63:0] m_axi_wstrb_o, + output m_axi_wlast_o, + output m_axi_wvalid_o, + input m_axi_wready_i, + // Master Interface Write Response Ports + output m_axi_bready_o, + input [3:0] m_axi_bid_i, + input [1:0] m_axi_bresp_i, + input m_axi_bvalid_i, + + input wr_fifo_empty_i, + output wr_fifo_re_o, + input [32:0] wr_fifo_addr_i, + input [7:0] wr_fifo_len_i, + input [511:0] wr_fifo_data_i, + input [63:0] wr_fifo_mask_i + ); + + localparam + S_WR_IDLE = 5'b00001, + S_WR_ADDR_START = 5'b00010, + S_WR_ADDR_WAIT = 5'b00100, + S_WR_DATA = 5'b01000, + S_WR_DONE = 5'b10000; + + reg [4:0] c_state; + reg [4:0] n_state; + + reg wr_fifo_re; + reg [32:0] wr_addr; + reg [7:0] wr_len; + reg wr_addr_v; + reg [511:0] wr_data; + reg [63:0] wr_mask; + reg wr_data_v; + reg wr_last; + + reg m_axi_bready; + + assign wr_fifo_re_o = wr_fifo_re; + assign m_axi_awid_o = 4'h0; + assign m_axi_awaddr_o = wr_addr; + assign m_axi_awlen_o = 8'b0; + assign m_axi_awsize_o = 3'b110; // 512 bit + assign m_axi_awburst_o = 2'b01; // inc mode + assign m_axi_awlock_o = 1'b0; + assign m_axi_awcache_o = 4'b0000; + assign m_axi_awprot_o = 3'b000; + assign m_axi_awvalid_o = wr_addr_v; + assign m_axi_wdata_o = wr_data; + assign m_axi_wstrb_o = wr_mask; + assign m_axi_wlast_o = wr_last; + assign m_axi_wvalid_o = wr_data_v; + assign m_axi_bready_o = m_axi_bready; + + always @(posedge ui_clk_i or posedge ui_rst_i) begin + if(ui_rst_i) begin + c_state <= S_WR_IDLE; + end + else begin + c_state <= n_state; + end + end + + always @(*) begin + n_state = S_WR_IDLE; + wr_fifo_re = 1'b0; + wr_addr = 33'b0; + wr_len = 8'b0; + wr_addr_v = 1'b0; + wr_data = 512'b0; + wr_mask = 64'b0; + wr_data_v = 1'b0; + wr_last = 1'b0; + m_axi_bready = 1'b0; + + case(c_state) + S_WR_IDLE: begin + if(!wr_fifo_empty_i) begin + wr_fifo_re = 1'b1; + n_state = S_WR_ADDR_START; + end + else begin + n_state = S_WR_IDLE; + end + end + S_WR_ADDR_START: begin + wr_addr = wr_fifo_addr_i; + wr_len = wr_fifo_len_i; + wr_addr_v = 1'b1; + wr_data = wr_fifo_data_i; + wr_mask = wr_fifo_mask_i; + n_state = S_WR_ADDR_WAIT; + end + S_WR_ADDR_WAIT: begin + if(m_axi_awready_i) begin + wr_data_v = 1'b1; + n_state = S_WR_DATA; + end + else begin + wr_addr = wr_addr; + wr_len = wr_len; + wr_addr_v = wr_addr_v; + wr_data = wr_data; + wr_mask = wr_mask; + n_state = S_WR_ADDR_WAIT; + end + end + S_WR_DATA: begin + if(m_axi_wready_i) begin + wr_last = 1'b1; + n_state = S_WR_DONE; + end + else begin + wr_data = wr_data; + wr_mask = wr_mask; + wr_data_v = wr_data_v; + n_state = S_WR_DATA; + end + end + S_WR_DONE: begin + if(m_axi_bvalid_i && m_axi_bresp_i == 2'b00) begin + n_state = S_WR_IDLE; + end + else begin + n_state = S_WR_DONE; + end + end + endcase + end + + +endmodule diff --git a/ddr_general_design.srcs/sources_1/new/fifo2axi_convert.v b/ddr_general_design.srcs/sources_1/new/fifo2axi_convert.v deleted file mode 100644 index 6f9cbd3..0000000 --- a/ddr_general_design.srcs/sources_1/new/fifo2axi_convert.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/03/19 10:25:21 -// Design Name: -// Module Name: fifo2axi_convert -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module fifo2axi_convert( - - ); -endmodule diff --git a/ddr_general_design.srcs/sources_1/new/axi2fifo_convert.v b/ddr_general_design.srcs/sources_1/new/old/axi2fifo_convert.v similarity index 100% rename from ddr_general_design.srcs/sources_1/new/axi2fifo_convert.v rename to ddr_general_design.srcs/sources_1/new/old/axi2fifo_convert.v diff --git a/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v b/ddr_general_design.srcs/sources_1/new/old/ddr_axi_rd.v similarity index 100% rename from ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v rename to ddr_general_design.srcs/sources_1/new/old/ddr_axi_rd.v diff --git a/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v b/ddr_general_design.srcs/sources_1/new/old/ddr_axi_wr.v similarity index 93% rename from ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v rename to ddr_general_design.srcs/sources_1/new/old/ddr_axi_wr.v index d9da7fa..3c9ff73 100644 --- a/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v +++ b/ddr_general_design.srcs/sources_1/new/old/ddr_axi_wr.v @@ -25,7 +25,7 @@ module ddr_axi_wr( input aclk , //axi总时钟 //axi4写通道地址通道 output [3:0] m_axi_awid , //写地址ID，用来标志一组写信号 - output [31:0] m_axi_awaddr , //写地址，给出一次写突发传输的写地址 + output [32:0] m_axi_awaddr , //写地址，给出一次写突发传输的写地址 output [7:0] m_axi_awlen , //突发长度，给出突发传输的次数 output [2:0] m_axi_awsize , //突发大小，给出每次突发传输的字节数 output [1:0] m_axi_awburst, //突发类型 @@ -36,7 +36,7 @@ module ddr_axi_wr( output m_axi_awvalid, //有效信号，表明此通道的地址控制信号有效 input m_axi_awready, //表明“从”可以接收地址和对应的控制信号 //axi4写通道数据通道 - output [63:0] m_axi_wdata , //写数据 + output [511:0] m_axi_wdata , //写数据 output [7:0] m_axi_wstrb , //写数据有效的字节线 output m_axi_wlast , //表明此次传输是最后一个突发传输 output m_axi_wvalid , //写有效，表明此次写有效 @@ -48,11 +48,11 @@ module ddr_axi_wr( output m_axi_bready , //表明主机能够接收写响应 //用户端信号 input wr_start , //写突发触发信号 - input [31:0] wr_adrs , //地址 + input [32:0] wr_adrs , //地址 input [9:0] wr_len , //长度 output wr_ready , //写空闲 output wr_fifo_re , //连接到写fifo的读使能 - input [63:0] wr_fifo_data , //连接到fifo的读数据 + input [511:0] wr_fifo_data , //连接到fifo的读数据 output wr_done //完成一次突发 ); @@ -69,7 +69,7 @@ localparam S_WR_WAIT = 3'd5;//接受写应答 localparam S_WR_DONE = 3'd6;//写结束 //reg define reg [2:0] wr_state ; //状态寄存器 -reg [31:0] reg_wr_adrs; //地址寄存器 +reg [32:0] reg_wr_adrs; //地址寄存器 reg reg_awvalid; //地址有效握手信号 reg reg_wvalid ; //数据有效握手信号 reg reg_w_last ; //传输最后一个数据 @@ -86,7 +86,7 @@ assign wr_fifo_re = ((reg_wvalid & m_axi_wready )); //只有一个主机，可随意设置 assign m_axi_awid = 4'b1111; //把地址赋予总线 -assign m_axi_awaddr[31:0] = reg_wr_adrs[31:0]; +assign m_axi_awaddr[32:0] = reg_wr_adrs[32:0]; //一次突发传输1长度 assign m_axi_awlen[7:0] = wr_len-'d1; //表示AXI总线每个数据宽度是8字节，64位 @@ -100,7 +100,7 @@ assign m_axi_awqos[3:0] = 4'b0000; //地址握手信号AWVALID assign m_axi_awvalid = reg_awvalid; //fifo数据赋予总线 -assign m_axi_wdata[63:0] = wr_fifo_data[63:0]; +assign m_axi_wdata[511:0] = wr_fifo_data[511:0]; assign m_axi_wstrb[7:0] = 8'hFF; //写到最后一个数据 assign m_axi_wlast =(reg_w_len[7:0] == 8'd0)?'b1:'b0; @@ -115,7 +115,7 @@ assign wr_ready = (wr_state == S_WR_IDLE)?1'b1:1'b0; always @(posedge aclk or negedge aresetn) begin if(!aresetn) begin wr_state <= S_WR_IDLE; - reg_wr_adrs[31:0] <= 32'd0; + reg_wr_adrs[32:0] <= 33'd0; reg_awvalid <= 1'b0; reg_wvalid <= 1'b0; reg_w_last <= 1'b0; @@ -126,7 +126,7 @@ assign wr_ready = (wr_state == S_WR_IDLE)?1'b1:1'b0; S_WR_IDLE: begin //写空闲 if(wr_start) begin //触发写过程 wr_state <= S_WA_WAIT; - reg_wr_adrs[31:0] <= wr_adrs[31:0]; + reg_wr_adrs[32:0] <= wr_adrs[32:0]; end reg_awvalid <= 1'b0; reg_wvalid <= 1'b0; diff --git a/ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v b/ddr_general_design.srcs/sources_1/new/old/ddr_ctrl_top.v similarity index 100% rename from ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v rename to ddr_general_design.srcs/sources_1/new/old/ddr_ctrl_top.v diff --git a/ddr_general_design.srcs/sources_1/new/old/fifo2axi_convert.v b/ddr_general_design.srcs/sources_1/new/old/fifo2axi_convert.v new file mode 100644 index 0000000..94dc91a --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/old/fifo2axi_convert.v @@ -0,0 +1,98 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/19 10:25:21 +// Design Name: +// Module Name: fifo2axi_convert +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module fifo2axi_convert( + input clk, + input rst, + + input [1:0] rw_req , + input [32:0] rw_addr , + input [4:0] rd_length , + input [511:0] wr_data , + input [63:0] wr_mask , + input [4:0] rw_where , + output rw_in_fifo_ack , + output [4:0] rw_in_fifo_ack_2where, + output rw_fifo_buzy , + + output reg wr_start , + input wr_ready , + input wr_fifo_re , + input wr_done , + + input fifo_ddr_waddr_full, + output reg fifo_ddr_waddr_we, + input fifo_ddr_waddr_empty, + output reg fifo_ddr_waddr_re, + input fifo_ddr_waddr_wack, + input fifo_ddr_waddr_rv, + + output rd_start , + output [32:0] rd_adrs , + output [9:0] rd_len , + input rd_ready , + input rd_fifo_we , + input rd_done + ); + + localparam [1:0] + S_IDLE = 2'd0, + S_FIFO_RD = 2'd1, + S_WR_START = 2'd2, +; + + reg [1:0] c_state; + reg [1:0] n_state; + + always @(posedge clk or posedge rst) begin + if(rst) begin + c_state <= 0; + end + else begin + c_state <= n_state; + end + end + + always @(*) begin + wr_start <= 1'b0; + fifo_ddr_waddr_we <= 1'b0; + fifo_ddr_waddr_re <= 1'b0; + case(c_state) + S_IDLE: begin + casex({wr_ready, !fifo_ddr_waddr_empty}) + 2'b11: begin + n_state <= S_FIFO_RD; + fifo_ddr_waddr_re <= 1'b1; + end + default: begin + n_state = S_IDLE; + end + endcase + end + S_FIFO_RD: begin + n_state <= S_WR_START; + wr_start <= 1'b1; + end + endcase + end + +endmodule diff --git a/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v b/ddr_general_design.srcs/sources_1/new/old/fifo_axi_ctrl.v similarity index 87% rename from ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v rename to ddr_general_design.srcs/sources_1/new/old/fifo_axi_ctrl.v index 3acb91e..d0b725a 100644 --- a/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v +++ b/ddr_general_design.srcs/sources_1/new/old/fifo_axi_ctrl.v @@ -35,14 +35,30 @@ module fifo_axi_ctrl( output [4:0] rw_in_fifo_ack_2where, output [511:0] rd_data , output rd_valid , - output [4:0] rd_valid_2where + output [4:0] rd_valid_2where , + + output wr_start , + output [31:0] wr_adrs , + output [9:0] wr_len , + input wr_ready , + input wr_fifo_re , + output [63:0] wr_fifo_data , + input wr_done , + + output rd_start , + output [32:0] rd_adrs , + output [9:0] rd_len , + input rd_ready , + input rd_fifo_we , + input [63:0] rd_fifo_data, + input rd_done ); fifo2axi_convert fifo2axi_convert_inst( - .clk (), - .rst (), + .clk (clk), + .rst (rst), .rw_req (), .rw_addr (), diff --git a/ddr_general_design.xpr b/ddr_general_design.xpr index 86ba4ac..0ba93b9 100644 --- a/ddr_general_design.xpr +++ b/ddr_general_design.xpr @@ -36,13 +36,13 @@