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包焕垲
2025-03-20 22:45:37 +08:00
parent 98a79e8c78
commit 630b6e313a
17 changed files with 2325 additions and 144 deletions
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26
ddr_general_design.srcs/sources_1/new/old/axi2fifo_convert.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/19 10:32:12
// Design Name:
// Module Name: axi2fifo_convert
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axi2fifo_convert(
);
endmodule

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ddr_general_design.srcs/sources_1/new/old/ddr_axi_rd.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/18 16:15:52
// Design Name:
// Module Name: ddr_axi_rd
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_axi_rd(
input aresetn, //axi复位
input aclk, //axi时钟
//axi读通道写地址
output [3:0] m_axi_arid , //读地址ID，用来标志一组写信号
output [32:0] m_axi_araddr , //读地址，给出一次写突发传输的读地址
output [7:0] m_axi_arlen , //突发长度，给出突发传输的次数
output [2:0] m_axi_arsize , //突发大小，给出每次突发传输的字节数
output [1:0] m_axi_arburst, //突发类型
output [0:0] m_axi_arlock , //总线锁信号，可提供操作的原子性
output [3:0] m_axi_arcache, //内存类型，表明一次传输是怎样通过系统的
output [2:0] m_axi_arprot , //保护类型，表明一次传输的特权级及安全等级
output [3:0] m_axi_arqos , //质量服务QOS
output m_axi_arvalid, //有效信号，表明此通道的地址控制信号有效
input m_axi_arready, //表明“从”可以接收地址和对应的控制信号
//axi读通道读数据
input [3:0] m_axi_rid , //读ID tag
input [63:0] m_axi_rdata , //读数据
input [1:0] m_axi_rresp , //读响应，表明读传输的状态
input m_axi_rlast , //表明读突发的最后一次传输
input m_axi_rvalid, //表明此通道信号有效
output m_axi_rready, //表明主机能够接收读数据和响应信息
//用户端fifo接口
input rd_start , //读突发触发信号
input [32:0] rd_adrs , //地址
input [9:0] rd_len , //长度
output rd_ready , //读空闲
output rd_fifo_we , //连接到读fifo的写使能
output [63:0] rd_fifo_data, //连接到读fifo的写数据
output rd_done //完成一次突发
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
localparam S_RD_IDLE = 3'd0; //读空闲
localparam S_RA_WAIT = 3'd1; //读地址等待
localparam S_RA_START = 3'd2; //读地址
localparam S_RD_WAIT = 3'd3; //读数据等待
localparam S_RD_PROC = 3'd4; //读数据循环
localparam S_RD_DONE = 3'd5; //写结束
//reg define
reg [2:0] rd_state ; //状态寄存器
reg [32:0] reg_rd_adrs; //地址寄存器
reg [31:0] reg_rd_len ; //突发长度寄存器
reg reg_arvalid; //地址有效寄存器
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
assign rd_done = (rd_state == S_RD_DONE) ;
assign m_axi_arid = 4'b1111;//地址id
assign m_axi_araddr[32:0] = reg_rd_adrs[32:0];//地址
assign m_axi_arlen[7:0] = rd_len-32'd1;//突发长度
assign m_axi_arsize[2:0] = 3'b011;//表示AXI总线每个数据宽度是8字节，64位
assign m_axi_arburst[1:0] = 2'b01;//地址递增方式传输
assign m_axi_arlock = 1'b0;
assign m_axi_arcache[3:0] = 4'b0000;
assign m_axi_arprot[2:0] = 3'b000;
assign m_axi_arqos[3:0] = 4'b0000;
assign m_axi_arvalid = reg_arvalid;
assign m_axi_rready = m_axi_rvalid;
assign rd_ready = (rd_state == S_RD_IDLE)?1'b1:1'b0;//读空闲
assign rd_fifo_we = m_axi_rvalid;//读fifo的写使能信号
assign rd_fifo_data[63:0] = m_axi_rdata[63:0];//读fifo的写数据信号
// 读状态机
always @(posedge aclk or negedge aresetn) begin
if(!aresetn) begin
rd_state <= S_RD_IDLE;
reg_rd_adrs[32:0] <= 33'd0;
reg_rd_len[31:0] <= 32'd0;
reg_arvalid <= 1'b0;
end else begin
case(rd_state)
S_RD_IDLE: begin//读空闲
if(rd_start) begin//突发触发信号
rd_state <= S_RA_WAIT;
reg_rd_adrs[32:0] <= rd_adrs[32:0];
reg_rd_len[31:0] <= rd_len[9:0] -32'd1;
end
reg_arvalid <= 1'b0;
end
S_RA_WAIT: begin//写地址等待
rd_state <= S_RA_START;
end
S_RA_START: begin//写地址
rd_state <= S_RD_WAIT;
reg_arvalid <= 1'b1;//拉高地址有效
end
S_RD_WAIT: begin //读取数据等待
if(m_axi_arready) begin
rd_state <= S_RD_PROC;
reg_arvalid <= 1'b0;//握手成功就拉低
end
end
S_RD_PROC: begin //接受循环
if(m_axi_rvalid) begin //收到数据有效，握手成功
if(m_axi_rlast) begin //收到最后一个数据
rd_state<= S_RD_DONE;
end
end
end
S_RD_DONE:begin
rd_state <= S_RD_IDLE;
end
endcase
end
end
endmodule

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ddr_general_design.srcs/sources_1/new/old/ddr_axi_wr.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/18 16:15:52
// Design Name:
// Module Name: ddr_axi_wr
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_axi_wr(
input aresetn , //axi复位
input aclk , //axi总时钟
//axi4写通道地址通道
output [3:0] m_axi_awid , //写地址ID，用来标志一组写信号
output [32:0] m_axi_awaddr , //写地址，给出一次写突发传输的写地址
output [7:0] m_axi_awlen , //突发长度，给出突发传输的次数
output [2:0] m_axi_awsize , //突发大小，给出每次突发传输的字节数
output [1:0] m_axi_awburst, //突发类型
output m_axi_awlock , //总线锁信号，可提供操作的原子性
output [3:0] m_axi_awcache, //内存类型，表明一次传输是怎样通过系统的
output [2:0] m_axi_awprot , //保护类型，表明一次传输的特权级及安全等级
output [3:0] m_axi_awqos , //质量服务QoS
output m_axi_awvalid, //有效信号，表明此通道的地址控制信号有效
input m_axi_awready, //表明“从”可以接收地址和对应的控制信号
//axi4写通道数据通道
output [511:0] m_axi_wdata , //写数据
output [7:0] m_axi_wstrb , //写数据有效的字节线
output m_axi_wlast , //表明此次传输是最后一个突发传输
output m_axi_wvalid , //写有效，表明此次写有效
input m_axi_wready , //表明从机可以接收写数据
//axi4写通道应答通道
input [3:0] m_axi_bid , //写响应ID TAG
input [1:0] m_axi_bresp , //写响应，表明写传输的状态
input m_axi_bvalid , //写响应有效
output m_axi_bready , //表明主机能够接收写响应
//用户端信号
input wr_start , //写突发触发信号
input [32:0] wr_adrs , //地址
input [9:0] wr_len , //长度
output wr_ready , //写空闲
output wr_fifo_re , //连接到写fifo的读使能
input [511:0] wr_fifo_data , //连接到fifo的读数据
output wr_done //完成一次突发
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
localparam S_WR_IDLE = 3'd0;//写空闲
localparam S_WA_WAIT = 3'd1;//写地址等待
localparam S_WA_START = 3'd2;//写地址
localparam S_WD_WAIT = 3'd3;//写数据等待
localparam S_WD_PROC = 3'd4;//写数据循环
localparam S_WR_WAIT = 3'd5;//接受写应答
localparam S_WR_DONE = 3'd6;//写结束
//reg define
reg [2:0] wr_state ; //状态寄存器
reg [32:0] reg_wr_adrs; //地址寄存器
reg reg_awvalid; //地址有效握手信号
reg reg_wvalid ; //数据有效握手信号
reg reg_w_last ; //传输最后一个数据
reg [7:0] reg_w_len ; //突发长度最大256，实测128最佳
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//写完成信号的写状态完成
assign wr_done = (wr_state == S_WR_DONE);
//写fifo的读使能为axi数据握手成功
assign wr_fifo_re = ((reg_wvalid & m_axi_wready ));
//只有一个主机，可随意设置
assign m_axi_awid = 4'b1111;
//把地址赋予总线
assign m_axi_awaddr[32:0] = reg_wr_adrs[32:0];
//一次突发传输1长度
assign m_axi_awlen[7:0] = wr_len-'d1;
//表示AXI总线每个数据宽度是8字节，64位
assign m_axi_awsize[2:0] = 3'b011;
//01代表地址递增，10代表递减
assign m_axi_awburst[1:0] = 2'b01;
assign m_axi_awlock = 1'b0;
assign m_axi_awcache[3:0] = 4'b0000;
assign m_axi_awprot[2:0] = 3'b000;
assign m_axi_awqos[3:0] = 4'b0000;
//地址握手信号AWVALID
assign m_axi_awvalid = reg_awvalid;
//fifo数据赋予总线
assign m_axi_wdata[511:0] = wr_fifo_data[511:0];
assign m_axi_wstrb[7:0] = 8'hFF;
//写到最后一个数据
assign m_axi_wlast =(reg_w_len[7:0] == 8'd0)?'b1:'b0;
//数据握手信号WVALID
assign m_axi_wvalid = reg_wvalid;
//这个信号是告诉AXI我收到你的应答
assign m_axi_bready = m_axi_bvalid;
//axi状态机空闲信号
assign wr_ready = (wr_state == S_WR_IDLE)?1'b1:1'b0;
//axi写过程状态机
always @(posedge aclk or negedge aresetn) begin
if(!aresetn) begin
wr_state <= S_WR_IDLE;
reg_wr_adrs[32:0] <= 33'd0;
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b0;
reg_w_last <= 1'b0;
reg_w_len[7:0] <= 8'd0;
end else begin
case(wr_state)
S_WR_IDLE: begin //写空闲
if(wr_start) begin //触发写过程
wr_state <= S_WA_WAIT;
reg_wr_adrs[32:0] <= wr_adrs[32:0];
end
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b0;
reg_w_len[7:0] <= 8'd0;
end
S_WA_WAIT: begin//写地址等待
wr_state <= S_WA_START;//等待一个周期
end
S_WA_START: begin
wr_state <= S_WD_WAIT;//写数据等待
reg_awvalid <= 1'b1; //拉高地址有效信号
reg_wvalid <= 1'b1;//拉高数据有效信号
end
S_WD_WAIT: begin
if(m_axi_awready) begin//等待写地址就绪
wr_state <= S_WD_PROC;
reg_w_len<=wr_len-'d1;//127代表128个长度，0代表1个长度
reg_awvalid <= 1'b0;
end
end
S_WD_PROC: begin//等待AXI写数据就绪信号
if(m_axi_wready) begin//拉高了就可以输出fifo使能信号开始读
if(reg_w_len[7:0] == 8'd0) begin//完成数据写过程
wr_state <= S_WR_WAIT;
reg_wvalid <= 1'b0;//此信号拉低，写fifo读使能无效
reg_w_last<='b1;
//读到最后一个数据，拉高这个标志信号告诉AXI总线这是最后一个
//如果不拉高传输不会成功
end
else begin
reg_w_len[7:0] <= reg_w_len[7:0] -8'd1;
end
end
end
S_WR_WAIT: begin//等待写的AXI应答信号
reg_w_last<='b0;
//M_AXI_BVALID拉高表示写成功，然后状态机完成一次突发传输
if(m_axi_bvalid) begin
wr_state <= S_WR_DONE;
end
end
S_WR_DONE: begin //写完成
wr_state <= S_WR_IDLE;
end
default: begin
wr_state <= S_WR_IDLE;
end
endcase
end
end
endmodule

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ddr_general_design.srcs/sources_1/new/old/ddr_ctrl_top.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/18 13:49:10
// Design Name:
// Module Name: ddr_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_ctrl_top(
// Inouts
inout [63:0] ddr3_dq,
inout [7:0] ddr3_dqs_n,
inout [7:0] ddr3_dqs_p,
// Outputs
output [15:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_cas_n,
output ddr3_ras_n,
output ddr3_we_n,
output ddr3_reset_n,
output [1:0] ddr3_ck_p,
output [1:0] ddr3_ck_n,
output [1:0] ddr3_cke,
output [1:0] ddr3_cs_n,
output [7:0] ddr3_dm,
output [1:0] ddr3_odt,
// Inputs
input sys_clk_i,
output tg_compare_error,
output init_calib_complete,
input sys_rst
);
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
localparam C_S_AXI_ID_WIDTH = 4;
// Width of all master and slave ID signals.
// # = >= 1.
localparam C_S_AXI_ADDR_WIDTH = 33;
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
localparam C_S_AXI_DATA_WIDTH = 512;
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
localparam C_S_AXI_SUPPORTS_NARROW_BURST = 0;
// Indicates whether to instatiate upsizer
// Range: 0, 1
// Output declaration of module ddr_axi_rd
wire [3:0] m_axi_arid;
wire [32:0] m_axi_araddr;
wire [7:0] m_axi_arlen;
wire [2:0] m_axi_arsize;
wire [1:0] m_axi_arburst;
wire [0:0] m_axi_arlock;
wire [3:0] m_axi_arcache;
wire [2:0] m_axi_arprot;
wire [3:0] m_axi_arqos;
wire m_axi_arvalid;
wire m_axi_rready;
wire rd_ready;
wire rd_fifo_we;
wire [511:0] rd_fifo_data;
wire rd_done;
// Output declaration of module ddr_axi_wr
wire [3:0] m_axi_awid;
wire [32:0] m_axi_awaddr;
wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst;
wire m_axi_awlock;
wire [3:0] m_axi_awcache;
wire [2:0] m_axi_awprot;
wire [3:0] m_axi_awqos;
wire m_axi_awvalid;
wire [511:0] m_axi_wdata;
wire [63:0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
wire m_axi_bready;
wire wr_ready;
wire wr_fifo_re;
wire wr_done;
// Slave Interface Write Address Ports
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid;
wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr;
wire [7:0] s_axi_awlen;
wire [2:0] s_axi_awsize;
wire [1:0] s_axi_awburst;
wire [0:0] s_axi_awlock;
wire [3:0] s_axi_awcache;
wire [2:0] s_axi_awprot;
wire s_axi_awvalid;
wire s_axi_awready;
// Slave Interface Write Data Ports
wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb;
wire s_axi_wlast;
wire s_axi_wvalid;
wire s_axi_wready;
// Slave Interface Write Response Ports
wire s_axi_bready;
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
// Slave Interface Read Address Ports
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid;
wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr;
wire [7:0] s_axi_arlen;
wire [2:0] s_axi_arsize;
wire [1:0] s_axi_arburst;
wire [0:0] s_axi_arlock;
wire [3:0] s_axi_arcache;
wire [2:0] s_axi_arprot;
wire s_axi_arvalid;
wire s_axi_arready;
// Slave Interface Read Data Ports
wire s_axi_rready;
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid;
wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rlast;
wire s_axi_rvalid;
fifo_axi_ctrl fifo_axi_ctrl_inst(
.rw_req (rw_req_i ),
.rw_addr (rw_addr_i ),
.rw_fifo_buzy (rw_fifo_buzy_o ),
.rd_length (rd_length_i ),
.wr_data (wr_data_i ),
.wr_mask (wr_mask_i ),
.rw_where (rw_where_i ),
.rw_in_fifo_ack (rw_in_fifo_ack_o ),
.rw_in_fifo_ack_2where (rw_in_fifo_ack_2where_o),
.rd_data (rd_data_o ),
.rd_valid (rd_valid_o ),
.rd_valid_2where (rd_valid_2where_o )
);
ddr_axi_rd u_ddr_axi_rd(
.aresetn (aresetn ),
.aclk (aclk ),
.m_axi_arid (m_axi_arid ),
.m_axi_araddr (m_axi_araddr ),
.m_axi_arlen (m_axi_arlen ),
.m_axi_arsize (m_axi_arsize ),
.m_axi_arburst (m_axi_arburst ),
.m_axi_arlock (m_axi_arlock ),
.m_axi_arcache (m_axi_arcache ),
.m_axi_arprot (m_axi_arprot ),
.m_axi_arqos (m_axi_arqos ),
.m_axi_arvalid (m_axi_arvalid ),
.m_axi_arready (m_axi_arready ),
.m_axi_rid (m_axi_rid ),
.m_axi_rdata (m_axi_rdata ),
.m_axi_rresp (m_axi_rresp ),
.m_axi_rlast (m_axi_rlast ),
.m_axi_rvalid (m_axi_rvalid ),
.m_axi_rready (m_axi_rready ),
.rd_start (rd_start ),
.rd_adrs (rd_adrs ),
.rd_len (rd_len ),
.rd_ready (rd_ready ),
.rd_fifo_we (rd_fifo_we ),
.rd_fifo_data (rd_fifo_data ),
.rd_done (rd_done )
);
ddr_axi_wr u_ddr_axi_wr(
.aresetn (aresetn ),
.aclk (aclk ),
.m_axi_awid (m_axi_awid ),
.m_axi_awaddr (m_axi_awaddr ),
.m_axi_awlen (m_axi_awlen ),
.m_axi_awsize (m_axi_awsize ),
.m_axi_awburst (m_axi_awburst ),
.m_axi_awlock (m_axi_awlock ),
.m_axi_awcache (m_axi_awcache ),
.m_axi_awprot (m_axi_awprot ),
.m_axi_awqos (m_axi_awqos ),
.m_axi_awvalid (m_axi_awvalid ),
.m_axi_awready (m_axi_awready ),
.m_axi_wdata (m_axi_wdata ),
.m_axi_wstrb (m_axi_wstrb ),
.m_axi_wlast (m_axi_wlast ),
.m_axi_wvalid (m_axi_wvalid ),
.m_axi_wready (m_axi_wready ),
.m_axi_bid (m_axi_bid ),
.m_axi_bresp (m_axi_bresp ),
.m_axi_bvalid (m_axi_bvalid ),
.m_axi_bready (m_axi_bready ),
.wr_start (wr_start ),
.wr_adrs (wr_adrs ),
.wr_len (wr_len ),
.wr_ready (wr_ready ),
.wr_fifo_re (wr_fifo_re ),
.wr_fifo_data (wr_fifo_data ),
.wr_done (wr_done )
);
ddr_ctrl ddr_ctrl_inst(
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_reset_n (ddr3_reset_n),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.ui_clk (clk),
.ui_clk_sync_rst (rst),
.mmcm_locked (mmcm_locked),
.aresetn (aresetn),
.app_sr_req (1'b0),
.app_ref_req (1'b0),
.app_zq_req (1'b0),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (4'h0),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (4'h0),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// System Clock Ports
.sys_clk_i (sys_clk_i),
.device_temp (device_temp),
.sys_rst (sys_rst)
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/19 10:25:21
// Design Name:
// Module Name: fifo2axi_convert
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo2axi_convert(
input clk,
input rst,
input [1:0] rw_req ,
input [32:0] rw_addr ,
input [4:0] rd_length ,
input [511:0] wr_data ,
input [63:0] wr_mask ,
input [4:0] rw_where ,
output rw_in_fifo_ack ,
output [4:0] rw_in_fifo_ack_2where,
output rw_fifo_buzy ,
output reg wr_start ,
input wr_ready ,
input wr_fifo_re ,
input wr_done ,
input fifo_ddr_waddr_full,
output reg fifo_ddr_waddr_we,
input fifo_ddr_waddr_empty,
output reg fifo_ddr_waddr_re,
input fifo_ddr_waddr_wack,
input fifo_ddr_waddr_rv,
output rd_start ,
output [32:0] rd_adrs ,
output [9:0] rd_len ,
input rd_ready ,
input rd_fifo_we ,
input rd_done
);
localparam [1:0]
S_IDLE = 2'd0,
S_FIFO_RD = 2'd1,
S_WR_START = 2'd2,
;
reg [1:0] c_state;
reg [1:0] n_state;
always @(posedge clk or posedge rst) begin
if(rst) begin
c_state <= 0;
end
else begin
c_state <= n_state;
end
end
always @(*) begin
wr_start <= 1'b0;
fifo_ddr_waddr_we <= 1'b0;
fifo_ddr_waddr_re <= 1'b0;
case(c_state)
S_IDLE: begin
casex({wr_ready, !fifo_ddr_waddr_empty})
2'b11: begin
n_state <= S_FIFO_RD;
fifo_ddr_waddr_re <= 1'b1;
end
default: begin
n_state = S_IDLE;
end
endcase
end
S_FIFO_RD: begin
n_state <= S_WR_START;
wr_start <= 1'b1;
end
endcase
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/19 10:26:57
// Design Name:
// Module Name: fifo_axi_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo_axi_ctrl(
input clk ,
input rst ,
input [1:0] rw_req ,
input [32:0] rw_addr ,
output rw_fifo_buzy ,
input [4:0] rd_length ,
input [511:0] wr_data ,
input [63:0] wr_mask ,
input [4:0] rw_where ,
output rw_in_fifo_ack ,
output [4:0] rw_in_fifo_ack_2where,
output [511:0] rd_data ,
output rd_valid ,
output [4:0] rd_valid_2where ,
output wr_start ,
output [31:0] wr_adrs ,
output [9:0] wr_len ,
input wr_ready ,
input wr_fifo_re ,
output [63:0] wr_fifo_data ,
input wr_done ,
output rd_start ,
output [32:0] rd_adrs ,
output [9:0] rd_len ,
input rd_ready ,
input rd_fifo_we ,
input [63:0] rd_fifo_data,
input rd_done
);
fifo2axi_convert fifo2axi_convert_inst(
.clk (clk),
.rst (rst),
.rw_req (),
.rw_addr (),
.rd_length (),
.wr_data (),
.wr_mask (),
.rw_where (),
.rw_in_fifo_ack (),
.rw_in_fifo_ack_2where (),
.rw_fifo_buzy (),
.wr_start (),
.wr_adrs (),
.wr_len (),
.wr_ready (),
.wr_fifo_re (),
.wr_fifo_data (),
.wr_done (),
.rd_start (),
.rd_adrs (),
.rd_len (),
.rd_ready (),
.rd_fifo_we (),
.rd_fifo_data (),
.rd_done ()
);
axi2fifo_convert axi2fifo_convert_inst(
);
fifo_ddr_addr fifo_ddr_waddr_inst(
.clk (clk),
.srst (rst),
.full (fifo_ddr_waddr_full),
.din (fifo_ddr_waddr_din),
.wr_en (fifo_ddr_waddr_we),
.empty (fifo_ddr_waddr_empty),
.dout (fifo_ddr_waddr_dout),
.rd_en (fifo_ddr_waddr_re),
.wr_ack (fifo_ddr_waddr_wack),
.valid (fifo_ddr_waddr_rv)
);
fifo_ddr_data fifo_ddr_wdata_inst(
.clk (clk),
.srst (rst),
.full (fifo_ddr_wdata_full),
.din (fifo_ddr_wdata_din),
.wr_en (fifo_ddr_wdata_we),
.empty (fifo_ddr_wdata_empty),
.dout (fifo_ddr_wdata_dout),
.rd_en (fifo_ddr_wdata_re),
.wr_ack (fifo_ddr_wdata_wack),
.valid (fifo_ddr_wdata_rv)
);
fifo_ddr_addr fifo_ddr_raddr_inst(
.clk (clk),
.srst (rst),
.full (fifo_ddr_raddr_full),
.din (fifo_ddr_raddr_din),
.wr_en (fifo_ddr_raddr_we),
.empty (fifo_ddr_raddr_empty),
.dout (fifo_ddr_raddr_dout),
.rd_en (fifo_ddr_raddr_re),
.wr_ack (fifo_ddr_raddr_wack),
.valid (fifo_ddr_raddr_rv)
);
fifo_ddr_data fifo_ddr_rdata_inst(
.clk (clk),
.srst (srst),
.full (fifo_ddr_rdata_full),
.din (fifo_ddr_rdata_din),
.wr_en (fifo_ddr_rdata_we),
.empty (fifo_ddr_rdata_empty),
.dout (fifo_ddr_rdata_dout),
.rd_en (fifo_ddr_rdata_re),
.wr_ack (fifo_ddr_rdata_wack),
.valid (fifo_ddr_rdata_rv)
);
fifo_ddr_info fifo_ddr_info_inst(
.clk (clk),
.srst (rst),
.full (fifo_ddr_info_full),
.din (fifo_ddr_info_din),
.wr_en (fifo_ddr_info_we),
.empty (fifo_ddr_info_empty),
.dout (fifo_ddr_info_dout),
.rd_en (fifo_ddr_info_re),
.wr_ack (fifo_ddr_info_wack),
.valid (fifo_ddr_info_rv)
);
endmodule