FPGALab/ddr3_general_design
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fix fifo ctrl bug

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包焕垲
2025-05-16 16:27:46 +08:00
parent b6dea8b6e0
commit 43b95e063d
2 changed files with 24 additions and 46 deletions
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20
ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v
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@@ -140,14 +140,14 @@ module ddr_axi_m_top #(
wire fifo_ddr_wstrb_full;
assign fifo_ddr_rd_almost_full_o = fifo_ddr_rd_addr_almost_full & fifo_ddr_rd_len_almost_full;
assign fifo_ddr_rd_full_o = fifo_ddr_rd_addr_full & fifo_ddr_rd_len_full;
assign fifo_ddr_rd_almost_full_o = fifo_ddr_rd_addr_almost_full | fifo_ddr_rd_len_almost_full;
assign fifo_ddr_rd_full_o = fifo_ddr_rd_addr_full | fifo_ddr_rd_len_full;
assign fifo_ddr_wr_almost_full_o = fifo_ddr_wr_addr_almost_full & fifo_ddr_wr_len_almost_full;
assign fifo_ddr_wr_full_o = fifo_ddr_wr_addr_full & fifo_ddr_wr_len_full;
assign fifo_ddr_wr_almost_full_o = fifo_ddr_wr_addr_almost_full | fifo_ddr_wr_len_almost_full;
assign fifo_ddr_wr_full_o = fifo_ddr_wr_addr_full | fifo_ddr_wr_len_full;
assign fifo_ddr_wdata_almost_full_o = fifo_ddr_wdata_almost_full & fifo_ddr_wstrb_almost_full;
assign fifo_ddr_wdata_full_o = fifo_ddr_wdata_full & fifo_ddr_wstrb_full;
assign fifo_ddr_wdata_almost_full_o = fifo_ddr_wdata_almost_full | fifo_ddr_wstrb_almost_full;
assign fifo_ddr_wdata_full_o = fifo_ddr_wdata_full | fifo_ddr_wstrb_full;
ddr_axi_m_rd #(
.ADDR_WIDTH (ADDR_WIDTH ),
@@ -173,9 +173,9 @@ module ddr_axi_m_top #(
.m_axi_rresp_i (m_axi_rresp_i ),
.m_axi_rlast_i (m_axi_rlast_i ),
.m_axi_rvalid_i (m_axi_rvalid_i ),
.fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty & fifo_ddr_rd_len_empty),
.fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty | fifo_ddr_rd_len_empty),
.fifo_ddr_rd_rd_en_o (fifo_ddr_rd_rd_en ),
.fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v ),
.fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v),
.fifo_ddr_rd_addr_i (fifo_ddr_rd_addr ),
.fifo_ddr_rd_len_i (fifo_ddr_rd_len ),
.fifo_ddr_rdata_almost_full_i (fifo_ddr_rdata_almost_full ),
@@ -211,12 +211,12 @@ module ddr_axi_m_top #(
.m_axi_bid_i (m_axi_bid_i ),
.m_axi_bresp_i (m_axi_bresp_i ),
.m_axi_bvalid_i (m_axi_bvalid_i ),
.fifo_ddr_wr_empty_i (fifo_ddr_wr_addr_empty & fifo_ddr_wr_len_empty),
.fifo_ddr_wr_empty_i (fifo_ddr_wr_addr_empty | fifo_ddr_wr_len_empty),
.fifo_ddr_wr_rd_en_o (fifo_ddr_wr_rd_en ),
.fifo_ddr_wr_v_i (fifo_ddr_wr_addr_v & fifo_ddr_wr_len_v),
.fifo_ddr_wr_addr_i (fifo_ddr_wr_addr ),
.fifo_ddr_wr_len_i (fifo_ddr_wr_len ),
.fifo_ddr_wdata_empty_i (fifo_ddr_wdata_empty & fifo_ddr_wstrb_empty),
.fifo_ddr_wdata_empty_i (fifo_ddr_wdata_empty | fifo_ddr_wstrb_empty),
.fifo_ddr_wdata_rd_en_o (fifo_ddr_wdata_rd_en ),
.fifo_ddr_wdata_v_i (fifo_ddr_wdata_v & fifo_ddr_wstrb_v),
.fifo_ddr_wdata_i (fifo_ddr_wdata ),