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包焕垲
2025-01-06 22:30:12 +08:00
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ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_module.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/01/06 15:49:11
// Design Name:
// Module Name: ddr3_ctrl_module
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr3_ctrl_module(
// Clock and reset signals
input sys_clk_i,
input sys_rst_i,
input ui_clk_i,
input ui_rst_i,
// Read & Write interface signals
input [ 1:0] rw_req_i,
output rw_ack_o,
output rw_full_o,
output rd_valid_o,
output rd_empty_o,
// User interface signals
output [ 28:0] app_addr_o,
output [ 2:0] app_cmd_o,
output app_en_o,
output [511:0] app_wdf_data_o,
output app_wdf_end_o,
output [ 63:0] app_wdf_mask_o,
output app_wdf_wren_o,
input [511:0] app_rd_data_i,
input app_rd_data_end_i,
input app_rd_data_valid_i,
input app_rdy_i,
input app_wdf_rdy_i
);
wire wr_req_i;
wire rd_req_i;
wire [ 2:0] cmd_fifo_din;
wire cmd_fifo_we;
wire cmd_fifo_full;
wire [ 2:0] cmd_fifo_dout;
wire cmd_fifo_re;
wire cmd_fifo_empty;
wire [ 28:0] addr_i_fifo_din;
wire addr_i_fifo_we;
wire addr_i_fifo_full;
wire [ 28:0] addr_i_fifo_dout;
wire addr_i_fifo_re;
wire addr_i_fifo_empty;
wire [511:0] wdata_fifo_din;
wire wdata_fifo_we;
wire wdata_fifo_full;
wire [511:0] wdata_fifo_dout;
wire wdata_fifo_re;
wire wdata_fifo_empty;
// Instantiate the module
ddr3_wr_ctrl ddr3_wr_ctrl_inst(
.sys_clk_i (sys_clk_i),
.sys_rst_i (sys_rst_i),
.ui_clk_i (ui_clk_i),
.ui_rst_i (ui_rst_i),
.rw_req_i (rw_req_i),
.rw_full_o (rw_full_o),
.cmd_fifo_full_i (cmd_fifo_full),
.addr_i_fifo_full_i (addr_i_fifo_full),
.wdata_fif_full_i (wdata_fifo_full),
.cmd_fifo_empty_i (cmd_fifo_empty),
.addr_i_fifo_empty_i (addr_i_fifo_empty),
.wdata_fifo_empty_i (wdata_fifo_empty),
.cmd_fifo_we_o (cmd_fifo_we),
.cmd_fifo_re_o (cmd_fifo_re),
.addr_i_fifo_we_o (addr_i_fifo_we),
.addr_i_fifo_re_o (addr_i_fifo_re),
.wdata_fifo_we_o (wdata_fifo_we),
.wdata_fifo_re_o (wdata_fifo_re)
);
// Instantiate the module
ddr3_cmd_fifo ddr3_cmd_fifo_inst (
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.din (cmd_fifo_din),
.wr_en (cmd_fifo_we),
.full (cmd_fifo_full),
.dout (cmd_fifo_dout),
.rd_en (cmd_fifo_re),
.empty (cmd_fifo_empty)
);
// Instantiate the module
ddr3_info_fifo ddr3_info_i_fifo_inst (
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.din (addr_i_fifo_din),
.wr_en (addr_i_fifo_we),
.full (addr_i_fifo_full),
.dout (addr_i_fifo_dout),
.rd_en (addr_i_fifo_re),
.empty (addr_i_fifo_empty)
);
// Instantiate the module
ddr3_data_fifo ddr3_wdata_fifo_inst (
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.din (wdata_fifo_din),
.wr_en (wdata_fifo_we),
.full (wdata_fifo_full),
.dout (wdata_fifo_dout),
.rd_en (wdata_fifo_re),
.empty (wdata_fifo_empty)
);
// Instantiate the module
ddr3_rd_ctrl ddr3_rd_ctrl_inst();
// Instantiate the module
ddr3_info_fifo ddr3_info_o_fifo_inst (
.wr_clk (ui_clk_i),
.rd_clk (sys_clk_i),
.rst (ui_rst_i),
.din (),
.wr_en (),
.full (),
.dout (),
.rd_en (),
.empty ()
);
// Instantiate the module
ddr3_data_fifo ddr3_rdata_fifo_inst (
.wr_clk (ui_clk_i),
.rd_clk (sys_clk_i),
.rst (ui_rst_i),
.din (),
.wr_en (),
.full (),
.dout (),
.rd_en (),
.empty ()
);
endmodule

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ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_top.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/01/06 13:54:40
// Design Name:
// Module Name: ddr3_ctrl_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr3_ctrl_top(
// Clock and reset signals
input sys_clk_i, // 200MHz
input sys_rst_i, // Active high
// System signals
output init_calib_complete_0_o, // Once the DDR initialization is complete, the signal will be set to 1
output init_calib_complete_1_o, // same as above
// User interface signals
input [ 1:0] ddr3_0_rw_req_i, // 01: Write, 10: Read, 00 or 11: Idle
input [ 34:0] ddr3_0_rw_info_i, // Info in (1 Ctrl Signal + 5 Scr ID + 29 Address)
input [ 63:0] ddr3_0_wr_mask_i, // Mask in
input [511:0] ddr3_0_wr_data_i, // Data in
output ddr3_0_rw_ack_o, // Read/Write acknowledge
output ddr3_0_rw_full_o, // Write FIFO full when up to 32
output [ 28:0] ddr3_0_rd_info_o, // Info out
output [511:0] ddr3_0_rd_data_o, // Data out
output ddr3_0_rd_valid_o, // Read data & addr & id valid
output ddr3_0_rd_empty_o, // Read FIFO empty
input [ 1:0] ddr3_1_rw_req_i, // 01: Write, 10: Read, 00 or 11: Idle
input [ 34:0] ddr3_1_rw_info_i, // Info in
input [ 63:0] ddr3_1_wr_mask_i, // Mask in
input [511:0] ddr3_1_wr_data_i, // Data in
output ddr3_1_rw_ack_o, // Read/Write acknowledge
output ddr3_1_rw_full_o, // Write FIFO full when up to 32
output [ 98:0] ddr3_1_rd_info_o, // Info out
output [511:0] ddr3_1_rd_data_o, // Data out
output ddr3_1_rd_valid_o, // Read data & info valid
output ddr3_1_rd_empty_o, // Read FIFO empty
// DDR3 interface signals
inout [ 63:0] ddr3_0_dq_io,
inout [ 7:0] ddr3_0_dqs_n_io,
inout [ 7:0] ddr3_0_dqs_p_io,
output [ 14:0] ddr3_0_addr_o,
output [ 2:0] ddr3_0_ba_o,
output ddr3_0_ras_n_o,
output ddr3_0_cas_n_o,
output ddr3_0_we_n_o,
output ddr3_0_reset_n_o,
output [ 0:0] ddr3_0_ck_p_o,
output [ 0:0] ddr3_0_ck_n_o,
output [ 0:0] ddr3_0_cke_o,
output [ 0:0] ddr3_0_cs_n_o,
output [ 7:0] ddr3_0_dm_o,
output [ 0:0] ddr3_0_odt_o,
inout [ 63:0] ddr3_1_dq_io,
inout [ 7:0] ddr3_1_dqs_n_io,
inout [ 7:0] ddr3_1_dqs_p_io,
output [ 14:0] ddr3_1_addr_o,
output [ 2:0] ddr3_1_ba_o,
output ddr3_1_ras_n_o,
output ddr3_1_cas_n_o,
output ddr3_1_we_n_o,
output ddr3_1_reset_n_o,
output [ 0:0] ddr3_1_ck_p_o,
output [ 0:0] ddr3_1_ck_n_o,
output [ 0:0] ddr3_1_cke_o,
output [ 0:0] ddr3_1_cs_n_o,
output [ 7:0] ddr3_1_dm_o,
output [ 0:0] ddr3_1_odt_o
);
// Internal DDR3 user interface signals
wire ui_0_clk;
wire ui_0_clk_sync_rst;
wire [ 28:0] app_0_addr;
wire [ 2:0] app_0_cmd;
wire app_0_en;
wire [511:0] app_0_wdf_data;
wire app_0_wdf_end;
wire [ 63:0] app_0_wdf_mask;
wire app_0_wdf_wren;
wire [511:0] app_0_rd_data;
wire app_0_rd_data_end;
wire app_0_rd_data_valid;
wire app_0_rdy;
wire app_0_wdf_rdy;
wire app_0_sr_req;
wire app_0_ref_req;
wire app_0_zq_req;
wire app_0_sr_active;
wire app_0_ref_ack;
wire app_0_zq_ack;
wire ui_1_clk;
wire ui_1_clk_sync_rst;
wire [ 28:0] app_1_addr;
wire [ 2:0] app_1_cmd;
wire app_1_en;
wire [511:0] app_1_wdf_data;
wire app_1_wdf_end;
wire [ 63:0] app_1_wdf_mask;
wire app_1_wdf_wren;
wire [511:0] app_1_rd_data;
wire app_1_rd_data_end;
wire app_1_rd_data_valid;
wire app_1_rdy;
wire app_1_wdf_rdy;
wire app_1_sr_req;
wire app_1_ref_req;
wire app_1_zq_req;
wire app_1_sr_active;
wire app_1_ref_ack;
wire app_1_zq_ack;
assign app_0_sr_req = 1'b0;
assign app_0_ref_req = 1'b0;
assign app_0_zq_req = 1'b0;
assign app_1_sr_req = 1'b0;
assign app_1_ref_req = 1'b0;
assign app_1_zq_req = 1'b0;
// Instantiate the DDR3 controller
ddr3_ctrl_0 ddr3_ctrl_0_inst (
.sys_clk_i (sys_clk_i ),
.sys_rst (sys_rst_i ),
.ddr3_addr (ddr3_0_dq_io ),
.ddr3_ba (ddr3_0_dqs_n_io ),
.ddr3_cas_n (ddr3_0_dqs_p_io ),
.ddr3_ck_n (ddr3_0_addr_o ),
.ddr3_ck_p (ddr3_0_ba_o ),
.ddr3_cke (ddr3_0_ras_n_o ),
.ddr3_ras_n (ddr3_0_cas_n_o ),
.ddr3_reset_n (ddr3_0_we_n_o ),
.ddr3_we_n (ddr3_0_reset_n_o ),
.ddr3_dq (ddr3_0_ck_p_o ),
.ddr3_dqs_n (ddr3_0_ck_n_o ),
.ddr3_dqs_p (ddr3_0_cke_o ),
.ddr3_cs_n (ddr3_0_cs_n_o ),
.ddr3_dm (ddr3_0_dm_o ),
.ddr3_odt (ddr3_0_odt_o ),
.init_calib_complete (init_calib_complete_0_o),
.ui_clk (ui_0_clk ),
.ui_clk_sync_rst (ui_0_clk_sync_rst ),
.app_addr (app_0_addr ),
.app_cmd (app_0_cmd ),
.app_en (app_0_en ),
.app_wdf_data (app_0_wdf_data ),
.app_wdf_end (app_0_wdf_end ),
.app_wdf_mask (app_0_wdf_mask ),
.app_wdf_wren (app_0_wdf_wren ),
.app_rd_data (app_0_rd_data ),
.app_rd_data_end (app_0_rd_data_end ),
.app_rd_data_valid (app_0_rd_data_valid ),
.app_rdy (app_0_rdy ),
.app_wdf_rdy (app_0_wdf_rdy ),
.app_sr_req (app_0_sr_req ),
.app_ref_req (app_0_ref_req ),
.app_zq_req (app_0_zq_req ),
.app_sr_active (app_0_sr_active ),
.app_ref_ack (app_0_ref_ack ),
.app_zq_ack (app_0_zq_ack )
);
// Instantiate the DDR3 controller
ddr3_ctrl_1 ddr3_ctrl_1_inst (
.sys_clk_i (sys_clk_i ),
.sys_rst (sys_rst_i ),
.ddr3_addr (ddr3_1_dq_io ),
.ddr3_ba (ddr3_1_dqs_n_io ),
.ddr3_cas_n (ddr3_1_dqs_p_io ),
.ddr3_ck_n (ddr3_1_addr_o ),
.ddr3_ck_p (ddr3_1_ba_o ),
.ddr3_cke (ddr3_1_ras_n_o ),
.ddr3_ras_n (ddr3_1_cas_n_o ),
.ddr3_reset_n (ddr3_1_we_n_o ),
.ddr3_we_n (ddr3_1_reset_n_o ),
.ddr3_dq (ddr3_1_ck_p_o ),
.ddr3_dqs_n (ddr3_1_ck_n_o ),
.ddr3_dqs_p (ddr3_1_cke_o ),
.ddr3_cs_n (ddr3_1_cs_n_o ),
.ddr3_dm (ddr3_1_dm_o ),
.ddr3_odt (ddr3_1_odt_o ),
.init_calib_complete (init_calib_complete_1_o),
.ui_clk (ui_1_clk ),
.ui_clk_sync_rst (ui_1_clk_sync_rst ),
.app_addr (app_1_addr ),
.app_cmd (app_1_cmd ),
.app_en (app_1_en ),
.app_wdf_data (app_1_wdf_data ),
.app_wdf_end (app_1_wdf_end ),
.app_wdf_mask (app_1_wdf_mask ),
.app_wdf_wren (app_1_wdf_wren ),
.app_rd_data (app_1_rd_data ),
.app_rd_data_end (app_1_rd_data_end ),
.app_rd_data_valid (app_1_rd_data_valid ),
.app_rdy (app_1_rdy ),
.app_wdf_rdy (app_1_wdf_rdy ),
.app_sr_req (app_1_sr_req ),
.app_ref_req (app_1_ref_req ),
.app_zq_req (app_1_zq_req ),
.app_sr_active (app_1_sr_active ),
.app_ref_ack (app_1_ref_ack ),
.app_zq_ack (app_1_zq_ack )
);
endmodule

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ddr3_general_design.srcs/sources_1/new/ddr3_rd_ctrl.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/01/06 16:25:28
// Design Name:
// Module Name: ddr3_rd_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr3_rd_ctrl(
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/01/06 16:58:22
// Design Name:
// Module Name: ddr3_rd_fifo_rd_fsm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr3_rd_fifo_rd_fsm(
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/01/06 16:58:22
// Design Name:
// Module Name: ddr3_rd_fifo_wr_fsm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr3_rd_fifo_wr_fsm(
);
endmodule

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ddr3_general_design.srcs/sources_1/new/ddr3_wr_ctrl.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/01/06 16:25:28
// Design Name:
// Module Name: ddr3_wr_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr3_wr_ctrl(
input sys_clk_i,
input sys_rst_i,
input ui_clk_i,
input ui_rst_i,
input [1:0] rw_req_i,
output rw_full_o,
input cmd_fifo_full_i,
input addr_i_fifo_full_i,
input wdata_fifo_full_i,
input cmd_fifo_empty_i,
input addr_i_fifo_empty_i,
input wdata_fifo_empty_i,
output cmd_fifo_we_o,
output cmd_fifo_re_o,
output addr_i_fifo_we_o,
output addr_i_fifo_re_o,
output wdata_fifo_we_o,
output wdata_fifo_re_o
);
// Instantiate the module
ddr3_wr_fifo_wr_fsm ddr3_wr_fifo_wr_fsm_inst (
.sys_clk_i (sys_clk_i),
.sys_rst_i (sys_rst_i),
.ui_clk_i (ui_clk_i),
.ui_rst_i (ui_rst_i),
.rw_req_i (rw_req_i),
.rw_full_o (rw_full_o),
.cmd_fifo_full_i (cmd_fifo_full_i),
.addr_i_fifo_full_i (addr_i_fifo_full_i),
.wdata_fif_full_i (wdata_fifo_full_i),
.cmd_fifo_we_o (cmd_fifo_we_o),
.addr_i_fifo_we_o (addr_i_fifo_we_o),
.wdata_fifo_we_o (wdata_fifo_we_o)
);
// Instantiate the module
ddr3_wr_fifo_rd_fsm ddr3_wr_fifo_rd_fsm_inst (
.sys_clk_i (sys_clk_i),
.sys_rst_i (sys_rst_i),
.ui_clk_i (ui_clk_i),
.ui_rst_i (ui_rst_i),
.cmd_fifo_empty (cmd_fifo_empty_i),
.addr_i_fifo_empty (addr_i_fifo_empty_i),
.wdata_fifo_empty (wdata_fifo_empty_i),
.cmd_fifo_re_o (cmd_fifo_re_o),
.addr_i_fifo_re_o (addr_i_fifo_re_o),
.wdata_fifo_re_o (wdata_fifo_re_o)
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/01/06 16:58:22
// Design Name:
// Module Name: ddr3_wr_fifo_rd_fsm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr3_wr_fifo_rd_fsm(
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/01/06 16:58:22
// Design Name:
// Module Name: ddr3_wr_fifo_wr_fsm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr3_wr_fifo_wr_fsm(
input sys_clk_i,
input sys_rst_i,
input ui_clk_i,
input ui_rst_i,
input [1:0] rw_req_i,
output rw_full_o,
input cmd_fifo_full_i,
input addr_i_fifo_full_i,
input wdata_fifo_full_i,
output [1:0] cmd_fifo_din_sel_o,
output cmd_fifo_we_o,
output addr_i_fifo_we_o,
output wdata_fifo_we_o
);
localparam [1:0]
S_IDLE = 2'b00,
S_FIFO_WRITE = 2'b01,
S_FIFO_WAIT = 2'b10;
reg [1:0] c_state;
reg [1:0] n_state;
always @(posedge sys_clk_i or negedge sys_rst_i) begin
if (sys_rst_i) begin
c_state <= S_IDLE;
end
else begin
c_state <= n_state;
end
end
always @(*) begin
case (c_state)
S_IDLE: begin
if(rw_req_i == 2'b10 || rw_req_i == 2'b01) begin
n_state = S_FIFO_WRITE;
end
else begin
n_state = S_IDLE;
end
end
S_FIFO_WRITE: begin
if (cmd_fifo_full_i || addr_i_fifo_full_i || wdata_fifo_full_i) begin
n_state = S_FIFO_WAIT;
end
else begin
n_state = S_FIFO_WRITE;
end
end
S_FIFO_WAIT: begin
if (!cmd_fifo_full_i && !addr_i_fifo_full_i && !wdata_fifo_full_i) begin
n_state = S_FIFO_WRITE;
end
else begin
n_state = S_FIFO_WAIT;
end
end
default: begin
n_state = S_IDLE;
end
endcase;
end
endmodule