commit 30fa4e98fe34e2a63b57f259b2330687092812dd Author: UnbalancedCat Date: Mon Jan 6 22:30:12 2025 +0800 first commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..67e2457 --- /dev/null +++ b/.gitignore @@ -0,0 +1,20 @@ +* +!*/ + +# track this file or dic +!.gitignore +!readme.md + +doc/** +!others/** + +# vivado +!ddr3_general_design.xpr + +## srcs +!ddr3_general_design.srcs/constrs_1/** + +!ddr3_general_design.srcs/sources_1/ip/*/*.xci +!ddr3_general_design.srcs/sources_1/ip/*/*.coe + +!ddr3_general_design.srcs/sources_1/new/** \ No newline at end of file diff --git a/ddr3_general_design.srcs/constrs_1/ddr3_0.ucf b/ddr3_general_design.srcs/constrs_1/ddr3_0.ucf new file mode 100644 index 0000000..1a4a0f9 --- /dev/null +++ b/ddr3_general_design.srcs/constrs_1/ddr3_0.ucf @@ -0,0 +1,117 @@ +NET "clk_ref_n" LOC = "T39" | IOSTANDARD = DIFF_SSTL135 | VCCAUX_IO = DONTCARE ; +NET "clk_ref_p" LOC = "U39" | IOSTANDARD = DIFF_SSTL135 | VCCAUX_IO = DONTCARE ; +NET "ddr3_addr[0]" LOC = "T40" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[10]" LOC = "P32" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[11]" LOC = "W42" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[12]" LOC = "N33" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[13]" LOC = "W33" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[14]" LOC = "U41" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[1]" LOC = "P35" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[2]" LOC = "U33" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[3]" LOC = "U34" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[4]" LOC = "N34" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[5]" LOC = "U32" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[6]" LOC = "T42" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[7]" LOC = "V38" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[8]" LOC = "R34" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[9]" LOC = "V41" | | VCCAUX_IO = HIGH ; +NET "ddr3_ba[0]" LOC = "T36" | | VCCAUX_IO = HIGH ; +NET "ddr3_ba[1]" LOC = "R33" | | VCCAUX_IO = HIGH ; +NET "ddr3_ba[2]" LOC = "T34" | | VCCAUX_IO = HIGH ; +NET "ddr3_cas_n" LOC = "P37" | | VCCAUX_IO = HIGH ; +NET "ddr3_ck_n[0]" LOC = "U38" | | VCCAUX_IO = HIGH ; +NET "ddr3_ck_p[0]" LOC = "U37" | | VCCAUX_IO = HIGH ; +NET "ddr3_cke[0]" LOC = "R32" | | VCCAUX_IO = HIGH ; +NET "ddr3_cs_n[0]" LOC = "R35" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[0]" LOC = "F41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[1]" LOC = "B41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[2]" LOC = "AG42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[3]" LOC = "AK40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[4]" LOC = "L41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[5]" LOC = "R40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[6]" LOC = "AA40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[7]" LOC = "AD42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[0]" LOC = "H41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[10]" LOC = "A40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[11]" LOC = "F42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[12]" LOC = "C40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[13]" LOC = "E40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[14]" LOC = "B42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[15]" LOC = "D40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[16]" LOC = "AJ38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[17]" LOC = "AF39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[18]" LOC = "AH38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[19]" LOC = "AF42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[1]" LOC = "H39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[20]" LOC = "AG38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[21]" LOC = "AF40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[22]" LOC = "AK38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[23]" LOC = "AF41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[24]" LOC = "AH41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[25]" LOC = "AJ41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[26]" LOC = "AH40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[27]" LOC = "AL39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[28]" LOC = "AK42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[29]" LOC = "AK39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[2]" LOC = "J41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[30]" LOC = "AJ42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[31]" LOC = "AJ40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[32]" LOC = "L40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[33]" LOC = "M42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[34]" LOC = "K37" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[35]" LOC = "L42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[36]" LOC = "L39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[37]" LOC = "K38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[38]" LOC = "M36" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[39]" LOC = "M41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[3]" LOC = "F40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[40]" LOC = "M39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[41]" LOC = "P41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[42]" LOC = "M38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[43]" LOC = "N38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[44]" LOC = "N40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[45]" LOC = "N39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[46]" LOC = "M37" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[47]" LOC = "P40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[48]" LOC = "AB42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[49]" LOC = "AA42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[4]" LOC = "K39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[50]" LOC = "AB39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[51]" LOC = "Y40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[52]" LOC = "AB41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[53]" LOC = "W40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[54]" LOC = "AB38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[55]" LOC = "Y42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[56]" LOC = "AC40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[57]" LOC = "AE42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[58]" LOC = "AC38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[59]" LOC = "AE39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[5]" LOC = "G39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[60]" LOC = "AC41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[61]" LOC = "AE40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[62]" LOC = "AC39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[63]" LOC = "AD40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[6]" LOC = "J40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[7]" LOC = "H40" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[8]" LOC = "A41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[9]" LOC = "E42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[0]" LOC = "G42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[1]" LOC = "D42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[2]" LOC = "AH39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[3]" LOC = "AL42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[4]" LOC = "J42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[5]" LOC = "P42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[6]" LOC = "AA39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[7]" LOC = "AE38" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[0]" LOC = "G41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[1]" LOC = "D41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[2]" LOC = "AG39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[3]" LOC = "AL41" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[4]" LOC = "K42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[5]" LOC = "R42" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[6]" LOC = "Y39" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[7]" LOC = "AD38" | | VCCAUX_IO = HIGH ; +NET "ddr3_odt[0]" LOC = "R37" | | VCCAUX_IO = HIGH ; +NET "ddr3_ras_n" LOC = "P36" | | VCCAUX_IO = HIGH ; +NET "ddr3_reset_n" LOC = "W38" | | VCCAUX_IO = HIGH ; +NET "ddr3_we_n" LOC = "P38" | | VCCAUX_IO = HIGH ; diff --git a/ddr3_general_design.srcs/constrs_1/ddr3_1.ucf b/ddr3_general_design.srcs/constrs_1/ddr3_1.ucf new file mode 100644 index 0000000..093ac78 --- /dev/null +++ b/ddr3_general_design.srcs/constrs_1/ddr3_1.ucf @@ -0,0 +1,115 @@ +NET "ddr3_addr[0]" LOC = "A35" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[10]" LOC = "J37" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[11]" LOC = "D32" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[12]" LOC = "F35" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[13]" LOC = "G38" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[14]" LOC = "B32" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[1]" LOC = "E32" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[2]" LOC = "B36" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[3]" LOC = "C39" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[4]" LOC = "G33" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[5]" LOC = "A39" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[6]" LOC = "G36" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[7]" LOC = "B39" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[8]" LOC = "H38" | | VCCAUX_IO = HIGH ; +NET "ddr3_addr[9]" LOC = "A36" | | VCCAUX_IO = HIGH ; +NET "ddr3_ba[0]" LOC = "C38" | | VCCAUX_IO = HIGH ; +NET "ddr3_ba[1]" LOC = "J36" | | VCCAUX_IO = HIGH ; +NET "ddr3_ba[2]" LOC = "B34" | | VCCAUX_IO = HIGH ; +NET "ddr3_cas_n" LOC = "B33" | | VCCAUX_IO = HIGH ; +NET "ddr3_ck_n[0]" LOC = "D36" | | VCCAUX_IO = HIGH ; +NET "ddr3_ck_p[0]" LOC = "D35" | | VCCAUX_IO = HIGH ; +NET "ddr3_cke[0]" LOC = "J38" | | VCCAUX_IO = HIGH ; +NET "ddr3_cs_n[0]" LOC = "A37" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[0]" LOC = "K27" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[1]" LOC = "H23" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[2]" LOC = "N29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[3]" LOC = "V31" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[4]" LOC = "K23" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[5]" LOC = "M27" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[6]" LOC = "J32" | | VCCAUX_IO = HIGH ; +NET "ddr3_dm[7]" LOC = "H31" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[0]" LOC = "G28" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[10]" LOC = "J21" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[11]" LOC = "G27" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[12]" LOC = "G22" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[13]" LOC = "G26" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[14]" LOC = "G21" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[15]" LOC = "H24" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[16]" LOC = "M31" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[17]" LOC = "N28" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[18]" LOC = "P30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[19]" LOC = "P28" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[1]" LOC = "K25" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[20]" LOC = "N31" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[21]" LOC = "R28" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[22]" LOC = "R30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[23]" LOC = "N30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[24]" LOC = "U29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[25]" LOC = "W31" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[26]" LOC = "V29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[27]" LOC = "Y29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[28]" LOC = "U31" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[29]" LOC = "Y30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[2]" LOC = "G29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[30]" LOC = "V30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[31]" LOC = "W30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[32]" LOC = "M24" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[33]" LOC = "J22" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[34]" LOC = "L25" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[35]" LOC = "K22" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[36]" LOC = "L24" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[37]" LOC = "M21" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[38]" LOC = "L26" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[39]" LOC = "J23" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[3]" LOC = "K24" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[40]" LOC = "N25" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[41]" LOC = "N26" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[42]" LOC = "P21" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[43]" LOC = "L27" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[44]" LOC = "N24" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[45]" LOC = "P26" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[46]" LOC = "N23" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[47]" LOC = "P25" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[48]" LOC = "L34" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[49]" LOC = "J35" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[4]" LOC = "K28" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[50]" LOC = "M34" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[51]" LOC = "J33" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[52]" LOC = "L35" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[53]" LOC = "H34" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[54]" LOC = "M33" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[55]" LOC = "K35" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[56]" LOC = "J30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[57]" LOC = "J31" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[58]" LOC = "K30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[59]" LOC = "L32" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[5]" LOC = "J25" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[60]" LOC = "H30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[61]" LOC = "M32" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[62]" LOC = "K29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[63]" LOC = "L31" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[6]" LOC = "J28" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[7]" LOC = "J27" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[8]" LOC = "H21" | | VCCAUX_IO = HIGH ; +NET "ddr3_dq[9]" LOC = "G24" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[0]" LOC = "H29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[1]" LOC = "H26" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[2]" LOC = "M29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[3]" LOC = "T30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[4]" LOC = "L22" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[5]" LOC = "P23" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[6]" LOC = "K34" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[7]" LOC = "L30" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[0]" LOC = "H28" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[1]" LOC = "H25" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[2]" LOC = "M28" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[3]" LOC = "T29" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[4]" LOC = "M22" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[5]" LOC = "P22" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[6]" LOC = "K33" | | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[7]" LOC = "L29" | | VCCAUX_IO = HIGH ; +NET "ddr3_odt[0]" LOC = "E39" | | VCCAUX_IO = HIGH ; +NET "ddr3_ras_n" LOC = "E33" | | VCCAUX_IO = HIGH ; +NET "ddr3_reset_n" LOC = "B37" | | VCCAUX_IO = HIGH ; +NET "ddr3_we_n" LOC = "A34" | | VCCAUX_IO = HIGH ; diff --git a/ddr3_general_design.srcs/sources_1/ip/ddr3_cmd_fifo/ddr3_cmd_fifo.xci b/ddr3_general_design.srcs/sources_1/ip/ddr3_cmd_fifo/ddr3_cmd_fifo.xci new file mode 100644 index 0000000..fbe7517 --- /dev/null +++ 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READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 6 + BlankString + 35 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 35 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtex7 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x36 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 61 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 60 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 64 + 1 + 6 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 64 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 6 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + ddr3_info_fifo + 64 + false + 6 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 61 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 60 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 35 + 64 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 35 + 64 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtex7 + + + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2018.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_module.v b/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_module.v new file mode 100644 index 0000000..ad9cc3c --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_module.v @@ -0,0 +1,168 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/06 15:49:11 +// Design Name: +// Module Name: ddr3_ctrl_module +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_ctrl_module( + // Clock and reset signals + input sys_clk_i, + input sys_rst_i, + input ui_clk_i, + input ui_rst_i, + + // Read & Write interface signals + input [ 1:0] rw_req_i, + output rw_ack_o, + output rw_full_o, + output rd_valid_o, + output rd_empty_o, + + // User interface signals + output [ 28:0] app_addr_o, + output [ 2:0] app_cmd_o, + output app_en_o, + output [511:0] app_wdf_data_o, + output app_wdf_end_o, + output [ 63:0] app_wdf_mask_o, + output app_wdf_wren_o, + input [511:0] app_rd_data_i, + input app_rd_data_end_i, + input app_rd_data_valid_i, + input app_rdy_i, + input app_wdf_rdy_i + ); + + wire wr_req_i; + wire rd_req_i; + + wire [ 2:0] cmd_fifo_din; + wire cmd_fifo_we; + wire cmd_fifo_full; + wire [ 2:0] cmd_fifo_dout; + wire cmd_fifo_re; + wire cmd_fifo_empty; + + wire [ 28:0] addr_i_fifo_din; + wire addr_i_fifo_we; + wire addr_i_fifo_full; + wire [ 28:0] addr_i_fifo_dout; + wire addr_i_fifo_re; + wire addr_i_fifo_empty; + + wire [511:0] wdata_fifo_din; + wire wdata_fifo_we; + wire wdata_fifo_full; + wire [511:0] wdata_fifo_dout; + wire wdata_fifo_re; + wire wdata_fifo_empty; + + // Instantiate the module + ddr3_wr_ctrl ddr3_wr_ctrl_inst( + .sys_clk_i (sys_clk_i), + .sys_rst_i (sys_rst_i), + .ui_clk_i (ui_clk_i), + .ui_rst_i (ui_rst_i), + + .rw_req_i (rw_req_i), + .rw_full_o (rw_full_o), + + .cmd_fifo_full_i (cmd_fifo_full), + .addr_i_fifo_full_i (addr_i_fifo_full), + .wdata_fif_full_i (wdata_fifo_full), + .cmd_fifo_empty_i (cmd_fifo_empty), + .addr_i_fifo_empty_i (addr_i_fifo_empty), + .wdata_fifo_empty_i (wdata_fifo_empty), + + .cmd_fifo_we_o (cmd_fifo_we), + .cmd_fifo_re_o (cmd_fifo_re), + .addr_i_fifo_we_o (addr_i_fifo_we), + .addr_i_fifo_re_o (addr_i_fifo_re), + .wdata_fifo_we_o (wdata_fifo_we), + .wdata_fifo_re_o (wdata_fifo_re) + ); + + // Instantiate the module + ddr3_cmd_fifo ddr3_cmd_fifo_inst ( + .wr_clk (sys_clk_i), + .rd_clk (ui_clk_i), + .rst (sys_rst_i), + .din (cmd_fifo_din), + .wr_en (cmd_fifo_we), + .full (cmd_fifo_full), + .dout (cmd_fifo_dout), + .rd_en (cmd_fifo_re), + .empty (cmd_fifo_empty) + ); + + // Instantiate the module + ddr3_info_fifo ddr3_info_i_fifo_inst ( + .wr_clk (sys_clk_i), + .rd_clk (ui_clk_i), + .rst (sys_rst_i), + .din (addr_i_fifo_din), + .wr_en (addr_i_fifo_we), + .full (addr_i_fifo_full), + .dout (addr_i_fifo_dout), + .rd_en (addr_i_fifo_re), + .empty (addr_i_fifo_empty) + ); + + // Instantiate the module + ddr3_data_fifo ddr3_wdata_fifo_inst ( + .wr_clk (sys_clk_i), + .rd_clk (ui_clk_i), + .rst (sys_rst_i), + .din (wdata_fifo_din), + .wr_en (wdata_fifo_we), + .full (wdata_fifo_full), + .dout (wdata_fifo_dout), + .rd_en (wdata_fifo_re), + .empty (wdata_fifo_empty) + ); + + // Instantiate the module + ddr3_rd_ctrl ddr3_rd_ctrl_inst(); + + // Instantiate the module + ddr3_info_fifo ddr3_info_o_fifo_inst ( + .wr_clk (ui_clk_i), + .rd_clk (sys_clk_i), + .rst (ui_rst_i), + .din (), + .wr_en (), + .full (), + .dout (), + .rd_en (), + .empty () + ); + + // Instantiate the module + ddr3_data_fifo ddr3_rdata_fifo_inst ( + .wr_clk (ui_clk_i), + .rd_clk (sys_clk_i), + .rst (ui_rst_i), + .din (), + .wr_en (), + .full (), + .dout (), + .rd_en (), + .empty () + ); +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_top.v b/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_top.v new file mode 100644 index 0000000..d0e8bcc --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_top.v @@ -0,0 +1,235 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/06 13:54:40 +// Design Name: +// Module Name: ddr3_ctrl_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_ctrl_top( + // Clock and reset signals + input sys_clk_i, // 200MHz + input sys_rst_i, // Active high + + // System signals + output init_calib_complete_0_o, // Once the DDR initialization is complete, the signal will be set to 1 + output init_calib_complete_1_o, // same as above + + // User interface signals + input [ 1:0] ddr3_0_rw_req_i, // 01: Write, 10: Read, 00 or 11: Idle + input [ 34:0] ddr3_0_rw_info_i, // Info in (1 Ctrl Signal + 5 Scr ID + 29 Address) + input [ 63:0] ddr3_0_wr_mask_i, // Mask in + input [511:0] ddr3_0_wr_data_i, // Data in + output ddr3_0_rw_ack_o, // Read/Write acknowledge + output ddr3_0_rw_full_o, // Write FIFO full when up to 32 + + output [ 28:0] ddr3_0_rd_info_o, // Info out + output [511:0] ddr3_0_rd_data_o, // Data out + output ddr3_0_rd_valid_o, // Read data & addr & id valid + output ddr3_0_rd_empty_o, // Read FIFO empty + + input [ 1:0] ddr3_1_rw_req_i, // 01: Write, 10: Read, 00 or 11: Idle + input [ 34:0] ddr3_1_rw_info_i, // Info in + input [ 63:0] ddr3_1_wr_mask_i, // Mask in + input [511:0] ddr3_1_wr_data_i, // Data in + output ddr3_1_rw_ack_o, // Read/Write acknowledge + output ddr3_1_rw_full_o, // Write FIFO full when up to 32 + + output [ 98:0] ddr3_1_rd_info_o, // Info out + output [511:0] ddr3_1_rd_data_o, // Data out + output ddr3_1_rd_valid_o, // Read data & info valid + output ddr3_1_rd_empty_o, // Read FIFO empty + + // DDR3 interface signals + inout [ 63:0] ddr3_0_dq_io, + inout [ 7:0] ddr3_0_dqs_n_io, + inout [ 7:0] ddr3_0_dqs_p_io, + output [ 14:0] ddr3_0_addr_o, + output [ 2:0] ddr3_0_ba_o, + output ddr3_0_ras_n_o, + output ddr3_0_cas_n_o, + output ddr3_0_we_n_o, + output ddr3_0_reset_n_o, + output [ 0:0] ddr3_0_ck_p_o, + output [ 0:0] ddr3_0_ck_n_o, + output [ 0:0] ddr3_0_cke_o, + output [ 0:0] ddr3_0_cs_n_o, + output [ 7:0] ddr3_0_dm_o, + output [ 0:0] ddr3_0_odt_o, + + + inout [ 63:0] ddr3_1_dq_io, + inout [ 7:0] ddr3_1_dqs_n_io, + inout [ 7:0] ddr3_1_dqs_p_io, + output [ 14:0] ddr3_1_addr_o, + output [ 2:0] ddr3_1_ba_o, + output ddr3_1_ras_n_o, + output ddr3_1_cas_n_o, + output ddr3_1_we_n_o, + output ddr3_1_reset_n_o, + output [ 0:0] ddr3_1_ck_p_o, + output [ 0:0] ddr3_1_ck_n_o, + output [ 0:0] ddr3_1_cke_o, + output [ 0:0] ddr3_1_cs_n_o, + output [ 7:0] ddr3_1_dm_o, + output [ 0:0] ddr3_1_odt_o + ); + + // Internal DDR3 user interface signals + wire ui_0_clk; + wire ui_0_clk_sync_rst; + wire [ 28:0] app_0_addr; + wire [ 2:0] app_0_cmd; + wire app_0_en; + wire [511:0] app_0_wdf_data; + wire app_0_wdf_end; + wire [ 63:0] app_0_wdf_mask; + wire app_0_wdf_wren; + wire [511:0] app_0_rd_data; + wire app_0_rd_data_end; + wire app_0_rd_data_valid; + wire app_0_rdy; + wire app_0_wdf_rdy; + + wire app_0_sr_req; + wire app_0_ref_req; + wire app_0_zq_req; + wire app_0_sr_active; + wire app_0_ref_ack; + wire app_0_zq_ack; + + wire ui_1_clk; + wire ui_1_clk_sync_rst; + wire [ 28:0] app_1_addr; + wire [ 2:0] app_1_cmd; + wire app_1_en; + wire [511:0] app_1_wdf_data; + wire app_1_wdf_end; + wire [ 63:0] app_1_wdf_mask; + wire app_1_wdf_wren; + wire [511:0] app_1_rd_data; + wire app_1_rd_data_end; + wire app_1_rd_data_valid; + wire app_1_rdy; + wire app_1_wdf_rdy; + + wire app_1_sr_req; + wire app_1_ref_req; + wire app_1_zq_req; + wire app_1_sr_active; + wire app_1_ref_ack; + wire app_1_zq_ack; + + assign app_0_sr_req = 1'b0; + assign app_0_ref_req = 1'b0; + assign app_0_zq_req = 1'b0; + + assign app_1_sr_req = 1'b0; + assign app_1_ref_req = 1'b0; + assign app_1_zq_req = 1'b0; + + // Instantiate the DDR3 controller + ddr3_ctrl_0 ddr3_ctrl_0_inst ( + .sys_clk_i (sys_clk_i ), + .sys_rst (sys_rst_i ), + + .ddr3_addr (ddr3_0_dq_io ), + .ddr3_ba (ddr3_0_dqs_n_io ), + .ddr3_cas_n (ddr3_0_dqs_p_io ), + .ddr3_ck_n (ddr3_0_addr_o ), + .ddr3_ck_p (ddr3_0_ba_o ), + .ddr3_cke (ddr3_0_ras_n_o ), + .ddr3_ras_n (ddr3_0_cas_n_o ), + .ddr3_reset_n (ddr3_0_we_n_o ), + .ddr3_we_n (ddr3_0_reset_n_o ), + .ddr3_dq (ddr3_0_ck_p_o ), + .ddr3_dqs_n (ddr3_0_ck_n_o ), + .ddr3_dqs_p (ddr3_0_cke_o ), + .ddr3_cs_n (ddr3_0_cs_n_o ), + .ddr3_dm (ddr3_0_dm_o ), + .ddr3_odt (ddr3_0_odt_o ), + + .init_calib_complete (init_calib_complete_0_o), + .ui_clk (ui_0_clk ), + .ui_clk_sync_rst (ui_0_clk_sync_rst ), + + .app_addr (app_0_addr ), + .app_cmd (app_0_cmd ), + .app_en (app_0_en ), + .app_wdf_data (app_0_wdf_data ), + .app_wdf_end (app_0_wdf_end ), + .app_wdf_mask (app_0_wdf_mask ), + .app_wdf_wren (app_0_wdf_wren ), + .app_rd_data (app_0_rd_data ), + .app_rd_data_end (app_0_rd_data_end ), + .app_rd_data_valid (app_0_rd_data_valid ), + .app_rdy (app_0_rdy ), + .app_wdf_rdy (app_0_wdf_rdy ), + .app_sr_req (app_0_sr_req ), + .app_ref_req (app_0_ref_req ), + .app_zq_req (app_0_zq_req ), + .app_sr_active (app_0_sr_active ), + .app_ref_ack (app_0_ref_ack ), + .app_zq_ack (app_0_zq_ack ) + ); + + // Instantiate the DDR3 controller + ddr3_ctrl_1 ddr3_ctrl_1_inst ( + .sys_clk_i (sys_clk_i ), + .sys_rst (sys_rst_i ), + + .ddr3_addr (ddr3_1_dq_io ), + .ddr3_ba (ddr3_1_dqs_n_io ), + .ddr3_cas_n (ddr3_1_dqs_p_io ), + .ddr3_ck_n (ddr3_1_addr_o ), + .ddr3_ck_p (ddr3_1_ba_o ), + .ddr3_cke (ddr3_1_ras_n_o ), + .ddr3_ras_n (ddr3_1_cas_n_o ), + .ddr3_reset_n (ddr3_1_we_n_o ), + .ddr3_we_n (ddr3_1_reset_n_o ), + .ddr3_dq (ddr3_1_ck_p_o ), + .ddr3_dqs_n (ddr3_1_ck_n_o ), + .ddr3_dqs_p (ddr3_1_cke_o ), + .ddr3_cs_n (ddr3_1_cs_n_o ), + .ddr3_dm (ddr3_1_dm_o ), + .ddr3_odt (ddr3_1_odt_o ), + + .init_calib_complete (init_calib_complete_1_o), + .ui_clk (ui_1_clk ), + .ui_clk_sync_rst (ui_1_clk_sync_rst ), + + .app_addr (app_1_addr ), + .app_cmd (app_1_cmd ), + .app_en (app_1_en ), + .app_wdf_data (app_1_wdf_data ), + .app_wdf_end (app_1_wdf_end ), + .app_wdf_mask (app_1_wdf_mask ), + .app_wdf_wren (app_1_wdf_wren ), + .app_rd_data (app_1_rd_data ), + .app_rd_data_end (app_1_rd_data_end ), + .app_rd_data_valid (app_1_rd_data_valid ), + .app_rdy (app_1_rdy ), + .app_wdf_rdy (app_1_wdf_rdy ), + .app_sr_req (app_1_sr_req ), + .app_ref_req (app_1_ref_req ), + .app_zq_req (app_1_zq_req ), + .app_sr_active (app_1_sr_active ), + .app_ref_ack (app_1_ref_ack ), + .app_zq_ack (app_1_zq_ack ) + ); + +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_ctrl.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rd_ctrl.v new file mode 100644 index 0000000..78b5aaf --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_rd_ctrl.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/06 16:25:28 +// Design Name: +// Module Name: ddr3_rd_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_rd_ctrl( + + ); +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_rd_fsm.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_rd_fsm.v new file mode 100644 index 0000000..00ea43f --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_rd_fsm.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/06 16:58:22 +// Design Name: +// Module Name: ddr3_rd_fifo_rd_fsm +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_rd_fifo_rd_fsm( + + ); +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_wr_fsm.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_wr_fsm.v new file mode 100644 index 0000000..17b8e57 --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_wr_fsm.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/06 16:58:22 +// Design Name: +// Module Name: ddr3_rd_fifo_wr_fsm +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_rd_fifo_wr_fsm( + + ); +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_ctrl.v b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_ctrl.v new file mode 100644 index 0000000..eaa4b39 --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_ctrl.v @@ -0,0 +1,81 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/06 16:25:28 +// Design Name: +// Module Name: ddr3_wr_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_wr_ctrl( + input sys_clk_i, + input sys_rst_i, + input ui_clk_i, + input ui_rst_i, + + input [1:0] rw_req_i, + output rw_full_o, + + input cmd_fifo_full_i, + input addr_i_fifo_full_i, + input wdata_fifo_full_i, + input cmd_fifo_empty_i, + input addr_i_fifo_empty_i, + input wdata_fifo_empty_i, + + output cmd_fifo_we_o, + output cmd_fifo_re_o, + output addr_i_fifo_we_o, + output addr_i_fifo_re_o, + output wdata_fifo_we_o, + output wdata_fifo_re_o +); + + // Instantiate the module + ddr3_wr_fifo_wr_fsm ddr3_wr_fifo_wr_fsm_inst ( + .sys_clk_i (sys_clk_i), + .sys_rst_i (sys_rst_i), + .ui_clk_i (ui_clk_i), + .ui_rst_i (ui_rst_i), + + .rw_req_i (rw_req_i), + .rw_full_o (rw_full_o), + + .cmd_fifo_full_i (cmd_fifo_full_i), + .addr_i_fifo_full_i (addr_i_fifo_full_i), + .wdata_fif_full_i (wdata_fifo_full_i), + + .cmd_fifo_we_o (cmd_fifo_we_o), + .addr_i_fifo_we_o (addr_i_fifo_we_o), + .wdata_fifo_we_o (wdata_fifo_we_o) + ); + + // Instantiate the module + ddr3_wr_fifo_rd_fsm ddr3_wr_fifo_rd_fsm_inst ( + .sys_clk_i (sys_clk_i), + .sys_rst_i (sys_rst_i), + .ui_clk_i (ui_clk_i), + .ui_rst_i (ui_rst_i), + + .cmd_fifo_empty (cmd_fifo_empty_i), + .addr_i_fifo_empty (addr_i_fifo_empty_i), + .wdata_fifo_empty (wdata_fifo_empty_i), + + .cmd_fifo_re_o (cmd_fifo_re_o), + .addr_i_fifo_re_o (addr_i_fifo_re_o), + .wdata_fifo_re_o (wdata_fifo_re_o) + ); +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_rd_fsm.v b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_rd_fsm.v new file mode 100644 index 0000000..c22531d --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_rd_fsm.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/06 16:58:22 +// Design Name: +// Module Name: ddr3_wr_fifo_rd_fsm +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_wr_fifo_rd_fsm( + + ); +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_wr_fsm.v b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_wr_fsm.v new file mode 100644 index 0000000..6b900de --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_wr_fsm.v @@ -0,0 +1,92 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/06 16:58:22 +// Design Name: +// Module Name: ddr3_wr_fifo_wr_fsm +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_wr_fifo_wr_fsm( + input sys_clk_i, + input sys_rst_i, + input ui_clk_i, + input ui_rst_i, + + input [1:0] rw_req_i, + output rw_full_o, + + input cmd_fifo_full_i, + input addr_i_fifo_full_i, + input wdata_fifo_full_i, + + output [1:0] cmd_fifo_din_sel_o, + + output cmd_fifo_we_o, + output addr_i_fifo_we_o, + output wdata_fifo_we_o + ); + + localparam [1:0] + S_IDLE = 2'b00, + S_FIFO_WRITE = 2'b01, + S_FIFO_WAIT = 2'b10; + + + reg [1:0] c_state; + reg [1:0] n_state; + + always @(posedge sys_clk_i or negedge sys_rst_i) begin + if (sys_rst_i) begin + c_state <= S_IDLE; + end + else begin + c_state <= n_state; + end + end + + always @(*) begin + case (c_state) + S_IDLE: begin + if(rw_req_i == 2'b10 || rw_req_i == 2'b01) begin + n_state = S_FIFO_WRITE; + end + else begin + n_state = S_IDLE; + end + end + S_FIFO_WRITE: begin + if (cmd_fifo_full_i || addr_i_fifo_full_i || wdata_fifo_full_i) begin + n_state = S_FIFO_WAIT; + end + else begin + n_state = S_FIFO_WRITE; + end + end + S_FIFO_WAIT: begin + if (!cmd_fifo_full_i && !addr_i_fifo_full_i && !wdata_fifo_full_i) begin + n_state = S_FIFO_WRITE; + end + else begin + n_state = S_FIFO_WAIT; + end + end + default: begin + n_state = S_IDLE; + end + endcase; + end +endmodule diff --git a/ddr3_general_design.xpr b/ddr3_general_design.xpr new file mode 100644 index 0000000..5c4e16a --- /dev/null +++ b/ddr3_general_design.xpr @@ -0,0 +1,403 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + + diff --git a/others/wavedrom.com.txt b/others/wavedrom.com.txt new file mode 100644 index 0000000..4e5f77a --- /dev/null +++ b/others/wavedrom.com.txt @@ -0,0 +1,31 @@ +{ + signal: [ + {}, + {name: 'clk', wave: 'p........|........'}, + {name: 'rw_req_i', wave: 'x=43=....|.......x', data: ['idle', 'read', 'write', 'idle', ]}, + {name: 'rw_addr_i', wave: 'x=43=....|.......x', data: ['29\'h0000', '29\'h0008', '29\'h000a', '29\'h0000', ]}, + {name: 'wr_data_i', wave: 'x=.3=....|.......x', data: [ '512\'h0000', '512\'hxxxx', '512\'h0000' ]}, + {name: 'rd_src_id_i', wave: 'x=43=....|.......x', data: ['5\'h00', '5\'h01', '5\'h02', '5\'h00', ]}, + {name: 'rd_len_i', wave: 'x=4==....|.......x', data: ['5h\'h00', '5h\'h04', '5\'h01', '5h\'h00', ]}, + {name: 'rw_ack_o', wave: '0..10..10|........'}, + {name: 'rd_addr_o', wave: 'x=.......|..4444=x', data: [ '29\'h0000', '29\'h0008', '29\'h0009', '29\'h000a', '29\'h000b', '29\'h0000' ]}, + {name: 'rd_src_id_o', wave: 'x=.......|..4444=x', data: [ '5\'h00', '5\'h01', '5\'h01', '5\'h01', '5\'h01', '5\'h00' ]}, + {name: 'rd_data_o', wave: 'x=.......|..4444=x', data: [ '512h\'h0000', '512h\'hxxxx', '512\'hxxxx', '512h\'hxxxx', '512h\'hxxxx', '512h\'h0000' ]}, + {name: 'rd_valid_o', wave: '0........|..1...0.', }, + {}, + {}, + {name: 'clk', wave: 'p........|........'}, + {name: 'rw_req_i', wave: 'x=44443=.|.......x', data: ['idle', 'read', 'read', 'read', 'read', 'write', 'idle', ]}, + {name: 'rw_addr_i', wave: 'x=44443=.|.......x', data: ['29\'h0000', '29\'h0008', '29\'h0009', '29\'h000a', '29\'h000b', '29\'h000a', '29\'h0000', ]}, + {name: 'wr_data_i', wave: 'x=....3=.|.......x', data: [ '512\'h0000', '512\'hxxxx', '512\'h0000' ]}, + {name: 'rd_src_id_i', wave: 'x=44443=.|.......x', data: ['5\'h00', '5\'h01', '5\'h01', '5\'h01', '5\'h01', '5\'h02', '5\'h00', ]}, + {name: 'rw_ack_o', wave: '0..1....0|........'}, + {name: 'rd_addr_o', wave: 'x=.......|..4444=x', data: [ '29\'h0_0000', '29\'h0008', '29\'h0009', '29\'h000a', '29\'h000b', '29\'h0000' ]}, + {name: 'rd_src_id_o', wave: 'x=.......|..4444=x', data: [ '5\'h00', '5\'h01', '5\'h01', '5\'h01', '5\'h01', '5\'h00' ]}, + {name: 'rd_data_o', wave: 'x=.......|..4444=x', data: [ '512h\'h0000', '512h\'hxxxx', '512\'hxxxx', '512h\'hxxxx', '512h\'hxxxx', '512h\'h0000' ]}, + {name: 'rd_valid_o', wave: '0........|..1...0.', }, + {}, +], + config: { hscale: 3 } +} +