FPGALab/ddr3_general_design
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UnbalancedCat 30fa4e98fe first commit
2025-01-06 22:30:12 +08:00
ddr3_general_design.srcs
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others
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ddr3_general_design.xpr
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Description
基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板
59 MiB
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Verilog 100%