Initial

cpu_rv32i.srcs/sources_1/new/regfile.v

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+module regfile(
+    input         clk,
+    input         reset,
+    // READ PORT 1
+    input  [ 4:0] raddr1,
+    output [31:0] rdata1,
+    // READ PORT 2
+    input  [ 4:0] raddr2,
+    output [31:0] rdata2,
+    // READ PORT 3
+    input  [ 4:0] raddr3,
+    output [31:0] rdata3,
+    // WRITE PORT
+    input         we,       //write enable, HIGH valid
+    input  [ 4:0] waddr,
+    input  [31:0] wdata
+);
+reg [31:0] rf[31:0];
+integer i = 0;
+//WRITE
+always @(posedge clk) begin
+    if (reset) begin
+        for(i = 0; i < 32; i = i + 1) begin
+            rf[i] <= 32'b0;
+        end 
+    end
+    else if (we) begin
+        rf[waddr]<= wdata;
+    end
+end
+
+//READ OUT 1
+assign rdata1 = (we & (raddr1 == waddr)) ? wdata :
+                (      raddr1 == 5'b0  ) ? 32'b0 : 
+                                           rf[raddr1];
+
+//READ OUT 2
+assign rdata2 = (we & (raddr2 == waddr)) ? wdata :
+                (      raddr2 == 5'b0  ) ? 32'b0 : 
+                                           rf[raddr2];
+//READ OUT 3
+assign rdata3 = (we & (raddr3 == waddr)) ? wdata :
+                (      raddr3 == 5'b0  ) ? 32'b0 : 
+                                           rf[raddr3];
+endmodule