45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
module regfile(
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input clk,
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input reset,
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// READ PORT 1
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input [ 4:0] raddr1,
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output [31:0] rdata1,
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// READ PORT 2
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input [ 4:0] raddr2,
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output [31:0] rdata2,
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// READ PORT 3
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input [ 4:0] raddr3,
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output [31:0] rdata3,
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// WRITE PORT
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input we, //write enable, HIGH valid
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input [ 4:0] waddr,
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input [31:0] wdata
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);
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reg [31:0] rf[31:0];
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integer i = 0;
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//WRITE
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always @(posedge clk) begin
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if (reset) begin
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for(i = 0; i < 32; i = i + 1) begin
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rf[i] <= 32'b0;
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end
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end
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else if (we) begin
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rf[waddr]<= wdata;
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end
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end
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//READ OUT 1
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assign rdata1 = (we & (raddr1 == waddr)) ? wdata :
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( raddr1 == 5'b0 ) ? 32'b0 :
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rf[raddr1];
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//READ OUT 2
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assign rdata2 = (we & (raddr2 == waddr)) ? wdata :
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( raddr2 == 5'b0 ) ? 32'b0 :
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rf[raddr2];
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//READ OUT 3
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assign rdata3 = (we & (raddr3 == waddr)) ? wdata :
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( raddr3 == 5'b0 ) ? 32'b0 :
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rf[raddr3];
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endmodule |