This website requires JavaScript.
Explore
Help
Sign In
UnbalancedCat
/
risc-v_cpu_core
Watch
1
Star
0
Fork
0
You've already forked risc-v_cpu_core
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
1
Commit
1
Branch
0
Tags
9135170576cc2bdd12c10e06288224c42e923e62
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
UnbalancedCat
9135170576
init repo: update to RV32IMA (M mode)
2025-05-23 00:15:19 +08:00
rv_cpu.srcs/sources_1
/new
init repo: update to RV32IMA (M mode)
2025-05-23 00:15:19 +08:00
.gitignore
init repo: update to RV32IMA (M mode)
2025-05-23 00:15:19 +08:00
rv_cpu.xpr
init repo: update to RV32IMA (M mode)
2025-05-23 00:15:19 +08:00
Description
RV32IMA
72
KiB
Languages
Verilog
100%