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UnbalancedCat
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risc-v_cpu_core
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UnbalancedCat
a0bf7f174f
fix bug & update xret
2025-05-23 20:10:03 +08:00
rv_cpu.srcs/sources_1
/new
fix bug & update xret
2025-05-23 20:10:03 +08:00
.gitignore
init repo: update to RV32IMA (M mode)
2025-05-23 00:15:19 +08:00
rv_cpu.xpr
init repo: update to RV32IMA (M mode)
2025-05-23 00:15:19 +08:00
Description
RV32IMA
72
KiB
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Verilog
100%