56 lines
1.3 KiB
Verilog
56 lines
1.3 KiB
Verilog
module mul(
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input clk,
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input reset,
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output stallreq,
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input in_valid,
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output out_valid,
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input [31:0] a,
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input [31:0] b,
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output reg [31:0] result_h,
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output reg [31:0] result_l
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);
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reg [ 5:0] cnt;
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wire [31:0] add_result;
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wire carry;
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wire [63:0] mul_result;
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reg [63:0] mul_result_r;
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always @ (posedge clk) begin
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if (reset) begin
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cnt <= 0;
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end
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else if (cnt != 0) begin
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cnt <= cnt - 1;
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end
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else if (in_valid) begin
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cnt <= 2;//32;
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end
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end
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assign mul_result = a * b;
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always @ (posedge clk) begin
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if (reset) begin
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result_h <= 0;
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result_l <= 0;
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mul_result_r <= 0;
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end
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else if (cnt != 0) begin
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//{result_h, result_l} <= {carry, add_result, result_l[31:1]};
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result_h <= mul_result_r[63:32];
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result_l <= mul_result_r[31: 0];
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mul_result_r <= mul_result;
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end
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else if (in_valid) begin
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result_h <= 0;
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result_l <= 0;//b;
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mul_result_r <= 0;
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end
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end
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assign out_valid = (cnt==0);
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assign stallreq = in_valid | (~(cnt==0));
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endmodule |