63 lines
2.1 KiB
Verilog
63 lines
2.1 KiB
Verilog
module icache
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#(
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parameter HIT_WD = 2,
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parameter LRU_WD = 1,
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parameter CACHELINE_WD = 512
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)
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(
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input clk,
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input reset,
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input inst_sram_en,
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input [ 3:0] inst_sram_we,
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input [31:0] inst_sram_addr,
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input [31:0] inst_sram_wdata,
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input icache_refresh,
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input [CACHELINE_WD -1:0] icache_cacheline_new,
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output stallreq_icache,
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output [31:0] inst_sram_rdata,
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output icache_miss,
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output [31:0] icache_raddr,
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output [31:0] icache_waddr,
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output [CACHELINE_WD -1:0] icache_cacheline_old
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);
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wire [HIT_WD -1:0] icache_hit;
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wire [LRU_WD -1:0] icache_lru;
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cache_tag_v5 u_icache_tag(
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.clk (clk ),
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.reset (reset ),
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.flush (1'b0 ),
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.stallreq (stallreq_icache ),
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.cached (1'b1 ),
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.sram_en (inst_sram_en ),
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.sram_we (inst_sram_we ),
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.sram_addr (inst_sram_addr ),
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.refresh (icache_refresh ),
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.miss (icache_miss ),
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.axi_raddr (icache_raddr ),
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.write_back (/*icache_write_back*/ ), // no use
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.axi_waddr (icache_waddr ),
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.hit (icache_hit ),
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.lru (icache_lru )
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);
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cache_data_v5 u_icache_data(
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.clk (clk ),
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.reset (reset ),
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.write_back (1'b0 ),
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.hit (icache_hit ),
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.lru (icache_lru ),
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.cached (1'b1 ),
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.sram_en (inst_sram_en ),
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.sram_we (inst_sram_we ),
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.sram_addr (inst_sram_addr ),
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.sram_wdata (inst_sram_wdata ),
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.sram_rdata (inst_sram_rdata ),
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.refresh (icache_refresh ),
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.cacheline_new (icache_cacheline_new ),
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.cacheline_old (icache_cacheline_old )
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);
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endmodule |