65 lines
2.2 KiB
Verilog
65 lines
2.2 KiB
Verilog
module dcache
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#(
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parameter HIT_WD = 2,
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parameter LRU_WD = 1,
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parameter CACHELINE_WD = 512
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)
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(
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input clk,
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input reset,
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input data_sram_en,
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input [ 3:0] data_sram_we,
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input [31:0] data_sram_addr,
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input [31:0] data_sram_wdata,
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input dcache_refresh,
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input dcache_uncached,
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input [CACHELINE_WD -1:0] dcache_cacheline_new,
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output stallreq_dcache,
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output [31:0] data_sram_rdata,
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output dcache_miss,
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output [31:0] dcache_raddr,
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output [31:0] dcache_waddr,
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output dcache_write_back,
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output [CACHELINE_WD -1:0] dcache_cacheline_old
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);
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wire [HIT_WD -1:0] dcache_hit;
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wire [LRU_WD -1:0] dcache_lru;
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cache_tag_v5 u_dcache_tag(
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.clk (clk ),
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.reset (reset ),
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.flush (1'b0 ),
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.stallreq (stallreq_dcache ),
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.cached (~dcache_uncached ),
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.sram_en (data_sram_en ),
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.sram_we (data_sram_we ),
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.sram_addr (data_sram_addr ),
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.refresh (dcache_refresh ),
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.miss (dcache_miss ),
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.axi_raddr (dcache_raddr ),
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.write_back (dcache_write_back ),
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.axi_waddr (dcache_waddr ),
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.hit (dcache_hit ),
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.lru (dcache_lru )
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);
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cache_data_v5 u_dcache_data(
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.clk (clk ),
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.reset (reset ),
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.write_back (dcache_write_back ),
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.hit (dcache_hit ),
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.lru (dcache_lru ),
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.cached (~dcache_uncached ),
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.sram_en (data_sram_en ),
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.sram_we (data_sram_we ),
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.sram_addr (data_sram_addr ),
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.sram_wdata (data_sram_wdata ),
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.sram_rdata (data_sram_rdata ),
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.refresh (dcache_refresh ),
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.cacheline_new (dcache_cacheline_new ),
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.cacheline_old (dcache_cacheline_old )
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);
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endmodule |