63 lines
1.5 KiB
Verilog
63 lines
1.5 KiB
Verilog
module dt
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#(
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parameter ES_TO_DT_BUS_WD = 340,
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parameter DT_TO_MS_BUS_WD = 271,
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parameter MS_TO_ES_BUS_WD = 38
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)
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(
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input clk,
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input reset,
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input flush,
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input [ 5:0] stall,
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input [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus,
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output [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus,
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output [MS_TO_ES_BUS_WD -1:0] dts_to_es_bus,
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output data_sram_en,
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output [ 3:0] data_sram_we,
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output [31:0] data_sram_addr,
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output [31:0] data_sram_wdata
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);
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reg [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus_r;
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wire reg_we;
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wire [ 4:0] dest;
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wire [31:0] es_result;
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assign dts_to_ms1_bus = es_to_dts_bus_r[DT_TO_MS_BUS_WD -1:0];
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assign {reg_we ,
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dest ,
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es_result
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} = es_to_dts_bus_r[133:96];
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assign {data_sram_en ,
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data_sram_we ,
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data_sram_addr ,
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data_sram_wdata
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} = es_to_dts_bus_r[339:271];
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assign dts_to_es_bus = {reg_we,
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dest,
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es_result
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};
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always @(posedge clk) begin
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if (reset) begin
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es_to_dts_bus_r <= 0;
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end
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else if (flush) begin
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es_to_dts_bus_r <= 0;
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end
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else if(stall[3] & (!stall[4])) begin
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es_to_dts_bus_r <= 0;
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end
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else if(!stall[3]) begin
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es_to_dts_bus_r <= es_to_dts_bus;
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end
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end
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endmodule |