56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
module bru(
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input [31:0] pc,
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input [31:0] rj_value,
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input [31:0] rkd_value,
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input [31:0] imm,
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input [ 8:0] branch_op,
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output br_taken,
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output [31:0] br_target
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);
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wire inst_jirl;
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wire inst_b;
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wire inst_bl;
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wire inst_beq;
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wire inst_bne;
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wire inst_blt;
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wire inst_bge;
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wire inst_bltu;
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wire inst_bgeu;
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wire rj_eq_rd;
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wire rj_lt_rd;
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wire rj_ltu_rd;
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assign {inst_beq,
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inst_bne,
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inst_blt,
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inst_bge,
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inst_bltu,
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inst_bgeu,
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inst_jirl,
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inst_bl,
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inst_b
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} = branch_op;
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assign rj_eq_rd = (rj_value == rkd_value);
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assign rj_ltu_rd = (rj_value < rkd_value);
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assign rj_lt_rd = (rj_value[31] && ~rkd_value[31]) ? 1'b1 :
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(~rj_value[31] && rkd_value[31]) ? 1'b0 :
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rj_ltu_rd;
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assign br_taken = ( inst_beq && rj_eq_rd
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|| inst_bne && !rj_eq_rd
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|| inst_blt && rj_lt_rd
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|| inst_bge && !rj_lt_rd
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|| inst_bltu && rj_ltu_rd
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|| inst_bgeu && !rj_ltu_rd
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|| inst_jirl
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|| inst_bl
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|| inst_b
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);
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assign br_target = ({32{inst_beq|inst_bne|inst_bl|inst_b|inst_blt|inst_bge|inst_bltu|inst_bgeu}} & (pc + imm))
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| ({32{inst_jirl}} & (rj_value + imm));
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endmodule |