61 lines
1.5 KiB
Verilog
61 lines
1.5 KiB
Verilog
`define StallBus 6
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module pip_ctrl(
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input reset,
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input except_en,
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//input stallreq_fs_for_cache,
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//input stallreq_es_for_cache,
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input stallreq_ds,
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input stallreq_es,
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input stallreq_axi,
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input stallreq_cache,
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output reg flush,
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output reg [`StallBus-1:0] stall
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);
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//stall[0] --?
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//stall[1] --?
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//stall[2] --id
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//stall[3]
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//stall[4]
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//stall[5]
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always @ (*) begin
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if (reset) begin
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flush = 0;
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stall = `StallBus'b000000;
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end
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else if (stallreq_axi) begin
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flush = 0;
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stall = `StallBus'b111111;
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end
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else if (except_en) begin
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flush = 1;
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stall = `StallBus'b0;
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end
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else if (stallreq_es) begin
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flush = 0;
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stall = `StallBus'b111111;
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end
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//id段å<C2B5>‘生暂å<E2809A>œï¼Œæ¤æ—¶idå<64>Šä¹‹å‰<C3A5>æš‚å<E2809A>?
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else if (stallreq_ds) begin
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flush = 0;
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stall = `StallBus'b000111;
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end
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// else if(stallreq_fs_for_cache) begin
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// flush = 0;
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// stall = `StallBus'b000011;
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// end
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// else if(stallreq_es_for_cache) begin
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// flush = 0;
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// stall = `StallBus'b011111;
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// end
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// else if(stallreq_cache) begin
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// flush = 0;
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// stall = `StallBus'b111111;
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// end
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else begin
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flush = 0;
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stall = `StallBus'b000000;
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end
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end
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endmodule
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