55 lines
812 B
Verilog
55 lines
812 B
Verilog
`default_nettype wire
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module decoder_2_4(
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input [ 1:0] in,
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output [ 3:0] out
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);
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genvar i;
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generate for (i=0; i<4; i=i+1) begin : gen_for_dec_2_4
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assign out[i] = (in == i);
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end endgenerate
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endmodule
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module decoder_4_16(
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input [ 3:0] in,
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output [15:0] out
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);
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genvar i;
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generate for (i=0; i<16; i=i+1) begin : gen_for_dec_4_16
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assign out[i] = (in == i);
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end endgenerate
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endmodule
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module decoder_5_32(
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input [ 4:0] in,
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output [31:0] out
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);
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genvar i;
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generate for (i=0; i<32; i=i+1) begin : gen_for_dec_5_32
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assign out[i] = (in == i);
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end endgenerate
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endmodule
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module decoder_6_64(
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input [ 5:0] in,
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output [63:0] out
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);
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genvar i;
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generate for (i=0; i<64; i=i+1) begin : gen_for_dec_6_64 //bug7
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assign out[i] = (in == i);
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end endgenerate
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endmodule
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