UnbalancedCat 4c9c2ddd78 [Modified] Debug & board test with cache & pass n58 with 40 MHz

2023-07-22 14:56:53 +08:00

..

axi_wrap

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

CONFREG

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

mycpu

[Modified] Debug & board test with cache & pass n58 with 40 MHz

2023-07-22 14:56:53 +08:00

ram_wrap

[Modified] Switch soc_top&board to axi&xc7a200t

2023-07-20 21:40:21 +08:00

xilinx_ip

[Modified] Debug & board test with cache & pass n58 with 40 MHz

2023-07-22 14:56:53 +08:00

soc_lite_top.v

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00

soc_lite_top.v.axi_bak

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00

soc_lite_top.v.bram_bak

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00