21 lines
729 B
Verilog
21 lines
729 B
Verilog
module mmu (
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input [31:0] addr_i,
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output [31:0] addr_o,
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output cache_v
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);
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wire [1:0] addr_head_i, addr_head_o;
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assign addr_head_i = addr_i[31:30];
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wire kseg0_l, kseg0_h, kseg1_l, kseg1_h;
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assign kseg0_l = addr_head_i == 2'b00;
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assign kseg0_h = addr_head_i == 2'b01;
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assign kseg1_l = addr_head_i == 2'b10;
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assign kseg1_h = addr_head_i == 2'b11;
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wire other_seg;
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assign other_seg = ~kseg0_l & ~kseg0_h & ~kseg1_l & ~kseg1_h;
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assign addr_head_o = {2{kseg0_l}}&2'b00 | {2{kseg0_h}}&2'b01 | {2{kseg1_l}}&2'b10 | {2{kseg1_h}}&2'b11 | {2{other_seg}}&addr_head_i;
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assign addr_o = {addr_head_o, addr_i[29:0]};
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assign cache_v = ~(kseg0_l|kseg1_l|kseg1_h);
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endmodule |