538 lines
21 KiB
Verilog
538 lines
21 KiB
Verilog
module inst_decoder(
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input [31:0] inst,
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output src1_is_pc,
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output src2_is_imm,
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output src2_is_4,
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output src_reg_is_rd,
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output [ 4:0] rj,
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output [ 4:0] rk,
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output [ 4:0] rd,
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output [31:0] imm,
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output [ 4:0] dest,
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// alu
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output [11:0] alu_op,
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// mul div
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output [ 3:0] mul_div_op,
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output mul_div_sign,
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// branch
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output [ 8:0] branch_op,
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output [ 5:0] load_op,
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output [ 2:0] store_op,
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// csr
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input excp_adef,
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input [ 1:0] csr_plv,
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input csr_has_int,
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output csr_we,
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output [ 6:0] csr_op,
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output [13:0] csr_addr,
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output csr_wdata_sel,
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output [31:0] csr_vec_l,
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output reg_we
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);
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wire dest_is_r1;
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wire dest_is_rj;
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wire [ 5:0] op_31_26;
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wire [ 3:0] op_25_22;
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wire [ 1:0] op_21_20;
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wire [ 4:0] op_19_15;
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wire [63:0] op_31_26_d;
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wire [15:0] op_25_22_d;
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wire [ 3:0] op_21_20_d;
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wire [31:0] op_19_15_d;
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wire [31:0] rd_d;
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wire [31:0] rj_d;
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wire [31:0] rk_d;
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wire [11:0] i12;
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wire [13:0] i14;
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wire [19:0] i20;
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wire [15:0] i16;
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wire [25:0] i26;
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wire [13:0] csr_idx;
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wire inst_add_w;
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wire inst_sub_w;
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wire inst_slt;
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wire inst_sltu;
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wire inst_nor;
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wire inst_and;
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wire inst_or;
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wire inst_xor;
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wire inst_lu12i_w;
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wire inst_addi_w;
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wire inst_slti;
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wire inst_sltui;
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wire inst_pcaddi;
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wire inst_pcaddu12i;
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//wire inst_andn;
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//wire inst_orn;
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wire inst_andi;
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wire inst_ori;
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wire inst_xori;
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wire inst_mul_w;
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wire inst_mulh_w;
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wire inst_mulh_wu;
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wire inst_div_w;
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wire inst_mod_w;
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wire inst_div_wu;
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wire inst_mod_wu;
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wire inst_slli_w;
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wire inst_srli_w;
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wire inst_srai_w;
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wire inst_sll_w;
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wire inst_srl_w;
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wire inst_sra_w;
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wire inst_jirl;
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wire inst_b;
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wire inst_bl;
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wire inst_beq;
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wire inst_bne;
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wire inst_blt;
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wire inst_bge;
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wire inst_bltu;
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wire inst_bgeu;
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wire inst_ll_w;
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wire inst_sc_w;
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wire inst_ld_b;
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wire inst_ld_bu;
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wire inst_ld_h;
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wire inst_ld_hu;
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wire inst_ld_w;
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wire inst_st_b;
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wire inst_st_h;
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wire inst_st_w;
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wire inst_syscall;
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wire inst_break;
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wire inst_csrrd;
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wire inst_csrwr;
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wire inst_csrxchg;
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wire inst_ertn;
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wire inst_rdcntid_w;
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wire inst_rdcntvl_w;
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wire inst_rdcntvh_w;
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//wire inst_idle;
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//wire inst_tlbsrch;
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//wire inst_tlbrd;
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//wire inst_tlbwr;
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//wire inst_tlbfill;
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//wire inst_invtlb;
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//wire inst_cacop;
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//wire inst_preld;
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wire inst_dbar;
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wire inst_ibar;
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wire need_ui5;
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wire need_si12;
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wire need_ui12;
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wire need_si14_pc;
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wire need_si16_pc;
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wire need_si20;
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wire need_si20_pc;
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wire need_si26_pc;
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wire inst_valid;
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wire excp_ine;
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wire kernel_inst;
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wire excp_ipe;
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assign op_31_26 = inst[31:26];
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assign op_25_22 = inst[25:22];
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assign op_21_20 = inst[21:20];
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assign op_19_15 = inst[19:15];
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assign rd = inst[ 4: 0];
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assign rj = inst[ 9: 5];
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assign rk = inst[14:10];
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assign i12 = inst[21:10];
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assign i14 = inst[23:10];
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assign i20 = inst[24: 5];
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assign i16 = inst[25:10];
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assign i26 = {inst[ 9: 0], inst[25:10]};
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assign csr_idx = inst[23:10];
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decoder_6_64 u_dec0(.in(op_31_26 ), .out(op_31_26_d ));
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decoder_4_16 u_dec1(.in(op_25_22 ), .out(op_25_22_d ));
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decoder_2_4 u_dec2(.in(op_21_20 ), .out(op_21_20_d ));
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decoder_5_32 u_dec3(.in(op_19_15 ), .out(op_19_15_d ));
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decoder_5_32 u_dec4(.in(rd ), .out(rd_d ));
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decoder_5_32 u_dec5(.in(rj ), .out(rj_d ));
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decoder_5_32 u_dec6(.in(rk ), .out(rk_d ));
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assign inst_add_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h00];
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assign inst_sub_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h02];
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assign inst_slt = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h04];
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assign inst_sltu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h05];
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assign inst_nor = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h08];
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assign inst_and = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h09];
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assign inst_or = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0a];
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assign inst_xor = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0b];
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//assign inst_orn = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0c];
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//assign inst_andn = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0d];
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assign inst_sll_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0e];
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assign inst_srl_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0f];
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assign inst_sra_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h10];
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assign inst_mul_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h18];
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assign inst_mulh_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h19];
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assign inst_mulh_wu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h1a];
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assign inst_div_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h00];
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assign inst_mod_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h01];
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assign inst_div_wu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h02];
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assign inst_mod_wu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h03];
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assign inst_break = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h14];
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assign inst_syscall = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h16];
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assign inst_slli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h01];
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assign inst_srli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h09];
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assign inst_srai_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h11];
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//assign inst_idle = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h11];
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//assign inst_invtlb = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h13];
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assign inst_dbar = op_31_26_d[6'h0e] & op_25_22_d[4'h1] & op_21_20_d[2'h3] & op_19_15_d[5'h04];
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assign inst_ibar = op_31_26_d[6'h0e] & op_25_22_d[4'h1] & op_21_20_d[2'h3] & op_19_15_d[5'h05];
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assign inst_slti = op_31_26_d[6'h00] & op_25_22_d[4'h8];
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assign inst_sltui = op_31_26_d[6'h00] & op_25_22_d[4'h9];
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assign inst_addi_w = op_31_26_d[6'h00] & op_25_22_d[4'ha];
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assign inst_andi = op_31_26_d[6'h00] & op_25_22_d[4'hd];
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assign inst_ori = op_31_26_d[6'h00] & op_25_22_d[4'he];
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assign inst_xori = op_31_26_d[6'h00] & op_25_22_d[4'hf];
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assign inst_ld_b = op_31_26_d[6'h0a] & op_25_22_d[4'h0];
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assign inst_ld_h = op_31_26_d[6'h0a] & op_25_22_d[4'h1];
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assign inst_ld_w = op_31_26_d[6'h0a] & op_25_22_d[4'h2];
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assign inst_st_b = op_31_26_d[6'h0a] & op_25_22_d[4'h4];
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assign inst_st_h = op_31_26_d[6'h0a] & op_25_22_d[4'h5];
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assign inst_st_w = op_31_26_d[6'h0a] & op_25_22_d[4'h6];
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assign inst_ld_bu = op_31_26_d[6'h0a] & op_25_22_d[4'h8];
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assign inst_ld_hu = op_31_26_d[6'h0a] & op_25_22_d[4'h9];
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//assign inst_cacop = op_31_26_d[6'h01] & op_25_22_d[4'h8];
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//assign inst_preld = op_31_26_d[6'h0a] & op_25_22_d[4'hb];
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assign inst_jirl = op_31_26_d[6'h13];
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assign inst_b = op_31_26_d[6'h14];
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assign inst_bl = op_31_26_d[6'h15];
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assign inst_beq = op_31_26_d[6'h16];
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assign inst_bne = op_31_26_d[6'h17];
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assign inst_blt = op_31_26_d[6'h18];
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assign inst_bge = op_31_26_d[6'h19];
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assign inst_bltu = op_31_26_d[6'h1a];
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assign inst_bgeu = op_31_26_d[6'h1b];
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assign inst_lu12i_w = op_31_26_d[6'h05] & ~inst[25];
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assign inst_pcaddi = op_31_26_d[6'h06] & ~inst[25];
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assign inst_pcaddu12i = op_31_26_d[6'h07] & ~inst[25];
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assign inst_csrxchg = op_31_26_d[6'h01] & ~inst[25] & ~inst[24] & (~rj_d[5'h00] & ~rj_d[5'h01]); //rj != 0,1
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assign inst_ll_w = op_31_26_d[6'h08] & ~inst[25] & ~inst[24];
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assign inst_sc_w = op_31_26_d[6'h08] & ~inst[25] & inst[24];
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assign inst_csrrd = op_31_26_d[6'h01] & ~inst[25] & ~inst[24] & rj_d[5'h00];
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assign inst_csrwr = op_31_26_d[6'h01] & ~inst[25] & ~inst[24] & rj_d[5'h01];
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assign inst_rdcntid_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h00] & rk_d[5'h18] & rd_d[5'h00];
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assign inst_rdcntvl_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h00] & rk_d[5'h18] & rj_d[5'h00] & !rd_d[5'h00];
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assign inst_rdcntvh_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h00] & rk_d[5'h19] & rj_d[5'h00];
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assign inst_ertn = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0e] & rj_d[5'h00] & rd_d[5'h00];
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//assign inst_tlbsrch = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0a] & rj_d[5'h00] & rd_d[5'h00];
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//assign inst_tlbrd = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0b] & rj_d[5'h00] & rd_d[5'h00];
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//assign inst_tlbwr = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0c] & rj_d[5'h00] & rd_d[5'h00];
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//assign inst_tlbfill = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0d] & rj_d[5'h00] & rd_d[5'h00];
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assign src_reg_is_rd = inst_beq |
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inst_bne |
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inst_blt |
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inst_bltu |
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inst_bge |
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inst_bgeu |
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inst_st_b |
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inst_st_h |
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inst_st_w |
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inst_sc_w |
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inst_csrwr |
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inst_csrxchg;
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assign src1_is_pc = inst_jirl |
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inst_bl |
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inst_pcaddi |
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inst_pcaddu12i;
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assign src2_is_imm = inst_slli_w |
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inst_srli_w |
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inst_srai_w |
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inst_addi_w |
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inst_slti |
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inst_sltui |
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inst_andi |
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inst_ori |
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inst_xori |
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inst_pcaddi |
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inst_pcaddu12i |
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inst_ld_b |
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inst_ld_h |
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inst_ld_w |
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inst_ld_bu |
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inst_ld_hu |
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inst_st_b |
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inst_st_h |
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inst_st_w |
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inst_ll_w |
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inst_sc_w |
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inst_lu12i_w ;
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//inst_cacop |
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//inst_preld ;
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assign src2_is_4 = inst_jirl |
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inst_bl;
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assign dest_is_r1 = inst_bl;
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assign dest_is_rj = inst_rdcntid_w;
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assign dest = (dest_is_r1) ? 5'd1 :
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(dest_is_rj) ? rj :
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rd;
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// alu_op
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assign alu_op[ 0] = inst_add_w |
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inst_addi_w |
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//inst_ld_b |
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//inst_ld_h |
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//inst_ld_w |
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//inst_st_b |
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//inst_st_h |
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//inst_st_w |
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//inst_ld_bu |
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//inst_ld_hu |
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//inst_ll_w |
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//inst_sc_w |
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inst_jirl |
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inst_bl |
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inst_pcaddi |
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inst_pcaddu12i;
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//inst_cacop |
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//inst_preld ;
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assign alu_op[ 1] = inst_sub_w;
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assign alu_op[ 2] = inst_slt | inst_slti;
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assign alu_op[ 3] = inst_sltu | inst_sltui;
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assign alu_op[ 4] = inst_and | inst_andi;
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assign alu_op[ 5] = inst_nor;
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assign alu_op[ 6] = inst_or | inst_ori;
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assign alu_op[ 7] = inst_xor | inst_xori;
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assign alu_op[ 8] = inst_sll_w | inst_slli_w;
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assign alu_op[ 9] = inst_srl_w | inst_srli_w;
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assign alu_op[10] = inst_sra_w | inst_srai_w;
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assign alu_op[11] = inst_lu12i_w;
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//assign alu_op[12] = inst_andn;
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//assign alu_op[13] = inst_orn;
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|
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// imm
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assign need_ui5 = inst_slli_w | inst_srli_w | inst_srai_w;
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assign need_si12 = inst_addi_w |
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inst_ld_b |
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inst_ld_h |
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inst_ld_w |
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inst_st_b |
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inst_st_h |
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inst_st_w |
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inst_ld_bu |
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inst_ld_hu |
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inst_slti |
|
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inst_sltui;
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//inst_cacop |
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|
//inst_preld ;
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|
|
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assign need_ui12 = inst_andi | inst_ori | inst_xori;
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assign need_si14_pc = inst_ll_w | inst_sc_w;
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assign need_si16_pc = inst_jirl |
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inst_beq |
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inst_bne |
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inst_blt |
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inst_bge |
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inst_bltu |
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inst_bgeu;
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|
|
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assign need_si20 = inst_lu12i_w | inst_pcaddu12i;
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assign need_si20_pc = inst_pcaddi;
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assign need_si26_pc = inst_b | inst_bl;
|
|
|
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assign imm = ({32{need_ui5 }} & {27'b0, rk} ) |
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({32{need_si12 }} & {{20{i12[11]}}, i12} ) |
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({32{need_ui12 }} & {20'b0, i12} ) |
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|
({32{need_si14_pc}} & {{16{i14[13]}}, i14, 2'b0}) |
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|
({32{need_si16_pc}} & {{14{i16[15]}}, i16, 2'b0}) |
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|
({32{need_si20 }} & {i20, 12'b0} ) |
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|
({32{need_si20_pc}} & {{10{i20[19]}}, i20, 2'b0}) |
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|
({32{need_si26_pc}} & {{ 4{i26[25]}}, i26, 2'b0}) ;
|
|
|
|
// mul_div
|
|
assign mul_div_op[ 0] = inst_mul_w;
|
|
assign mul_div_op[ 1] = inst_mulh_w | inst_mulh_wu;
|
|
assign mul_div_op[ 2] = inst_div_w | inst_div_wu;
|
|
assign mul_div_op[ 3] = inst_mod_w | inst_mod_wu;
|
|
|
|
assign mul_div_sign = inst_mul_w | inst_mulh_w | inst_div_w | inst_mod_w;
|
|
|
|
// branch_op
|
|
assign branch_op = {inst_beq,
|
|
inst_bne,
|
|
inst_blt,
|
|
inst_bge,
|
|
inst_bltu,
|
|
inst_bgeu,
|
|
inst_jirl,
|
|
inst_bl,
|
|
inst_b
|
|
};
|
|
|
|
// load_op store_op
|
|
assign load_op = {inst_ld_b,
|
|
inst_ld_h,
|
|
inst_ld_w,
|
|
inst_ld_bu,
|
|
inst_ld_hu,
|
|
inst_ll_w
|
|
};
|
|
assign store_op = {inst_st_b,
|
|
inst_st_h,
|
|
inst_st_w
|
|
};
|
|
assign reg_we = ~inst_st_b &
|
|
~inst_st_h &
|
|
~inst_st_w &
|
|
~inst_beq &
|
|
~inst_bne &
|
|
~inst_blt &
|
|
~inst_bge &
|
|
~inst_bltu &
|
|
~inst_bgeu &
|
|
~inst_b &
|
|
~inst_syscall &
|
|
//~inst_tlbsrch &
|
|
//~inst_tlbrd &
|
|
//~inst_tlbwr &
|
|
//~inst_tlbfill &
|
|
//~inst_invtlb &
|
|
//~inst_cacop &
|
|
//~inst_preld &
|
|
~inst_dbar &
|
|
~inst_ibar ;
|
|
|
|
|
|
|
|
// csr
|
|
assign csr_we = inst_csrwr | inst_csrxchg;
|
|
assign csr_op = {inst_csrrd,
|
|
inst_csrwr,
|
|
inst_csrxchg,
|
|
inst_rdcntid_w,
|
|
inst_rdcntvh_w,
|
|
inst_rdcntvl_w,
|
|
inst_sc_w
|
|
};
|
|
assign csr_addr = inst[23:10];
|
|
assign csr_wdata_sel = inst_csrxchg;
|
|
assign csr_vec_l = {25'b0, excp_adef, excp_ipe, excp_ine, inst_break, inst_syscall, inst_ertn, csr_has_int};
|
|
|
|
assign inst_valid = inst_add_w |
|
|
inst_sub_w |
|
|
inst_slt |
|
|
inst_sltu |
|
|
inst_nor |
|
|
inst_and |
|
|
inst_or |
|
|
inst_xor |
|
|
inst_sll_w |
|
|
inst_srl_w |
|
|
inst_sra_w |
|
|
inst_mul_w |
|
|
inst_mulh_w |
|
|
inst_mulh_wu |
|
|
inst_div_w |
|
|
inst_mod_w |
|
|
inst_div_wu |
|
|
inst_mod_wu |
|
|
inst_break |
|
|
inst_syscall |
|
|
inst_slli_w |
|
|
inst_srli_w |
|
|
inst_srai_w |
|
|
//inst_idle |
|
|
inst_slti |
|
|
inst_sltui |
|
|
inst_addi_w |
|
|
inst_andi |
|
|
inst_ori |
|
|
inst_xori |
|
|
inst_ld_b |
|
|
inst_ld_h |
|
|
inst_ld_w |
|
|
inst_st_b |
|
|
inst_st_h |
|
|
inst_st_w |
|
|
inst_ld_bu |
|
|
inst_ld_hu |
|
|
inst_ll_w |
|
|
inst_sc_w |
|
|
inst_jirl |
|
|
inst_b |
|
|
inst_bl |
|
|
inst_beq |
|
|
inst_bne |
|
|
inst_blt |
|
|
inst_bge |
|
|
inst_bltu |
|
|
inst_bgeu |
|
|
inst_lu12i_w |
|
|
inst_pcaddu12i |
|
|
inst_csrrd |
|
|
inst_csrwr |
|
|
inst_csrxchg |
|
|
inst_rdcntid_w |
|
|
inst_rdcntvh_w |
|
|
inst_rdcntvl_w |
|
|
inst_ertn |
|
|
//inst_cacop |
|
|
//inst_preld |
|
|
inst_dbar |
|
|
inst_ibar ;
|
|
//inst_tlbsrch |
|
|
//inst_tlbrd |
|
|
//inst_tlbwr |
|
|
//inst_tlbfill |
|
|
//(inst_invtlb && (rd == 5'd0 ||
|
|
// rd == 5'd1 ||
|
|
// rd == 5'd2 ||
|
|
// rd == 5'd3 ||
|
|
// rd == 5'd4 ||
|
|
// rd == 5'd5 ||
|
|
// rd == 5'd6 )); //invtlb valid op
|
|
|
|
|
|
assign excp_ine = ~inst_valid;
|
|
|
|
assign kernel_inst = inst_csrrd |
|
|
inst_csrwr |
|
|
inst_csrxchg |
|
|
//inst_cacop |
|
|
//inst_tlbsrch |
|
|
//inst_tlbrd |
|
|
//inst_tlbwr |
|
|
//inst_tlbfill |
|
|
//inst_invtlb |
|
|
inst_ertn ;
|
|
//inst_idle ;
|
|
|
|
assign excp_ipe = kernel_inst && (csr_plv == 2'b11);
|
|
endmodule
|