UnbalancedCat/neulacpu
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0f65e8f6ccdc08cfad3f3a861e534502f64642ee
neulacpu/lacpu/rtl/mycpu
History
UnbalancedCat 0f65e8f6cc final submit
2023-08-17 11:31:28 +08:00
..
alu.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
axi_ctrl.v
[Modified] fix axi, pass func & pref test, but down to 85MHz
2023-08-01 14:30:11 +08:00
bru.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
cache_data.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
cache_tag.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
csr.v
final submit
2023-08-17 11:31:28 +08:00
csr.vh
final submit
2023-08-17 11:31:28 +08:00
dcache.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
div.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
dt_stage.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
exe_stage.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
forward.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00
icache.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
id_stage.v
final submit
2023-08-17 11:31:28 +08:00
if_stage.v
final submit
2023-08-17 11:31:28 +08:00
inst_decoder.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
lsu.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mem_stage.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
mmu.v
[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test
2023-07-31 16:05:29 +08:00
mul_div_lock.v
[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test
2023-07-31 16:05:29 +08:00
mul_div_top.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
mul.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
mycpu_core.v
final submit
2023-08-17 11:31:28 +08:00
mycpu_top.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
pip_ctrl.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
regfile.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
tools.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
uncache.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
wb_stage.v
[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
2023-07-29 21:16:28 +08:00