124 lines
3.5 KiB
Verilog
124 lines
3.5 KiB
Verilog
`default_nettype wire
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module uncache
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#(
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parameter STAGE_WD = 4,
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parameter WAIT = 4'b1000,
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parameter IDLE = 4'b0001,
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parameter BUFFER = 4'b0010
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)
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(
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input clk,
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input resetn,
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output stallreq,
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input conf_en,
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input [ 3:0] conf_we,
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input [31:0] conf_addr,
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input [31:0] conf_wdata,
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output reg [31:0] conf_rdata,
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output reg axi_en, // en
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output reg [ 3:0] axi_wsel, // we
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output reg [31:0] axi_addr, // addr
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output reg [31:0] axi_wdata,
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input reload,
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input [31:0] axi_rdata
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);
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reg valid;
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reg finish;
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reg buffer_valid;
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reg [STAGE_WD -1:0] stage;
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wire conf_rd_req;
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wire conf_wr_req;
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assign conf_rd_req = conf_en & ~valid & ~(|conf_we);
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assign conf_wr_req = conf_en & ~valid & (|conf_we);
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assign stallreq = conf_rd_req & ~valid | conf_wr_req & buffer_valid & ~valid | stage[3];
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always @ (posedge clk) begin
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if (!resetn) begin
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valid <= 1'b0;
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end
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else if (finish) begin
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valid <= 1'b1;
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end
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else begin
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valid <= 1'b0;
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end
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end
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always @ (posedge clk) begin
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if (!resetn) begin
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conf_rdata <= 32'b0;
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end
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else if (reload) begin
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conf_rdata <= axi_rdata;
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end
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end
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always @ (posedge clk) begin
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if (!resetn) begin
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buffer_valid <= 1'b0;
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stage <= {{(STAGE_WD-1){1'b0}}, 1'b1};
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finish <= 1'b0;
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axi_en <= 1'b0;
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axi_wsel <= 4'b0;
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axi_addr <= 32'b0;
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axi_wdata <= 32'b0;
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end
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else begin
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case(1'b1)
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stage[0]:begin
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if (conf_rd_req & ~buffer_valid) begin
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axi_en <= 1'b1;
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axi_wsel <= conf_we;
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axi_addr <= conf_addr;
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axi_wdata <= conf_wdata;
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stage <= WAIT;
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end
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else if (conf_wr_req & ~buffer_valid) begin
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axi_en <= 1'b1;
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axi_wsel <= conf_we;
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axi_addr <= conf_addr;
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axi_wdata <= conf_wdata;
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buffer_valid <= 1'b1;
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// finish <= 1'b1;
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stage <= BUFFER;
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end
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end
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stage[1]:begin //BUFFER
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// finish <= 1'b0;
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if (reload) begin
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buffer_valid <= 1'b0;
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axi_en <= 1'b0;
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axi_wsel <= 4'b0;
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axi_addr <= 32'b0;
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axi_wdata <= 32'b0;
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stage <= IDLE;
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end
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end
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stage[3]:begin
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if (reload) begin
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axi_en <= 1'b0;
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axi_wsel <= 4'b0;
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axi_addr <= 32'b0;
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axi_wdata <= 32'b0;
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finish <= 1'b1;
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end
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else if (finish) begin
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finish <= 1'b0;
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stage <= {{(STAGE_WD-1){1'b0}}, 1'b1};
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end
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end
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default:begin
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stage <= {{(STAGE_WD-1){1'b0}}, 1'b1};
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end
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endcase
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end
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end
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endmodule |