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[Modified] pre submit file organization

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包焕垲
2023-08-04 16:10:30 +08:00
parent df11c3a4ab
commit f87199d467
35 changed files with 98 additions and 5939 deletions
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lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.dcp
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lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xci
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@@ -244,7 +244,7 @@
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>

192
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xml
View File

@@ -1457,11 +1457,11 @@
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<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
<spirit:value>Fri Aug 04 07:02:12 UTC 2023</spirit:value>
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<spirit:name>outputProductCRC</spirit:name>
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@@ -1477,11 +1477,11 @@
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<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
<spirit:value>Fri Aug 04 07:02:49 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
<spirit:value>9:2ebdaf5f</spirit:value>
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@@ -1492,7 +1492,7 @@
<spirit:parameters>
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<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
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@@ -1508,86 +1508,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
<spirit:value>Fri Aug 04 07:02:49 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:949760af</spirit:value>
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<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>data_bram_bank</spirit:modelName>
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<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
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<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>xilinx_project_archive</spirit:name>
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<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
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<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>xilinx_versioninformation</spirit:name>
<spirit:displayName>Version Information</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
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<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
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<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
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@@ -1601,11 +1526,11 @@
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Fri Aug 04 07:04:01 UTC 2023</spirit:value>
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@@ -1619,7 +1544,6 @@
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@@ -1642,7 +1566,6 @@
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@@ -1665,7 +1588,6 @@
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@@ -1688,7 +1610,6 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1715,7 +1636,6 @@
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@@ -1742,7 +1662,6 @@
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@@ -1769,7 +1688,6 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1796,7 +1714,6 @@
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@@ -1816,7 +1733,6 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1839,7 +1755,6 @@
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@@ -1862,7 +1777,6 @@
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1885,7 +1799,6 @@
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1912,7 +1825,6 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1939,7 +1851,6 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1966,7 +1877,6 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1993,7 +1903,6 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2013,7 +1922,6 @@
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2036,7 +1944,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2059,7 +1966,6 @@
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2082,7 +1988,6 @@
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@@ -2102,7 +2007,6 @@
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<spirit:typeName>std_logic</spirit:typeName>
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@@ -2126,7 +2030,6 @@
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@@ -2169,7 +2071,6 @@
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<spirit:typeName>std_logic</spirit:typeName>
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@@ -2215,7 +2115,6 @@
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@@ -2235,7 +2134,6 @@
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@@ -2255,7 +2153,6 @@
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@@ -2305,7 +2201,6 @@
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@@ -2332,7 +2227,6 @@
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@@ -2359,7 +2253,6 @@
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@@ -2386,7 +2279,6 @@
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@@ -2436,7 +2327,6 @@
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<spirit:typeName>std_logic</spirit:typeName>
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@@ -2483,7 +2372,6 @@
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@@ -2603,7 +2487,6 @@
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2872,7 +2745,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2896,7 +2768,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2920,7 +2791,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2940,7 +2810,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2960,7 +2829,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2980,7 +2848,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3003,7 +2870,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3026,7 +2892,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -3049,7 +2914,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3069,7 +2933,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3093,7 +2956,6 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -3569,42 +3431,6 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>simulation/blk_mem_gen_v8_4.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
<spirit:exportedName>blk_mem_gen_v8_4_4</spirit:exportedName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/data_bram_bank.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_project_archive_view_fileset</spirit:name>
<spirit:file>
<spirit:name>summary.log</spirit:name>
<spirit:userFileType>log</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>misc/blk_mem_gen_v8_4.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>doc/blk_mem_gen_v8_4_changelog.txt</spirit:name>
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>

4
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
View File

@@ -1,14 +1,14 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Mon Jul 31 07:02:57 2023
// Date : Fri Aug 4 15:04:01 2023
// Host : BHKLaptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
// Design : data_bram_bank
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a200tfbg676-1
// Device : xc7a200tfbg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

4
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.vhdl
View File

@@ -1,14 +1,14 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Mon Jul 31 07:02:57 2023
-- Date : Fri Aug 4 15:04:01 2023
-- Host : BHKLaptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.vhdl
-- Design : data_bram_bank
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tfbg676-1
-- Device : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

4
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
View File

@@ -1,13 +1,13 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Mon Jul 31 07:02:57 2023
// Date : Fri Aug 4 15:04:01 2023
// Host : BHKLaptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
// Design : data_bram_bank
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tfbg676-1
// Device : xc7a200tfbg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

4
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
View File

@@ -1,13 +1,13 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Mon Jul 31 07:02:57 2023
-- Date : Fri Aug 4 15:04:01 2023
-- Host : BHKLaptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
-- Design : data_bram_bank
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tfbg676-1
-- Device : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

207
lacpu/rtl/xilinx_ip/data_sram_bank/doc/blk_mem_gen_v8_4_changelog.txt
View File

@@ -1,207 +0,0 @@
2019.2:
* Version 8.4 (Rev. 4)
* Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations
2019.1.3:
* Version 8.4 (Rev. 3)
* No changes
2019.1.2:
* Version 8.4 (Rev. 3)
* No changes
2019.1.1:
* Version 8.4 (Rev. 3)
* No changes
2019.1:
* Version 8.4 (Rev. 3)
* General: Internal device family change, no functional changes
2018.3.1:
* Version 8.4 (Rev. 2)
* No changes
2018.3:
* Version 8.4 (Rev. 2)
* Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
* Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
* Other: Internal device family change, no functional changes
2018.2:
* Version 8.4 (Rev. 1)
* No changes
2018.1:
* Version 8.4 (Rev. 1)
* No changes
2017.4:
* Version 8.4 (Rev. 1)
* General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
2017.3:
* Version 8.4
* General: Safety Circuit option is enabled by default if reset option in any one port is enabled
2017.2:
* Version 8.3 (Rev. 6)
* No changes
2017.1:
* Version 8.3 (Rev. 6)
* General: Internal device family change, no functional changes
* General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
2016.4:
* Version 8.3 (Rev. 5)
* General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
2016.3:
* Version 8.3 (Rev. 4)
* Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
* Other: Enable support for future devices
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
2016.2:
* Version 8.3 (Rev. 3)
* updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
* Updated the IP to support the device package changes
2016.1:
* Version 8.3 (Rev. 2)
* Updated the IP to deliver only verilog behavioral model
* Updated the IP to support UltraRAM in IP Integrator
* Updated the IP to support the device package changes
2015.4.2:
* Version 8.3 (Rev. 1)
* No changes
2015.4.1:
* Version 8.3 (Rev. 1)
* No changes
2015.4:
* Version 8.3 (Rev. 1)
* Updated the IP to support the device package changes
2015.3:
* Version 8.3
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
* Simulation models are delivered in VHDL only
2015.2.1:
* Version 8.2 (Rev. 5)
* No changes
2015.2:
* Version 8.2 (Rev. 5)
* No changes
2015.1:
* Version 8.2 (Rev. 5)
* Delivering non encrypted behavioral models
* Supported memory depth is increased up to 1M words
* Added the power saving feature (RDADDRCHG) for ultrascale devices
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 8.2 (Rev. 4)
* Updated the IP to support the device package changes
2014.4:
* Version 8.2 (Rev. 3)
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
* Internal device family change, no functional changes
2014.3:
* Version 8.2 (Rev. 2)
* Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
* Fixed the GUI crash in Simple Dual Port RAM
* Added support of all write modes in Simple Dual Port RAM when ECC is not used
* Increased the supported depth to a maximum value of 256k
2014.2:
* Version 8.2 (Rev. 1)
* Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
2014.1:
* Version 8.2
* Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
* Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
* Added support of the dynamic power saving for ultra-scale devices
* Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
* Internal device family name change, no functional changes
2013.4:
* Version 8.1
* The Primitive output registers are made "ON" by default in the stand alone mode
* Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
* Added support for ultrascale devices
2013.3:
* Version 8.0 (Rev. 2)
* Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator.
* Improved GUI speed and responsivness, no functional changes
* Reduced synthesis and simulation warnings
* Added support for Cadence IES and Synopsys VCS simulators
* Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
* Changed BRAM Interface DIN and DOUT to match bus interface directions.
2013.2:
* Version 8.0 (Rev. 1)
* No Changes
2013.1:
* Version 8.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2019 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

150
lacpu/rtl/xilinx_ip/data_sram_bank/misc/blk_mem_gen_v8_4.vhd
View File

@@ -1,150 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_4_4 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_4_4;
architecture xilinx of blk_mem_gen_v8_4_4 is
begin
end
architecture xilinx;

220
lacpu/rtl/xilinx_ip/data_sram_bank/sim/data_bram_bank.v
View File

@@ -1,220 +0,0 @@
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
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// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module data_bram_bank (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [3 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [5 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [31 : 0] dina;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
blk_mem_gen_v8_4_4 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(8),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("data_bram_bank.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(4),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(64),
.C_READ_DEPTH_A(64),
.C_ADDRA_WIDTH(6),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(4),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(64),
.C_READ_DEPTH_B(64),
.C_ADDRB_WIDTH(6),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_READ_LATENCY_A(1),
.C_READ_LATENCY_B(1),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.53845 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(4'B0),
.addrb(6'B0),
.dinb(32'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(4'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule

4522
lacpu/rtl/xilinx_ip/data_sram_bank/simulation/blk_mem_gen_v8_4.v
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20
lacpu/rtl/xilinx_ip/data_sram_bank/summary.log
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@@ -1,20 +0,0 @@
User Configuration
--------------------------------------------------------------------------------
Algorithm : Minimum_Area
Memory Type : Single_Port_RAM
Port A Read Width : [32]
Port A Write Width : [32]
Memory Depth : [64]
----------------------------------------------------------------------------------
Block RAM resource(s) (18K BRAMs) : [1]
Block RAM resource(s) (36K BRAMs) : [0]
----------------------------------------------------------------------------------
Clock A Frequency : [100]
Port A Enable Rate : [100]
Port A Write Rate : [50]
----------------------------------------------------------------------------------
Estimated Power for IP : 3.53845 mW
----------------------------------------------------------------------------------