UnbalancedCat/neulacpu
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[Modified] pre submit file organization

Browse Source
This commit is contained in:
包焕垲
2023-08-04 16:10:30 +08:00
parent df11c3a4ab
commit f87199d467
35 changed files with 98 additions and 5939 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
lacpu/rtl/mycpu/csr.v
View File

@@ -63,9 +63,6 @@ module csr(
reg timer_en;
reg [63:0] timer_64;
// reg has_int_r;
// reg [ 1:0] plv_r;
wire inst_sc_w;
wire inst_csrrd;
wire inst_csrwr;
@@ -92,21 +89,6 @@ module csr(
wire va_error;
wire [31:0] bad_va;
// always @(posedge clk) begin
// if(reset) begin
// has_int_r <= 0;
// plv_r <= 0;
// end
// else begin
// has_int_r <= ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
// plv_r <= except_en & !inst_ertn ? 2'b0 :
// inst_ertn ? prmd[`PPLV] :
// csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] :
// crmd[`PLV];
// end
// end
// out TODO!
assign has_int_out = ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
assign plv_out = except_en & !inst_ertn ? 2'b0 :
inst_ertn ? prmd[`PPLV] :